1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include <rte_compat.h> 9 #include <rte_bitops.h> 10 11 #include "mlx5_glue.h" 12 #include "mlx5_prm.h" 13 14 /* This is limitation of libibverbs: in length variable type is u16. */ 15 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 16 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 17 18 struct mlx5_devx_counter_attr { 19 uint32_t pd_valid:1; 20 uint32_t pd:24; 21 uint32_t bulk_log_max_alloc:1; 22 union { 23 uint8_t flow_counter_bulk_log_size; 24 uint8_t bulk_n_128; 25 }; 26 }; 27 28 struct mlx5_devx_mkey_attr { 29 uint64_t addr; 30 uint64_t size; 31 uint32_t umem_id; 32 uint32_t pd; 33 uint32_t log_entity_size; 34 uint32_t pg_access:1; 35 uint32_t relaxed_ordering_write:1; 36 uint32_t relaxed_ordering_read:1; 37 uint32_t umr_en:1; 38 uint32_t crypto_en:2; 39 uint32_t set_remote_rw:1; 40 struct mlx5_klm *klm_array; 41 int klm_num; 42 }; 43 44 /* HCA qos attributes. */ 45 struct mlx5_hca_qos_attr { 46 uint32_t sup:1; /* Whether QOS is supported. */ 47 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 48 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 49 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 50 uint32_t flow_meter:1; 51 /* 52 * Flow meter is supported, updated version. 53 * When flow_meter is 1, it indicates that REG_C sharing is supported. 54 * If flow_meter is 1, flow_meter_old is also 1. 55 * Using older driver versions, flow_meter_old can be 1 56 * while flow_meter is 0. 57 */ 58 uint32_t flow_meter_aso_sup:1; 59 /* Whether FLOW_METER_ASO Object is supported. */ 60 uint8_t log_max_flow_meter; 61 /* Power of the maximum supported meters. */ 62 uint8_t flow_meter_reg_c_ids; 63 /* Bitmap of the reg_Cs available for flow meter to use. */ 64 uint32_t log_meter_aso_granularity:5; 65 /* Power of the minimum allocation granularity Object. */ 66 uint32_t log_meter_aso_max_alloc:5; 67 /* Power of the maximum allocation granularity Object. */ 68 uint32_t log_max_num_meter_aso:5; 69 /* Power of the maximum number of supported objects. */ 70 71 }; 72 73 struct mlx5_hca_vdpa_attr { 74 uint8_t virtio_queue_type; 75 uint32_t valid:1; 76 uint32_t desc_tunnel_offload_type:1; 77 uint32_t eth_frame_offload_type:1; 78 uint32_t virtio_version_1_0:1; 79 uint32_t tso_ipv4:1; 80 uint32_t tso_ipv6:1; 81 uint32_t tx_csum:1; 82 uint32_t rx_csum:1; 83 uint32_t event_mode:3; 84 uint32_t log_doorbell_stride:5; 85 uint32_t log_doorbell_bar_size:5; 86 uint32_t queue_counters_valid:1; 87 uint32_t vnet_modify_ext:1; 88 uint32_t virtio_net_q_addr_modify:1; 89 uint32_t virtio_q_index_modify:1; 90 uint32_t max_num_virtio_queues; 91 struct { 92 uint32_t a; 93 uint32_t b; 94 } umems[3]; 95 uint64_t doorbell_bar_offset; 96 }; 97 98 struct mlx5_hca_flow_attr { 99 uint32_t tunnel_header_0_1; 100 uint32_t tunnel_header_2_3; 101 }; 102 103 /** 104 * Accumulate port PARSE_GRAPH_NODE capabilities from 105 * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables 106 */ 107 __extension__ 108 struct mlx5_hca_flex_attr { 109 uint32_t node_in; 110 uint32_t node_out; 111 uint16_t header_length_mode; 112 uint16_t sample_offset_mode; 113 uint8_t max_num_arc_in; 114 uint8_t max_num_arc_out; 115 uint8_t max_num_sample; 116 uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ 117 uint8_t sample_id_in_out:1; 118 uint16_t max_base_header_length; 119 uint8_t max_sample_base_offset; 120 uint16_t max_next_header_offset; 121 uint8_t header_length_mask_width; 122 }; 123 124 /* ISO C restricts enumerator values to range of 'int' */ 125 __extension__ 126 enum { 127 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1), 128 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2), 129 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3), 130 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4), 131 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5), 132 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6), 133 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7), 134 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8), 135 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9), 136 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10), 137 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11), 138 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12), 139 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31) 140 }; 141 142 enum { 143 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0), 144 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1), 145 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2) 146 }; 147 148 /* 149 * DWORD shift is the base for calculating header_length_field_mask 150 * value in the MLX5_GRAPH_NODE_LEN_FIELD mode. 151 */ 152 #define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02 153 154 static inline uint32_t 155 mlx5_hca_parse_graph_node_base_hdr_len_mask 156 (const struct mlx5_hca_flex_attr *attr) 157 { 158 return (1 << attr->header_length_mask_width) - 1; 159 } 160 161 /* HCA supports this number of time periods for LRO. */ 162 #define MLX5_LRO_NUM_SUPP_PERIODS 4 163 164 /* HCA attributes. */ 165 struct mlx5_hca_attr { 166 uint32_t eswitch_manager:1; 167 uint32_t flow_counters_dump:1; 168 uint32_t mem_rq_rmp:1; 169 uint32_t log_max_rmp:5; 170 uint32_t log_max_rqt_size:5; 171 uint32_t parse_graph_flex_node:1; 172 uint8_t flow_counter_bulk_alloc_bitmap; 173 uint32_t eth_net_offloads:1; 174 uint32_t eth_virt:1; 175 uint32_t wqe_vlan_insert:1; 176 uint32_t csum_cap:1; 177 uint32_t vlan_cap:1; 178 uint32_t wqe_inline_mode:2; 179 uint32_t vport_inline_mode:3; 180 uint32_t tunnel_stateless_geneve_rx:1; 181 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 182 uint32_t tunnel_stateless_gtp:1; 183 uint32_t max_lso_cap; 184 uint32_t scatter_fcs:1; 185 uint32_t lro_cap:1; 186 uint32_t tunnel_lro_gre:1; 187 uint32_t tunnel_lro_vxlan:1; 188 uint32_t tunnel_stateless_gre:1; 189 uint32_t tunnel_stateless_vxlan:1; 190 uint32_t swp:1; 191 uint32_t swp_csum:1; 192 uint32_t swp_lso:1; 193 uint32_t lro_max_msg_sz_mode:2; 194 uint32_t rq_delay_drop:1; 195 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 196 uint16_t lro_min_mss_size; 197 uint32_t flex_parser_protocols; 198 uint32_t max_geneve_tlv_options; 199 uint32_t max_geneve_tlv_option_data_len; 200 uint32_t hairpin:1; 201 uint32_t log_max_hairpin_queues:5; 202 uint32_t log_max_hairpin_wq_data_sz:5; 203 uint32_t log_max_hairpin_num_packets:5; 204 uint32_t hairpin_sq_wqe_bb_size:4; 205 uint32_t hairpin_sq_wq_in_host_mem:1; 206 uint32_t hairpin_data_buffer_locked:1; 207 uint32_t vhca_id:16; 208 uint32_t relaxed_ordering_write:1; 209 uint32_t relaxed_ordering_read:1; 210 uint32_t access_register_user:1; 211 uint32_t wqe_index_ignore:1; 212 uint32_t cross_channel:1; 213 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 214 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 215 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 216 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 217 uint32_t scatter_fcs_w_decap_disable:1; 218 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 219 uint32_t roce:1; 220 uint32_t wait_on_time:1; 221 uint32_t rq_ts_format:2; 222 uint32_t sq_ts_format:2; 223 uint32_t steering_format_version:4; 224 uint32_t qp_ts_format:2; 225 uint32_t regexp_params:1; 226 uint32_t regexp_version:3; 227 uint32_t reg_c_preserve:1; 228 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 229 uint32_t crypto:1; /* Crypto engine is supported. */ 230 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 231 uint32_t dek:1; /* General obj type DEK is supported. */ 232 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 233 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 234 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 235 uint32_t regexp_num_of_engines; 236 uint32_t log_max_ft_sampler_num:8; 237 uint32_t inner_ipv4_ihl:1; 238 uint32_t outer_ipv4_ihl:1; 239 uint32_t geneve_tlv_opt; 240 uint32_t cqe_compression:1; 241 uint32_t mini_cqe_resp_flow_tag:1; 242 uint32_t mini_cqe_resp_l3_l4_tag:1; 243 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 244 struct mlx5_hca_qos_attr qos; 245 struct mlx5_hca_vdpa_attr vdpa; 246 struct mlx5_hca_flow_attr flow; 247 struct mlx5_hca_flex_attr flex; 248 int log_max_qp_sz; 249 int log_max_cq_sz; 250 int log_max_qp; 251 int log_max_cq; 252 uint32_t log_max_pd; 253 uint32_t log_max_mrw_sz; 254 uint32_t log_max_srq; 255 uint32_t log_max_srq_sz; 256 uint32_t rss_ind_tbl_cap; 257 uint32_t mmo_dma_sq_en:1; 258 uint32_t mmo_compress_sq_en:1; 259 uint32_t mmo_decompress_sq_en:1; 260 uint32_t mmo_dma_qp_en:1; 261 uint32_t mmo_compress_qp_en:1; 262 uint32_t mmo_decompress_qp_en:1; 263 uint32_t mmo_regex_qp_en:1; 264 uint32_t mmo_regex_sq_en:1; 265 uint32_t compress_min_block_size:4; 266 uint32_t log_max_mmo_dma:5; 267 uint32_t log_max_mmo_compress:5; 268 uint32_t log_max_mmo_decompress:5; 269 uint32_t umr_modify_entity_size_disabled:1; 270 uint32_t umr_indirect_mkey_disabled:1; 271 uint32_t log_min_stride_wqe_sz:5; 272 uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */ 273 uint32_t crypto_wrapped_import_method:1; 274 uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */ 275 uint16_t max_wqe_sz_sq; 276 uint32_t set_reg_c:8; 277 uint32_t nic_flow_table:1; 278 uint32_t modify_outer_ip_ecn:1; 279 union { 280 uint32_t max_flow_counter; 281 struct { 282 uint16_t max_flow_counter_15_0; 283 uint16_t max_flow_counter_31_16; 284 }; 285 }; 286 uint32_t flow_counter_bulk_log_max_alloc:5; 287 uint32_t flow_counter_bulk_log_granularity:5; 288 uint32_t alloc_flow_counter_pd:1; 289 uint32_t flow_counter_access_aso:1; 290 uint32_t flow_access_aso_opc_mod:8; 291 }; 292 293 /* LAG Context. */ 294 struct mlx5_devx_lag_context { 295 uint32_t fdb_selection_mode:1; 296 uint32_t port_select_mode:3; 297 uint32_t lag_state:3; 298 uint32_t tx_remap_affinity_1:4; 299 uint32_t tx_remap_affinity_2:4; 300 }; 301 302 struct mlx5_devx_wq_attr { 303 uint32_t wq_type:4; 304 uint32_t wq_signature:1; 305 uint32_t end_padding_mode:2; 306 uint32_t cd_slave:1; 307 uint32_t hds_skip_first_sge:1; 308 uint32_t log2_hds_buf_size:3; 309 uint32_t page_offset:5; 310 uint32_t lwm:16; 311 uint32_t pd:24; 312 uint32_t uar_page:24; 313 uint64_t dbr_addr; 314 uint32_t hw_counter; 315 uint32_t sw_counter; 316 uint32_t log_wq_stride:4; 317 uint32_t log_wq_pg_sz:5; 318 uint32_t log_wq_sz:5; 319 uint32_t dbr_umem_valid:1; 320 uint32_t wq_umem_valid:1; 321 uint32_t log_hairpin_num_packets:5; 322 uint32_t log_hairpin_data_sz:5; 323 uint32_t single_wqe_log_num_of_strides:4; 324 uint32_t two_byte_shift_en:1; 325 uint32_t single_stride_log_num_of_bytes:3; 326 uint32_t dbr_umem_id; 327 uint32_t wq_umem_id; 328 uint64_t wq_umem_offset; 329 }; 330 331 /* Create RQ attributes structure, used by create RQ operation. */ 332 struct mlx5_devx_create_rq_attr { 333 uint32_t rlky:1; 334 uint32_t delay_drop_en:1; 335 uint32_t scatter_fcs:1; 336 uint32_t vsd:1; 337 uint32_t mem_rq_type:4; 338 uint32_t state:4; 339 uint32_t flush_in_error_en:1; 340 uint32_t hairpin:1; 341 uint32_t hairpin_data_buffer_type:3; 342 uint32_t ts_format:2; 343 uint32_t user_index:24; 344 uint32_t cqn:24; 345 uint32_t counter_set_id:8; 346 uint32_t rmpn:24; 347 struct mlx5_devx_wq_attr wq_attr; 348 }; 349 350 /* Modify RQ attributes structure, used by modify RQ operation. */ 351 struct mlx5_devx_modify_rq_attr { 352 uint32_t rqn:24; 353 uint32_t rq_state:4; /* Current RQ state. */ 354 uint32_t state:4; /* Required RQ state. */ 355 uint32_t scatter_fcs:1; 356 uint32_t vsd:1; 357 uint32_t counter_set_id:8; 358 uint32_t hairpin_peer_sq:24; 359 uint32_t hairpin_peer_vhca:16; 360 uint64_t modify_bitmask; 361 uint32_t lwm:16; /* Contained WQ lwm. */ 362 }; 363 364 /* Create RMP attributes structure, used by create RMP operation. */ 365 struct mlx5_devx_create_rmp_attr { 366 uint32_t rsvd0:8; 367 uint32_t state:4; 368 uint32_t rsvd1:20; 369 uint32_t basic_cyclic_rcv_wqe:1; 370 uint32_t rsvd4:31; 371 uint32_t rsvd8[10]; 372 struct mlx5_devx_wq_attr wq_attr; 373 }; 374 375 struct mlx5_rx_hash_field_select { 376 uint32_t l3_prot_type:1; 377 uint32_t l4_prot_type:1; 378 uint32_t selected_fields:30; 379 }; 380 381 /* TIR attributes structure, used by TIR operations. */ 382 struct mlx5_devx_tir_attr { 383 uint32_t disp_type:4; 384 uint32_t lro_timeout_period_usecs:16; 385 uint32_t lro_enable_mask:4; 386 uint32_t lro_max_msg_sz:8; 387 uint32_t inline_rqn:24; 388 uint32_t rx_hash_symmetric:1; 389 uint32_t tunneled_offload_en:1; 390 uint32_t indirect_table:24; 391 uint32_t rx_hash_fn:4; 392 uint32_t self_lb_block:2; 393 uint32_t transport_domain:24; 394 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 395 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 396 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 397 }; 398 399 /* TIR attributes structure, used by TIR modify. */ 400 struct mlx5_devx_modify_tir_attr { 401 uint32_t tirn:24; 402 uint64_t modify_bitmask; 403 struct mlx5_devx_tir_attr tir; 404 }; 405 406 /* RQT attributes structure, used by RQT operations. */ 407 struct mlx5_devx_rqt_attr { 408 uint8_t rq_type; 409 uint32_t rqt_max_size:16; 410 uint32_t rqt_actual_size:16; 411 uint32_t rq_list[]; 412 }; 413 414 /* TIS attributes structure. */ 415 struct mlx5_devx_tis_attr { 416 uint32_t strict_lag_tx_port_affinity:1; 417 uint32_t tls_en:1; 418 uint32_t lag_tx_port_affinity:4; 419 uint32_t prio:4; 420 uint32_t transport_domain:24; 421 }; 422 423 /* SQ attributes structure, used by SQ create operation. */ 424 struct mlx5_devx_create_sq_attr { 425 uint32_t rlky:1; 426 uint32_t cd_master:1; 427 uint32_t fre:1; 428 uint32_t flush_in_error_en:1; 429 uint32_t allow_multi_pkt_send_wqe:1; 430 uint32_t min_wqe_inline_mode:3; 431 uint32_t state:4; 432 uint32_t reg_umr:1; 433 uint32_t allow_swp:1; 434 uint32_t hairpin:1; 435 uint32_t non_wire:1; 436 uint32_t static_sq_wq:1; 437 uint32_t ts_format:2; 438 uint32_t hairpin_wq_buffer_type:3; 439 uint32_t user_index:24; 440 uint32_t cqn:24; 441 uint32_t packet_pacing_rate_limit_index:16; 442 uint32_t tis_lst_sz:16; 443 uint32_t tis_num:24; 444 struct mlx5_devx_wq_attr wq_attr; 445 }; 446 447 /* SQ attributes structure, used by SQ modify operation. */ 448 struct mlx5_devx_modify_sq_attr { 449 uint32_t sq_state:4; 450 uint32_t state:4; 451 uint32_t hairpin_peer_rq:24; 452 uint32_t hairpin_peer_vhca:16; 453 }; 454 455 456 /* CQ attributes structure, used by CQ operations. */ 457 struct mlx5_devx_cq_attr { 458 uint32_t q_umem_valid:1; 459 uint32_t db_umem_valid:1; 460 uint32_t use_first_only:1; 461 uint32_t overrun_ignore:1; 462 uint32_t cqe_comp_en:1; 463 uint32_t mini_cqe_res_format:2; 464 uint32_t mini_cqe_res_format_ext:2; 465 uint32_t log_cq_size:5; 466 uint32_t log_page_size:5; 467 uint32_t uar_page_id; 468 uint32_t q_umem_id; 469 uint64_t q_umem_offset; 470 uint32_t db_umem_id; 471 uint64_t db_umem_offset; 472 uint32_t eqn; 473 uint64_t db_addr; 474 }; 475 476 /* Virtq attributes structure, used by VIRTQ operations. */ 477 struct mlx5_devx_virtq_attr { 478 uint16_t hw_available_index; 479 uint16_t hw_used_index; 480 uint16_t q_size; 481 uint32_t pd:24; 482 uint32_t virtio_version_1_0:1; 483 uint32_t tso_ipv4:1; 484 uint32_t tso_ipv6:1; 485 uint32_t tx_csum:1; 486 uint32_t rx_csum:1; 487 uint32_t event_mode:3; 488 uint32_t state:4; 489 uint32_t hw_latency_mode:2; 490 uint32_t hw_max_latency_us:12; 491 uint32_t hw_max_pending_comp:16; 492 uint32_t dirty_bitmap_dump_enable:1; 493 uint32_t dirty_bitmap_mkey; 494 uint32_t dirty_bitmap_size; 495 uint32_t mkey; 496 uint32_t qp_id; 497 uint32_t queue_index; 498 uint32_t tis_id; 499 uint32_t counters_obj_id; 500 uint64_t dirty_bitmap_addr; 501 uint64_t mod_fields_bitmap; 502 uint64_t desc_addr; 503 uint64_t used_addr; 504 uint64_t available_addr; 505 struct { 506 uint32_t id; 507 uint32_t size; 508 uint64_t offset; 509 } umems[3]; 510 uint8_t error_type; 511 uint8_t q_type; 512 }; 513 514 515 struct mlx5_devx_qp_attr { 516 uint32_t pd:24; 517 uint32_t uar_index:24; 518 uint32_t cqn:24; 519 uint32_t log_page_size:5; 520 uint32_t num_of_receive_wqes:17; /* Must be power of 2. */ 521 uint32_t log_rq_stride:3; 522 uint32_t num_of_send_wqbbs:17; /* Must be power of 2. */ 523 uint32_t ts_format:2; 524 uint32_t dbr_umem_valid:1; 525 uint32_t dbr_umem_id; 526 uint64_t dbr_address; 527 uint32_t wq_umem_id; 528 uint64_t wq_umem_offset; 529 uint32_t user_index:24; 530 uint32_t mmo:1; 531 }; 532 533 struct mlx5_devx_virtio_q_couners_attr { 534 uint64_t received_desc; 535 uint64_t completed_desc; 536 uint32_t error_cqes; 537 uint32_t bad_desc_errors; 538 uint32_t exceed_max_chain; 539 uint32_t invalid_buffer; 540 }; 541 542 /* 543 * graph flow match sample attributes structure, 544 * used by flex parser operations. 545 */ 546 struct mlx5_devx_match_sample_attr { 547 uint32_t flow_match_sample_en:1; 548 uint32_t flow_match_sample_field_offset:16; 549 uint32_t flow_match_sample_offset_mode:4; 550 uint32_t flow_match_sample_field_offset_mask; 551 uint32_t flow_match_sample_field_offset_shift:4; 552 uint32_t flow_match_sample_field_base_offset:8; 553 uint32_t flow_match_sample_tunnel_mode:3; 554 uint32_t flow_match_sample_field_id; 555 }; 556 557 /* graph node arc attributes structure, used by flex parser operations. */ 558 struct mlx5_devx_graph_arc_attr { 559 uint32_t compare_condition_value:16; 560 uint32_t start_inner_tunnel:1; 561 uint32_t arc_parse_graph_node:8; 562 uint32_t parse_graph_node_handle; 563 }; 564 565 /* Maximal number of samples per graph node. */ 566 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 567 568 /* Maximal number of input/output arcs per graph node. */ 569 #define MLX5_GRAPH_NODE_ARC_NUM 8 570 571 /* parse graph node attributes structure, used by flex parser operations. */ 572 struct mlx5_devx_graph_node_attr { 573 uint32_t modify_field_select; 574 uint32_t header_length_mode:4; 575 uint32_t header_length_base_value:16; 576 uint32_t header_length_field_shift:4; 577 uint32_t header_length_field_offset:16; 578 uint32_t header_length_field_mask; 579 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 580 uint32_t next_header_field_offset:16; 581 uint32_t next_header_field_size:5; 582 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 583 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 584 }; 585 586 /* Encryption key size is up to 1024 bit, 128 bytes. */ 587 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 588 589 struct mlx5_devx_dek_attr { 590 uint32_t key_size:4; 591 uint32_t has_keytag:1; 592 uint32_t key_purpose:4; 593 uint32_t pd:24; 594 uint64_t opaque; 595 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 596 }; 597 598 struct mlx5_devx_import_kek_attr { 599 uint64_t modify_field_select; 600 uint32_t state:8; 601 uint32_t key_size:4; 602 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 603 }; 604 605 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 606 607 struct mlx5_devx_credential_attr { 608 uint64_t modify_field_select; 609 uint32_t state:8; 610 uint32_t credential_role:8; 611 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 612 }; 613 614 struct mlx5_devx_crypto_login_attr { 615 uint64_t modify_field_select; 616 uint32_t credential_pointer:24; 617 uint32_t session_import_kek_ptr:24; 618 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 619 }; 620 621 /* mlx5_devx_cmds.c */ 622 623 __rte_internal 624 struct mlx5_devx_obj * 625 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 626 struct mlx5_devx_counter_attr *attr); 627 628 __rte_internal 629 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 630 uint32_t bulk_sz); 631 __rte_internal 632 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 633 __rte_internal 634 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 635 int clear, uint32_t n_counters, 636 uint64_t *pkts, uint64_t *bytes, 637 uint32_t mkey, void *addr, 638 void *cmd_comp, 639 uint64_t async_id); 640 __rte_internal 641 int mlx5_devx_cmd_query_hca_attr(void *ctx, 642 struct mlx5_hca_attr *attr); 643 __rte_internal 644 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 645 struct mlx5_devx_mkey_attr *attr); 646 __rte_internal 647 int mlx5_devx_get_out_command_status(void *out); 648 __rte_internal 649 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 650 uint32_t *tis_td); 651 __rte_internal 652 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 653 struct mlx5_devx_create_rq_attr *rq_attr, 654 int socket); 655 __rte_internal 656 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 657 struct mlx5_devx_modify_rq_attr *rq_attr); 658 __rte_internal 659 struct mlx5_devx_obj *mlx5_devx_cmd_create_rmp(void *ctx, 660 struct mlx5_devx_create_rmp_attr *rq_attr, int socket); 661 __rte_internal 662 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 663 struct mlx5_devx_tir_attr *tir_attr); 664 __rte_internal 665 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 666 struct mlx5_devx_rqt_attr *rqt_attr); 667 __rte_internal 668 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 669 struct mlx5_devx_create_sq_attr *sq_attr); 670 __rte_internal 671 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 672 struct mlx5_devx_modify_sq_attr *sq_attr); 673 __rte_internal 674 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 675 struct mlx5_devx_tis_attr *tis_attr); 676 __rte_internal 677 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 678 __rte_internal 679 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 680 FILE *file); 681 __rte_internal 682 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 683 __rte_internal 684 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 685 struct mlx5_devx_cq_attr *attr); 686 __rte_internal 687 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 688 struct mlx5_devx_virtq_attr *attr); 689 __rte_internal 690 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 691 struct mlx5_devx_virtq_attr *attr); 692 __rte_internal 693 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 694 struct mlx5_devx_virtq_attr *attr); 695 __rte_internal 696 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 697 struct mlx5_devx_qp_attr *attr); 698 __rte_internal 699 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 700 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 701 __rte_internal 702 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 703 struct mlx5_devx_rqt_attr *rqt_attr); 704 __rte_internal 705 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 706 struct mlx5_devx_modify_tir_attr *tir_attr); 707 __rte_internal 708 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 709 uint32_t ids[], uint32_t num); 710 711 __rte_internal 712 struct mlx5_devx_obj * 713 mlx5_devx_cmd_create_flex_parser(void *ctx, 714 struct mlx5_devx_graph_node_attr *data); 715 716 __rte_internal 717 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 718 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 719 720 __rte_internal 721 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 722 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 723 724 __rte_internal 725 struct mlx5_devx_obj * 726 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 727 uint16_t class, uint8_t type, uint8_t len); 728 729 /** 730 * Create virtio queue counters object DevX API. 731 * 732 * @param[in] ctx 733 * Device context. 734 735 * @return 736 * The DevX object created, NULL otherwise and rte_errno is set. 737 */ 738 __rte_internal 739 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 740 741 /** 742 * Query virtio queue counters object using DevX API. 743 * 744 * @param[in] couners_obj 745 * Pointer to virtq object structure. 746 * @param [in/out] attr 747 * Pointer to virtio queue counters attributes structure. 748 * 749 * @return 750 * 0 on success, a negative errno value otherwise and rte_errno is set. 751 */ 752 __rte_internal 753 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 754 struct mlx5_devx_virtio_q_couners_attr *attr); 755 __rte_internal 756 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 757 uint32_t pd); 758 __rte_internal 759 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 760 761 __rte_internal 762 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 763 764 __rte_internal 765 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 766 __rte_internal 767 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 768 uint32_t *out_of_buffers); 769 __rte_internal 770 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 771 uint32_t pd, uint32_t log_obj_size); 772 773 /** 774 * Create general object of type FLOW_METER_ASO using DevX API.. 775 * 776 * @param[in] ctx 777 * Device context. 778 * @param [in] pd 779 * PD value to associate the FLOW_METER_ASO object with. 780 * @param [in] log_obj_size 781 * log_obj_size define to allocate number of 2 * meters 782 * in one FLOW_METER_ASO object. 783 * 784 * @return 785 * The DevX object created, NULL otherwise and rte_errno is set. 786 */ 787 __rte_internal 788 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 789 uint32_t pd, uint32_t log_obj_size); 790 __rte_internal 791 struct mlx5_devx_obj * 792 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 793 794 __rte_internal 795 struct mlx5_devx_obj * 796 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 797 struct mlx5_devx_import_kek_attr *attr); 798 799 __rte_internal 800 struct mlx5_devx_obj * 801 mlx5_devx_cmd_create_credential_obj(void *ctx, 802 struct mlx5_devx_credential_attr *attr); 803 804 __rte_internal 805 struct mlx5_devx_obj * 806 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 807 struct mlx5_devx_crypto_login_attr *attr); 808 809 __rte_internal 810 int 811 mlx5_devx_cmd_query_lag(void *ctx, 812 struct mlx5_devx_lag_context *lag_ctx); 813 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 814