1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include <rte_compat.h> 9 10 #include "mlx5_glue.h" 11 #include "mlx5_prm.h" 12 13 /* This is limitation of libibverbs: in length variable type is u16. */ 14 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 15 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 16 17 struct mlx5_devx_mkey_attr { 18 uint64_t addr; 19 uint64_t size; 20 uint32_t umem_id; 21 uint32_t pd; 22 uint32_t log_entity_size; 23 uint32_t pg_access:1; 24 uint32_t relaxed_ordering_write:1; 25 uint32_t relaxed_ordering_read:1; 26 uint32_t umr_en:1; 27 uint32_t crypto_en:2; 28 uint32_t set_remote_rw:1; 29 struct mlx5_klm *klm_array; 30 int klm_num; 31 }; 32 33 /* HCA qos attributes. */ 34 struct mlx5_hca_qos_attr { 35 uint32_t sup:1; /* Whether QOS is supported. */ 36 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 37 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 38 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 39 uint32_t flow_meter:1; 40 /* 41 * Flow meter is supported, updated version. 42 * When flow_meter is 1, it indicates that REG_C sharing is supported. 43 * If flow_meter is 1, flow_meter_old is also 1. 44 * Using older driver versions, flow_meter_old can be 1 45 * while flow_meter is 0. 46 */ 47 uint32_t flow_meter_aso_sup:1; 48 /* Whether FLOW_METER_ASO Object is supported. */ 49 uint8_t log_max_flow_meter; 50 /* Power of the maximum supported meters. */ 51 uint8_t flow_meter_reg_c_ids; 52 /* Bitmap of the reg_Cs available for flow meter to use. */ 53 uint32_t log_meter_aso_granularity:5; 54 /* Power of the minimum allocation granularity Object. */ 55 uint32_t log_meter_aso_max_alloc:5; 56 /* Power of the maximum allocation granularity Object. */ 57 uint32_t log_max_num_meter_aso:5; 58 /* Power of the maximum number of supported objects. */ 59 60 }; 61 62 struct mlx5_hca_vdpa_attr { 63 uint8_t virtio_queue_type; 64 uint32_t valid:1; 65 uint32_t desc_tunnel_offload_type:1; 66 uint32_t eth_frame_offload_type:1; 67 uint32_t virtio_version_1_0:1; 68 uint32_t tso_ipv4:1; 69 uint32_t tso_ipv6:1; 70 uint32_t tx_csum:1; 71 uint32_t rx_csum:1; 72 uint32_t event_mode:3; 73 uint32_t log_doorbell_stride:5; 74 uint32_t log_doorbell_bar_size:5; 75 uint32_t queue_counters_valid:1; 76 uint32_t max_num_virtio_queues; 77 struct { 78 uint32_t a; 79 uint32_t b; 80 } umems[3]; 81 uint64_t doorbell_bar_offset; 82 }; 83 84 struct mlx5_hca_flow_attr { 85 uint32_t tunnel_header_0_1; 86 uint32_t tunnel_header_2_3; 87 }; 88 89 /* HCA supports this number of time periods for LRO. */ 90 #define MLX5_LRO_NUM_SUPP_PERIODS 4 91 92 /* HCA attributes. */ 93 struct mlx5_hca_attr { 94 uint32_t eswitch_manager:1; 95 uint32_t flow_counters_dump:1; 96 uint32_t log_max_rqt_size:5; 97 uint32_t parse_graph_flex_node:1; 98 uint8_t flow_counter_bulk_alloc_bitmap; 99 uint32_t eth_net_offloads:1; 100 uint32_t eth_virt:1; 101 uint32_t wqe_vlan_insert:1; 102 uint32_t csum_cap:1; 103 uint32_t vlan_cap:1; 104 uint32_t wqe_inline_mode:2; 105 uint32_t vport_inline_mode:3; 106 uint32_t tunnel_stateless_geneve_rx:1; 107 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 108 uint32_t tunnel_stateless_gtp:1; 109 uint32_t max_lso_cap; 110 uint32_t scatter_fcs:1; 111 uint32_t lro_cap:1; 112 uint32_t tunnel_lro_gre:1; 113 uint32_t tunnel_lro_vxlan:1; 114 uint32_t tunnel_stateless_gre:1; 115 uint32_t tunnel_stateless_vxlan:1; 116 uint32_t swp:1; 117 uint32_t swp_csum:1; 118 uint32_t swp_lso:1; 119 uint32_t lro_max_msg_sz_mode:2; 120 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 121 uint16_t lro_min_mss_size; 122 uint32_t flex_parser_protocols; 123 uint32_t max_geneve_tlv_options; 124 uint32_t max_geneve_tlv_option_data_len; 125 uint32_t hairpin:1; 126 uint32_t log_max_hairpin_queues:5; 127 uint32_t log_max_hairpin_wq_data_sz:5; 128 uint32_t log_max_hairpin_num_packets:5; 129 uint32_t vhca_id:16; 130 uint32_t relaxed_ordering_write:1; 131 uint32_t relaxed_ordering_read:1; 132 uint32_t access_register_user:1; 133 uint32_t wqe_index_ignore:1; 134 uint32_t cross_channel:1; 135 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 136 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 137 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 138 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 139 uint32_t scatter_fcs_w_decap_disable:1; 140 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 141 uint32_t roce:1; 142 uint32_t rq_ts_format:2; 143 uint32_t sq_ts_format:2; 144 uint32_t steering_format_version:4; 145 uint32_t qp_ts_format:2; 146 uint32_t regex:1; 147 uint32_t reg_c_preserve:1; 148 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 149 uint32_t crypto:1; /* Crypto engine is supported. */ 150 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 151 uint32_t dek:1; /* General obj type DEK is supported. */ 152 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 153 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 154 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 155 uint32_t regexp_num_of_engines; 156 uint32_t log_max_ft_sampler_num:8; 157 uint32_t inner_ipv4_ihl:1; 158 uint32_t outer_ipv4_ihl:1; 159 uint32_t geneve_tlv_opt; 160 uint32_t cqe_compression:1; 161 uint32_t mini_cqe_resp_flow_tag:1; 162 uint32_t mini_cqe_resp_l3_l4_tag:1; 163 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 164 struct mlx5_hca_qos_attr qos; 165 struct mlx5_hca_vdpa_attr vdpa; 166 struct mlx5_hca_flow_attr flow; 167 int log_max_qp_sz; 168 int log_max_cq_sz; 169 int log_max_qp; 170 int log_max_cq; 171 uint32_t log_max_pd; 172 uint32_t log_max_mrw_sz; 173 uint32_t log_max_srq; 174 uint32_t log_max_srq_sz; 175 uint32_t rss_ind_tbl_cap; 176 uint32_t mmo_dma_sq_en:1; 177 uint32_t mmo_compress_sq_en:1; 178 uint32_t mmo_decompress_sq_en:1; 179 uint32_t mmo_dma_qp_en:1; 180 uint32_t mmo_compress_qp_en:1; 181 uint32_t mmo_decompress_qp_en:1; 182 uint32_t mmo_regex_qp_en:1; 183 uint32_t mmo_regex_sq_en:1; 184 uint32_t compress_min_block_size:4; 185 uint32_t log_max_mmo_dma:5; 186 uint32_t log_max_mmo_compress:5; 187 uint32_t log_max_mmo_decompress:5; 188 uint32_t umr_modify_entity_size_disabled:1; 189 uint32_t umr_indirect_mkey_disabled:1; 190 }; 191 192 /* LAG Context. */ 193 struct mlx5_devx_lag_context { 194 uint32_t fdb_selection_mode:1; 195 uint32_t port_select_mode:3; 196 uint32_t lag_state:3; 197 uint32_t tx_remap_affinity_1:4; 198 uint32_t tx_remap_affinity_2:4; 199 }; 200 201 struct mlx5_devx_wq_attr { 202 uint32_t wq_type:4; 203 uint32_t wq_signature:1; 204 uint32_t end_padding_mode:2; 205 uint32_t cd_slave:1; 206 uint32_t hds_skip_first_sge:1; 207 uint32_t log2_hds_buf_size:3; 208 uint32_t page_offset:5; 209 uint32_t lwm:16; 210 uint32_t pd:24; 211 uint32_t uar_page:24; 212 uint64_t dbr_addr; 213 uint32_t hw_counter; 214 uint32_t sw_counter; 215 uint32_t log_wq_stride:4; 216 uint32_t log_wq_pg_sz:5; 217 uint32_t log_wq_sz:5; 218 uint32_t dbr_umem_valid:1; 219 uint32_t wq_umem_valid:1; 220 uint32_t log_hairpin_num_packets:5; 221 uint32_t log_hairpin_data_sz:5; 222 uint32_t single_wqe_log_num_of_strides:4; 223 uint32_t two_byte_shift_en:1; 224 uint32_t single_stride_log_num_of_bytes:3; 225 uint32_t dbr_umem_id; 226 uint32_t wq_umem_id; 227 uint64_t wq_umem_offset; 228 }; 229 230 /* Create RQ attributes structure, used by create RQ operation. */ 231 struct mlx5_devx_create_rq_attr { 232 uint32_t rlky:1; 233 uint32_t delay_drop_en:1; 234 uint32_t scatter_fcs:1; 235 uint32_t vsd:1; 236 uint32_t mem_rq_type:4; 237 uint32_t state:4; 238 uint32_t flush_in_error_en:1; 239 uint32_t hairpin:1; 240 uint32_t ts_format:2; 241 uint32_t user_index:24; 242 uint32_t cqn:24; 243 uint32_t counter_set_id:8; 244 uint32_t rmpn:24; 245 struct mlx5_devx_wq_attr wq_attr; 246 }; 247 248 /* Modify RQ attributes structure, used by modify RQ operation. */ 249 struct mlx5_devx_modify_rq_attr { 250 uint32_t rqn:24; 251 uint32_t rq_state:4; /* Current RQ state. */ 252 uint32_t state:4; /* Required RQ state. */ 253 uint32_t scatter_fcs:1; 254 uint32_t vsd:1; 255 uint32_t counter_set_id:8; 256 uint32_t hairpin_peer_sq:24; 257 uint32_t hairpin_peer_vhca:16; 258 uint64_t modify_bitmask; 259 uint32_t lwm:16; /* Contained WQ lwm. */ 260 }; 261 262 struct mlx5_rx_hash_field_select { 263 uint32_t l3_prot_type:1; 264 uint32_t l4_prot_type:1; 265 uint32_t selected_fields:30; 266 }; 267 268 /* TIR attributes structure, used by TIR operations. */ 269 struct mlx5_devx_tir_attr { 270 uint32_t disp_type:4; 271 uint32_t lro_timeout_period_usecs:16; 272 uint32_t lro_enable_mask:4; 273 uint32_t lro_max_msg_sz:8; 274 uint32_t inline_rqn:24; 275 uint32_t rx_hash_symmetric:1; 276 uint32_t tunneled_offload_en:1; 277 uint32_t indirect_table:24; 278 uint32_t rx_hash_fn:4; 279 uint32_t self_lb_block:2; 280 uint32_t transport_domain:24; 281 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 282 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 283 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 284 }; 285 286 /* TIR attributes structure, used by TIR modify. */ 287 struct mlx5_devx_modify_tir_attr { 288 uint32_t tirn:24; 289 uint64_t modify_bitmask; 290 struct mlx5_devx_tir_attr tir; 291 }; 292 293 /* RQT attributes structure, used by RQT operations. */ 294 struct mlx5_devx_rqt_attr { 295 uint8_t rq_type; 296 uint32_t rqt_max_size:16; 297 uint32_t rqt_actual_size:16; 298 uint32_t rq_list[]; 299 }; 300 301 /* TIS attributes structure. */ 302 struct mlx5_devx_tis_attr { 303 uint32_t strict_lag_tx_port_affinity:1; 304 uint32_t tls_en:1; 305 uint32_t lag_tx_port_affinity:4; 306 uint32_t prio:4; 307 uint32_t transport_domain:24; 308 }; 309 310 /* SQ attributes structure, used by SQ create operation. */ 311 struct mlx5_devx_create_sq_attr { 312 uint32_t rlky:1; 313 uint32_t cd_master:1; 314 uint32_t fre:1; 315 uint32_t flush_in_error_en:1; 316 uint32_t allow_multi_pkt_send_wqe:1; 317 uint32_t min_wqe_inline_mode:3; 318 uint32_t state:4; 319 uint32_t reg_umr:1; 320 uint32_t allow_swp:1; 321 uint32_t hairpin:1; 322 uint32_t non_wire:1; 323 uint32_t static_sq_wq:1; 324 uint32_t ts_format:2; 325 uint32_t user_index:24; 326 uint32_t cqn:24; 327 uint32_t packet_pacing_rate_limit_index:16; 328 uint32_t tis_lst_sz:16; 329 uint32_t tis_num:24; 330 struct mlx5_devx_wq_attr wq_attr; 331 }; 332 333 /* SQ attributes structure, used by SQ modify operation. */ 334 struct mlx5_devx_modify_sq_attr { 335 uint32_t sq_state:4; 336 uint32_t state:4; 337 uint32_t hairpin_peer_rq:24; 338 uint32_t hairpin_peer_vhca:16; 339 }; 340 341 342 /* CQ attributes structure, used by CQ operations. */ 343 struct mlx5_devx_cq_attr { 344 uint32_t q_umem_valid:1; 345 uint32_t db_umem_valid:1; 346 uint32_t use_first_only:1; 347 uint32_t overrun_ignore:1; 348 uint32_t cqe_comp_en:1; 349 uint32_t mini_cqe_res_format:2; 350 uint32_t mini_cqe_res_format_ext:2; 351 uint32_t log_cq_size:5; 352 uint32_t log_page_size:5; 353 uint32_t uar_page_id; 354 uint32_t q_umem_id; 355 uint64_t q_umem_offset; 356 uint32_t db_umem_id; 357 uint64_t db_umem_offset; 358 uint32_t eqn; 359 uint64_t db_addr; 360 }; 361 362 /* Virtq attributes structure, used by VIRTQ operations. */ 363 struct mlx5_devx_virtq_attr { 364 uint16_t hw_available_index; 365 uint16_t hw_used_index; 366 uint16_t q_size; 367 uint32_t pd:24; 368 uint32_t virtio_version_1_0:1; 369 uint32_t tso_ipv4:1; 370 uint32_t tso_ipv6:1; 371 uint32_t tx_csum:1; 372 uint32_t rx_csum:1; 373 uint32_t event_mode:3; 374 uint32_t state:4; 375 uint32_t hw_latency_mode:2; 376 uint32_t hw_max_latency_us:12; 377 uint32_t hw_max_pending_comp:16; 378 uint32_t dirty_bitmap_dump_enable:1; 379 uint32_t dirty_bitmap_mkey; 380 uint32_t dirty_bitmap_size; 381 uint32_t mkey; 382 uint32_t qp_id; 383 uint32_t queue_index; 384 uint32_t tis_id; 385 uint32_t counters_obj_id; 386 uint64_t dirty_bitmap_addr; 387 uint64_t type; 388 uint64_t desc_addr; 389 uint64_t used_addr; 390 uint64_t available_addr; 391 struct { 392 uint32_t id; 393 uint32_t size; 394 uint64_t offset; 395 } umems[3]; 396 uint8_t error_type; 397 }; 398 399 400 struct mlx5_devx_qp_attr { 401 uint32_t pd:24; 402 uint32_t uar_index:24; 403 uint32_t cqn:24; 404 uint32_t log_page_size:5; 405 uint32_t rq_size:17; /* Must be power of 2. */ 406 uint32_t log_rq_stride:3; 407 uint32_t sq_size:17; /* Must be power of 2. */ 408 uint32_t ts_format:2; 409 uint32_t dbr_umem_valid:1; 410 uint32_t dbr_umem_id; 411 uint64_t dbr_address; 412 uint32_t wq_umem_id; 413 uint64_t wq_umem_offset; 414 uint32_t user_index:24; 415 uint32_t mmo:1; 416 }; 417 418 struct mlx5_devx_virtio_q_couners_attr { 419 uint64_t received_desc; 420 uint64_t completed_desc; 421 uint32_t error_cqes; 422 uint32_t bad_desc_errors; 423 uint32_t exceed_max_chain; 424 uint32_t invalid_buffer; 425 }; 426 427 /* 428 * graph flow match sample attributes structure, 429 * used by flex parser operations. 430 */ 431 struct mlx5_devx_match_sample_attr { 432 uint32_t flow_match_sample_en:1; 433 uint32_t flow_match_sample_field_offset:16; 434 uint32_t flow_match_sample_offset_mode:4; 435 uint32_t flow_match_sample_field_offset_mask; 436 uint32_t flow_match_sample_field_offset_shift:4; 437 uint32_t flow_match_sample_field_base_offset:8; 438 uint32_t flow_match_sample_tunnel_mode:3; 439 uint32_t flow_match_sample_field_id; 440 }; 441 442 /* graph node arc attributes structure, used by flex parser operations. */ 443 struct mlx5_devx_graph_arc_attr { 444 uint32_t compare_condition_value:16; 445 uint32_t start_inner_tunnel:1; 446 uint32_t arc_parse_graph_node:8; 447 uint32_t parse_graph_node_handle; 448 }; 449 450 /* Maximal number of samples per graph node. */ 451 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 452 453 /* Maximal number of input/output arcs per graph node. */ 454 #define MLX5_GRAPH_NODE_ARC_NUM 8 455 456 /* parse graph node attributes structure, used by flex parser operations. */ 457 struct mlx5_devx_graph_node_attr { 458 uint32_t modify_field_select; 459 uint32_t header_length_mode:4; 460 uint32_t header_length_base_value:16; 461 uint32_t header_length_field_shift:4; 462 uint32_t header_length_field_offset:16; 463 uint32_t header_length_field_mask; 464 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 465 uint32_t next_header_field_offset:16; 466 uint32_t next_header_field_size:5; 467 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 468 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 469 }; 470 471 /* Encryption key size is up to 1024 bit, 128 bytes. */ 472 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 473 474 struct mlx5_devx_dek_attr { 475 uint32_t key_size:4; 476 uint32_t has_keytag:1; 477 uint32_t key_purpose:4; 478 uint32_t pd:24; 479 uint64_t opaque; 480 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 481 }; 482 483 struct mlx5_devx_import_kek_attr { 484 uint64_t modify_field_select; 485 uint32_t state:8; 486 uint32_t key_size:4; 487 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 488 }; 489 490 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 491 492 struct mlx5_devx_credential_attr { 493 uint64_t modify_field_select; 494 uint32_t state:8; 495 uint32_t credential_role:8; 496 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 497 }; 498 499 struct mlx5_devx_crypto_login_attr { 500 uint64_t modify_field_select; 501 uint32_t credential_pointer:24; 502 uint32_t session_import_kek_ptr:24; 503 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 504 }; 505 506 /* mlx5_devx_cmds.c */ 507 508 __rte_internal 509 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 510 uint32_t bulk_sz); 511 __rte_internal 512 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 513 __rte_internal 514 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 515 int clear, uint32_t n_counters, 516 uint64_t *pkts, uint64_t *bytes, 517 uint32_t mkey, void *addr, 518 void *cmd_comp, 519 uint64_t async_id); 520 __rte_internal 521 int mlx5_devx_cmd_query_hca_attr(void *ctx, 522 struct mlx5_hca_attr *attr); 523 __rte_internal 524 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 525 struct mlx5_devx_mkey_attr *attr); 526 __rte_internal 527 int mlx5_devx_get_out_command_status(void *out); 528 __rte_internal 529 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 530 uint32_t *tis_td); 531 __rte_internal 532 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 533 struct mlx5_devx_create_rq_attr *rq_attr, 534 int socket); 535 __rte_internal 536 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 537 struct mlx5_devx_modify_rq_attr *rq_attr); 538 __rte_internal 539 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 540 struct mlx5_devx_tir_attr *tir_attr); 541 __rte_internal 542 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 543 struct mlx5_devx_rqt_attr *rqt_attr); 544 __rte_internal 545 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 546 struct mlx5_devx_create_sq_attr *sq_attr); 547 __rte_internal 548 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 549 struct mlx5_devx_modify_sq_attr *sq_attr); 550 __rte_internal 551 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 552 struct mlx5_devx_tis_attr *tis_attr); 553 __rte_internal 554 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 555 __rte_internal 556 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 557 FILE *file); 558 __rte_internal 559 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 560 __rte_internal 561 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 562 struct mlx5_devx_cq_attr *attr); 563 __rte_internal 564 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 565 struct mlx5_devx_virtq_attr *attr); 566 __rte_internal 567 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 568 struct mlx5_devx_virtq_attr *attr); 569 __rte_internal 570 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 571 struct mlx5_devx_virtq_attr *attr); 572 __rte_internal 573 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 574 struct mlx5_devx_qp_attr *attr); 575 __rte_internal 576 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 577 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 578 __rte_internal 579 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 580 struct mlx5_devx_rqt_attr *rqt_attr); 581 __rte_internal 582 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 583 struct mlx5_devx_modify_tir_attr *tir_attr); 584 __rte_internal 585 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 586 uint32_t ids[], uint32_t num); 587 588 __rte_internal 589 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 590 struct mlx5_devx_graph_node_attr *data); 591 592 __rte_internal 593 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 594 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 595 596 __rte_internal 597 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 598 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 599 600 __rte_internal 601 struct mlx5_devx_obj * 602 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 603 uint16_t class, uint8_t type, uint8_t len); 604 605 /** 606 * Create virtio queue counters object DevX API. 607 * 608 * @param[in] ctx 609 * Device context. 610 611 * @return 612 * The DevX object created, NULL otherwise and rte_errno is set. 613 */ 614 __rte_internal 615 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 616 617 /** 618 * Query virtio queue counters object using DevX API. 619 * 620 * @param[in] couners_obj 621 * Pointer to virtq object structure. 622 * @param [in/out] attr 623 * Pointer to virtio queue counters attributes structure. 624 * 625 * @return 626 * 0 on success, a negative errno value otherwise and rte_errno is set. 627 */ 628 __rte_internal 629 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 630 struct mlx5_devx_virtio_q_couners_attr *attr); 631 __rte_internal 632 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 633 uint32_t pd); 634 __rte_internal 635 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 636 637 __rte_internal 638 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 639 640 __rte_internal 641 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 642 __rte_internal 643 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 644 uint32_t *out_of_buffers); 645 __rte_internal 646 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 647 uint32_t pd, uint32_t log_obj_size); 648 649 /** 650 * Create general object of type FLOW_METER_ASO using DevX API.. 651 * 652 * @param[in] ctx 653 * Device context. 654 * @param [in] pd 655 * PD value to associate the FLOW_METER_ASO object with. 656 * @param [in] log_obj_size 657 * log_obj_size define to allocate number of 2 * meters 658 * in one FLOW_METER_ASO object. 659 * 660 * @return 661 * The DevX object created, NULL otherwise and rte_errno is set. 662 */ 663 __rte_internal 664 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 665 uint32_t pd, uint32_t log_obj_size); 666 __rte_internal 667 struct mlx5_devx_obj * 668 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 669 670 __rte_internal 671 struct mlx5_devx_obj * 672 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 673 struct mlx5_devx_import_kek_attr *attr); 674 675 __rte_internal 676 struct mlx5_devx_obj * 677 mlx5_devx_cmd_create_credential_obj(void *ctx, 678 struct mlx5_devx_credential_attr *attr); 679 680 __rte_internal 681 struct mlx5_devx_obj * 682 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 683 struct mlx5_devx_crypto_login_attr *attr); 684 685 __rte_internal 686 int 687 mlx5_devx_cmd_query_lag(void *ctx, 688 struct mlx5_devx_lag_context *lag_ctx); 689 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 690