1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 11 12 /* This is limitation of libibverbs: in length variable type is u16. */ 13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 15 16 struct mlx5_devx_mkey_attr { 17 uint64_t addr; 18 uint64_t size; 19 uint32_t umem_id; 20 uint32_t pd; 21 uint32_t log_entity_size; 22 uint32_t pg_access:1; 23 uint32_t relaxed_ordering:1; 24 struct mlx5_klm *klm_array; 25 int klm_num; 26 }; 27 28 /* HCA qos attributes. */ 29 struct mlx5_hca_qos_attr { 30 uint32_t sup:1; /* Whether QOS is supported. */ 31 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ 32 uint32_t flow_meter_reg_share:1; 33 /* Whether reg_c share is supported. */ 34 uint8_t log_max_flow_meter; 35 /* Power of the maximum supported meters. */ 36 uint8_t flow_meter_reg_c_ids; 37 /* Bitmap of the reg_Cs available for flow meter to use. */ 38 39 }; 40 41 struct mlx5_hca_vdpa_attr { 42 uint8_t virtio_queue_type; 43 uint32_t valid:1; 44 uint32_t desc_tunnel_offload_type:1; 45 uint32_t eth_frame_offload_type:1; 46 uint32_t virtio_version_1_0:1; 47 uint32_t tso_ipv4:1; 48 uint32_t tso_ipv6:1; 49 uint32_t tx_csum:1; 50 uint32_t rx_csum:1; 51 uint32_t event_mode:3; 52 uint32_t log_doorbell_stride:5; 53 uint32_t log_doorbell_bar_size:5; 54 uint32_t queue_counters_valid:1; 55 uint32_t max_num_virtio_queues; 56 struct { 57 uint32_t a; 58 uint32_t b; 59 } umems[3]; 60 uint64_t doorbell_bar_offset; 61 }; 62 63 /* HCA supports this number of time periods for LRO. */ 64 #define MLX5_LRO_NUM_SUPP_PERIODS 4 65 66 /* HCA attributes. */ 67 struct mlx5_hca_attr { 68 uint32_t eswitch_manager:1; 69 uint32_t flow_counters_dump:1; 70 uint32_t log_max_rqt_size:5; 71 uint8_t flow_counter_bulk_alloc_bitmap; 72 uint32_t eth_net_offloads:1; 73 uint32_t eth_virt:1; 74 uint32_t wqe_vlan_insert:1; 75 uint32_t wqe_inline_mode:2; 76 uint32_t vport_inline_mode:3; 77 uint32_t tunnel_stateless_geneve_rx:1; 78 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 79 uint32_t tunnel_stateless_gtp:1; 80 uint32_t lro_cap:1; 81 uint32_t tunnel_lro_gre:1; 82 uint32_t tunnel_lro_vxlan:1; 83 uint32_t lro_max_msg_sz_mode:2; 84 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 85 uint32_t flex_parser_protocols; 86 uint32_t hairpin:1; 87 uint32_t log_max_hairpin_queues:5; 88 uint32_t log_max_hairpin_wq_data_sz:5; 89 uint32_t log_max_hairpin_num_packets:5; 90 uint32_t vhca_id:16; 91 uint32_t relaxed_ordering_write:1; 92 uint32_t relaxed_ordering_read:1; 93 struct mlx5_hca_qos_attr qos; 94 struct mlx5_hca_vdpa_attr vdpa; 95 }; 96 97 struct mlx5_devx_wq_attr { 98 uint32_t wq_type:4; 99 uint32_t wq_signature:1; 100 uint32_t end_padding_mode:2; 101 uint32_t cd_slave:1; 102 uint32_t hds_skip_first_sge:1; 103 uint32_t log2_hds_buf_size:3; 104 uint32_t page_offset:5; 105 uint32_t lwm:16; 106 uint32_t pd:24; 107 uint32_t uar_page:24; 108 uint64_t dbr_addr; 109 uint32_t hw_counter; 110 uint32_t sw_counter; 111 uint32_t log_wq_stride:4; 112 uint32_t log_wq_pg_sz:5; 113 uint32_t log_wq_sz:5; 114 uint32_t dbr_umem_valid:1; 115 uint32_t wq_umem_valid:1; 116 uint32_t log_hairpin_num_packets:5; 117 uint32_t log_hairpin_data_sz:5; 118 uint32_t single_wqe_log_num_of_strides:4; 119 uint32_t two_byte_shift_en:1; 120 uint32_t single_stride_log_num_of_bytes:3; 121 uint32_t dbr_umem_id; 122 uint32_t wq_umem_id; 123 uint64_t wq_umem_offset; 124 }; 125 126 /* Create RQ attributes structure, used by create RQ operation. */ 127 struct mlx5_devx_create_rq_attr { 128 uint32_t rlky:1; 129 uint32_t delay_drop_en:1; 130 uint32_t scatter_fcs:1; 131 uint32_t vsd:1; 132 uint32_t mem_rq_type:4; 133 uint32_t state:4; 134 uint32_t flush_in_error_en:1; 135 uint32_t hairpin:1; 136 uint32_t user_index:24; 137 uint32_t cqn:24; 138 uint32_t counter_set_id:8; 139 uint32_t rmpn:24; 140 struct mlx5_devx_wq_attr wq_attr; 141 }; 142 143 /* Modify RQ attributes structure, used by modify RQ operation. */ 144 struct mlx5_devx_modify_rq_attr { 145 uint32_t rqn:24; 146 uint32_t rq_state:4; /* Current RQ state. */ 147 uint32_t state:4; /* Required RQ state. */ 148 uint32_t scatter_fcs:1; 149 uint32_t vsd:1; 150 uint32_t counter_set_id:8; 151 uint32_t hairpin_peer_sq:24; 152 uint32_t hairpin_peer_vhca:16; 153 uint64_t modify_bitmask; 154 uint32_t lwm:16; /* Contained WQ lwm. */ 155 }; 156 157 struct mlx5_rx_hash_field_select { 158 uint32_t l3_prot_type:1; 159 uint32_t l4_prot_type:1; 160 uint32_t selected_fields:30; 161 }; 162 163 /* TIR attributes structure, used by TIR operations. */ 164 struct mlx5_devx_tir_attr { 165 uint32_t disp_type:4; 166 uint32_t lro_timeout_period_usecs:16; 167 uint32_t lro_enable_mask:4; 168 uint32_t lro_max_msg_sz:8; 169 uint32_t inline_rqn:24; 170 uint32_t rx_hash_symmetric:1; 171 uint32_t tunneled_offload_en:1; 172 uint32_t indirect_table:24; 173 uint32_t rx_hash_fn:4; 174 uint32_t self_lb_block:2; 175 uint32_t transport_domain:24; 176 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 177 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 178 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 179 }; 180 181 /* RQT attributes structure, used by RQT operations. */ 182 struct mlx5_devx_rqt_attr { 183 uint8_t rq_type; 184 uint32_t rqt_max_size:16; 185 uint32_t rqt_actual_size:16; 186 uint32_t rq_list[]; 187 }; 188 189 /* TIS attributes structure. */ 190 struct mlx5_devx_tis_attr { 191 uint32_t strict_lag_tx_port_affinity:1; 192 uint32_t tls_en:1; 193 uint32_t lag_tx_port_affinity:4; 194 uint32_t prio:4; 195 uint32_t transport_domain:24; 196 }; 197 198 /* SQ attributes structure, used by SQ create operation. */ 199 struct mlx5_devx_create_sq_attr { 200 uint32_t rlky:1; 201 uint32_t cd_master:1; 202 uint32_t fre:1; 203 uint32_t flush_in_error_en:1; 204 uint32_t allow_multi_pkt_send_wqe:1; 205 uint32_t min_wqe_inline_mode:3; 206 uint32_t state:4; 207 uint32_t reg_umr:1; 208 uint32_t allow_swp:1; 209 uint32_t hairpin:1; 210 uint32_t user_index:24; 211 uint32_t cqn:24; 212 uint32_t packet_pacing_rate_limit_index:16; 213 uint32_t tis_lst_sz:16; 214 uint32_t tis_num:24; 215 struct mlx5_devx_wq_attr wq_attr; 216 }; 217 218 /* SQ attributes structure, used by SQ modify operation. */ 219 struct mlx5_devx_modify_sq_attr { 220 uint32_t sq_state:4; 221 uint32_t state:4; 222 uint32_t hairpin_peer_rq:24; 223 uint32_t hairpin_peer_vhca:16; 224 }; 225 226 227 /* CQ attributes structure, used by CQ operations. */ 228 struct mlx5_devx_cq_attr { 229 uint32_t q_umem_valid:1; 230 uint32_t db_umem_valid:1; 231 uint32_t use_first_only:1; 232 uint32_t overrun_ignore:1; 233 uint32_t log_cq_size:5; 234 uint32_t log_page_size:5; 235 uint32_t uar_page_id; 236 uint32_t q_umem_id; 237 uint64_t q_umem_offset; 238 uint32_t db_umem_id; 239 uint64_t db_umem_offset; 240 uint32_t eqn; 241 uint64_t db_addr; 242 }; 243 244 /* Virtq attributes structure, used by VIRTQ operations. */ 245 struct mlx5_devx_virtq_attr { 246 uint16_t hw_available_index; 247 uint16_t hw_used_index; 248 uint16_t q_size; 249 uint32_t pd:24; 250 uint32_t virtio_version_1_0:1; 251 uint32_t tso_ipv4:1; 252 uint32_t tso_ipv6:1; 253 uint32_t tx_csum:1; 254 uint32_t rx_csum:1; 255 uint32_t event_mode:3; 256 uint32_t state:4; 257 uint32_t dirty_bitmap_dump_enable:1; 258 uint32_t dirty_bitmap_mkey; 259 uint32_t dirty_bitmap_size; 260 uint32_t mkey; 261 uint32_t qp_id; 262 uint32_t queue_index; 263 uint32_t tis_id; 264 uint32_t counters_obj_id; 265 uint64_t dirty_bitmap_addr; 266 uint64_t type; 267 uint64_t desc_addr; 268 uint64_t used_addr; 269 uint64_t available_addr; 270 struct { 271 uint32_t id; 272 uint32_t size; 273 uint64_t offset; 274 } umems[3]; 275 }; 276 277 278 struct mlx5_devx_qp_attr { 279 uint32_t pd:24; 280 uint32_t uar_index:24; 281 uint32_t cqn:24; 282 uint32_t log_page_size:5; 283 uint32_t rq_size:17; /* Must be power of 2. */ 284 uint32_t log_rq_stride:3; 285 uint32_t sq_size:17; /* Must be power of 2. */ 286 uint32_t dbr_umem_valid:1; 287 uint32_t dbr_umem_id; 288 uint64_t dbr_address; 289 uint32_t wq_umem_id; 290 uint64_t wq_umem_offset; 291 }; 292 293 struct mlx5_devx_virtio_q_couners_attr { 294 uint64_t received_desc; 295 uint64_t completed_desc; 296 uint32_t error_cqes; 297 uint32_t bad_desc_errors; 298 uint32_t exceed_max_chain; 299 uint32_t invalid_buffer; 300 }; 301 302 /* mlx5_devx_cmds.c */ 303 304 __rte_internal 305 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 306 uint32_t bulk_sz); 307 __rte_internal 308 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 309 __rte_internal 310 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 311 int clear, uint32_t n_counters, 312 uint64_t *pkts, uint64_t *bytes, 313 uint32_t mkey, void *addr, 314 void *cmd_comp, 315 uint64_t async_id); 316 __rte_internal 317 int mlx5_devx_cmd_query_hca_attr(void *ctx, 318 struct mlx5_hca_attr *attr); 319 __rte_internal 320 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 321 struct mlx5_devx_mkey_attr *attr); 322 __rte_internal 323 int mlx5_devx_get_out_command_status(void *out); 324 __rte_internal 325 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 326 uint32_t *tis_td); 327 __rte_internal 328 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 329 struct mlx5_devx_create_rq_attr *rq_attr, 330 int socket); 331 __rte_internal 332 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 333 struct mlx5_devx_modify_rq_attr *rq_attr); 334 __rte_internal 335 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 336 struct mlx5_devx_tir_attr *tir_attr); 337 __rte_internal 338 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 339 struct mlx5_devx_rqt_attr *rqt_attr); 340 __rte_internal 341 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 342 struct mlx5_devx_create_sq_attr *sq_attr); 343 __rte_internal 344 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 345 struct mlx5_devx_modify_sq_attr *sq_attr); 346 __rte_internal 347 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 348 struct mlx5_devx_tis_attr *tis_attr); 349 __rte_internal 350 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 351 __rte_internal 352 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 353 FILE *file); 354 __rte_internal 355 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 356 struct mlx5_devx_cq_attr *attr); 357 __rte_internal 358 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 359 struct mlx5_devx_virtq_attr *attr); 360 __rte_internal 361 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 362 struct mlx5_devx_virtq_attr *attr); 363 __rte_internal 364 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 365 struct mlx5_devx_virtq_attr *attr); 366 __rte_internal 367 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 368 struct mlx5_devx_qp_attr *attr); 369 __rte_internal 370 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 371 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 372 __rte_internal 373 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 374 struct mlx5_devx_rqt_attr *rqt_attr); 375 376 /** 377 * Create virtio queue counters object DevX API. 378 * 379 * @param[in] ctx 380 * Device context. 381 382 * @return 383 * The DevX object created, NULL otherwise and rte_errno is set. 384 */ 385 __rte_internal 386 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 387 388 /** 389 * Query virtio queue counters object using DevX API. 390 * 391 * @param[in] couners_obj 392 * Pointer to virtq object structure. 393 * @param [in/out] attr 394 * Pointer to virtio queue counters attributes structure. 395 * 396 * @return 397 * 0 on success, a negative errno value otherwise and rte_errno is set. 398 */ 399 __rte_internal 400 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 401 struct mlx5_devx_virtio_q_couners_attr *attr); 402 403 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 404