1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 uint32_t umr_en:1; 35 uint32_t crypto_en:2; 36 uint32_t set_remote_rw:1; 37 struct mlx5_klm *klm_array; 38 int klm_num; 39 }; 40 41 /* HCA qos attributes. */ 42 struct mlx5_hca_qos_attr { 43 uint32_t sup:1; /* Whether QOS is supported. */ 44 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 45 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 46 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 47 uint32_t flow_meter:1; 48 /* 49 * Flow meter is supported, updated version. 50 * When flow_meter is 1, it indicates that REG_C sharing is supported. 51 * If flow_meter is 1, flow_meter_old is also 1. 52 * Using older driver versions, flow_meter_old can be 1 53 * while flow_meter is 0. 54 */ 55 uint32_t flow_meter_aso_sup:1; 56 /* Whether FLOW_METER_ASO Object is supported. */ 57 uint8_t log_max_flow_meter; 58 /* Power of the maximum supported meters. */ 59 uint8_t flow_meter_reg_c_ids; 60 /* Bitmap of the reg_Cs available for flow meter to use. */ 61 uint32_t log_meter_aso_granularity:5; 62 /* Power of the minimum allocation granularity Object. */ 63 uint32_t log_meter_aso_max_alloc:5; 64 /* Power of the maximum allocation granularity Object. */ 65 uint32_t log_max_num_meter_aso:5; 66 /* Power of the maximum number of supported objects. */ 67 68 }; 69 70 struct mlx5_hca_vdpa_attr { 71 uint8_t virtio_queue_type; 72 uint32_t valid:1; 73 uint32_t desc_tunnel_offload_type:1; 74 uint32_t eth_frame_offload_type:1; 75 uint32_t virtio_version_1_0:1; 76 uint32_t tso_ipv4:1; 77 uint32_t tso_ipv6:1; 78 uint32_t tx_csum:1; 79 uint32_t rx_csum:1; 80 uint32_t event_mode:3; 81 uint32_t log_doorbell_stride:5; 82 uint32_t log_doorbell_bar_size:5; 83 uint32_t queue_counters_valid:1; 84 uint32_t max_num_virtio_queues; 85 struct { 86 uint32_t a; 87 uint32_t b; 88 } umems[3]; 89 uint64_t doorbell_bar_offset; 90 }; 91 92 /* HCA supports this number of time periods for LRO. */ 93 #define MLX5_LRO_NUM_SUPP_PERIODS 4 94 95 /* HCA attributes. */ 96 struct mlx5_hca_attr { 97 uint32_t eswitch_manager:1; 98 uint32_t flow_counters_dump:1; 99 uint32_t log_max_rqt_size:5; 100 uint32_t parse_graph_flex_node:1; 101 uint8_t flow_counter_bulk_alloc_bitmap; 102 uint32_t eth_net_offloads:1; 103 uint32_t eth_virt:1; 104 uint32_t wqe_vlan_insert:1; 105 uint32_t csum_cap:1; 106 uint32_t wqe_inline_mode:2; 107 uint32_t vport_inline_mode:3; 108 uint32_t tunnel_stateless_geneve_rx:1; 109 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 110 uint32_t tunnel_stateless_gtp:1; 111 uint32_t lro_cap:1; 112 uint32_t tunnel_lro_gre:1; 113 uint32_t tunnel_lro_vxlan:1; 114 uint32_t lro_max_msg_sz_mode:2; 115 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 116 uint16_t lro_min_mss_size; 117 uint32_t flex_parser_protocols; 118 uint32_t max_geneve_tlv_options; 119 uint32_t max_geneve_tlv_option_data_len; 120 uint32_t hairpin:1; 121 uint32_t log_max_hairpin_queues:5; 122 uint32_t log_max_hairpin_wq_data_sz:5; 123 uint32_t log_max_hairpin_num_packets:5; 124 uint32_t vhca_id:16; 125 uint32_t relaxed_ordering_write:1; 126 uint32_t relaxed_ordering_read:1; 127 uint32_t access_register_user:1; 128 uint32_t wqe_index_ignore:1; 129 uint32_t cross_channel:1; 130 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 131 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 132 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 133 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 134 uint32_t scatter_fcs_w_decap_disable:1; 135 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 136 uint32_t roce:1; 137 uint32_t rq_ts_format:2; 138 uint32_t sq_ts_format:2; 139 uint32_t qp_ts_format:2; 140 uint32_t regex:1; 141 uint32_t reg_c_preserve:1; 142 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 143 uint32_t crypto:1; /* Crypto engine is supported. */ 144 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 145 uint32_t dek:1; /* General obj type DEK is supported. */ 146 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 147 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 148 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 149 uint32_t regexp_num_of_engines; 150 uint32_t log_max_ft_sampler_num:8; 151 uint32_t geneve_tlv_opt; 152 uint32_t cqe_compression:1; 153 uint32_t mini_cqe_resp_flow_tag:1; 154 uint32_t mini_cqe_resp_l3_l4_tag:1; 155 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 156 struct mlx5_hca_qos_attr qos; 157 struct mlx5_hca_vdpa_attr vdpa; 158 int log_max_qp_sz; 159 int log_max_cq_sz; 160 int log_max_qp; 161 int log_max_cq; 162 uint32_t log_max_pd; 163 uint32_t log_max_mrw_sz; 164 uint32_t log_max_srq; 165 uint32_t log_max_srq_sz; 166 uint32_t rss_ind_tbl_cap; 167 uint32_t mmo_dma_en:1; 168 uint32_t mmo_compress_en:1; 169 uint32_t mmo_decompress_en:1; 170 uint32_t compress_min_block_size:4; 171 uint32_t log_max_mmo_dma:5; 172 uint32_t log_max_mmo_compress:5; 173 uint32_t log_max_mmo_decompress:5; 174 uint32_t umr_modify_entity_size_disabled:1; 175 uint32_t umr_indirect_mkey_disabled:1; 176 }; 177 178 struct mlx5_devx_wq_attr { 179 uint32_t wq_type:4; 180 uint32_t wq_signature:1; 181 uint32_t end_padding_mode:2; 182 uint32_t cd_slave:1; 183 uint32_t hds_skip_first_sge:1; 184 uint32_t log2_hds_buf_size:3; 185 uint32_t page_offset:5; 186 uint32_t lwm:16; 187 uint32_t pd:24; 188 uint32_t uar_page:24; 189 uint64_t dbr_addr; 190 uint32_t hw_counter; 191 uint32_t sw_counter; 192 uint32_t log_wq_stride:4; 193 uint32_t log_wq_pg_sz:5; 194 uint32_t log_wq_sz:5; 195 uint32_t dbr_umem_valid:1; 196 uint32_t wq_umem_valid:1; 197 uint32_t log_hairpin_num_packets:5; 198 uint32_t log_hairpin_data_sz:5; 199 uint32_t single_wqe_log_num_of_strides:4; 200 uint32_t two_byte_shift_en:1; 201 uint32_t single_stride_log_num_of_bytes:3; 202 uint32_t dbr_umem_id; 203 uint32_t wq_umem_id; 204 uint64_t wq_umem_offset; 205 }; 206 207 /* Create RQ attributes structure, used by create RQ operation. */ 208 struct mlx5_devx_create_rq_attr { 209 uint32_t rlky:1; 210 uint32_t delay_drop_en:1; 211 uint32_t scatter_fcs:1; 212 uint32_t vsd:1; 213 uint32_t mem_rq_type:4; 214 uint32_t state:4; 215 uint32_t flush_in_error_en:1; 216 uint32_t hairpin:1; 217 uint32_t ts_format:2; 218 uint32_t user_index:24; 219 uint32_t cqn:24; 220 uint32_t counter_set_id:8; 221 uint32_t rmpn:24; 222 struct mlx5_devx_wq_attr wq_attr; 223 }; 224 225 /* Modify RQ attributes structure, used by modify RQ operation. */ 226 struct mlx5_devx_modify_rq_attr { 227 uint32_t rqn:24; 228 uint32_t rq_state:4; /* Current RQ state. */ 229 uint32_t state:4; /* Required RQ state. */ 230 uint32_t scatter_fcs:1; 231 uint32_t vsd:1; 232 uint32_t counter_set_id:8; 233 uint32_t hairpin_peer_sq:24; 234 uint32_t hairpin_peer_vhca:16; 235 uint64_t modify_bitmask; 236 uint32_t lwm:16; /* Contained WQ lwm. */ 237 }; 238 239 struct mlx5_rx_hash_field_select { 240 uint32_t l3_prot_type:1; 241 uint32_t l4_prot_type:1; 242 uint32_t selected_fields:30; 243 }; 244 245 /* TIR attributes structure, used by TIR operations. */ 246 struct mlx5_devx_tir_attr { 247 uint32_t disp_type:4; 248 uint32_t lro_timeout_period_usecs:16; 249 uint32_t lro_enable_mask:4; 250 uint32_t lro_max_msg_sz:8; 251 uint32_t inline_rqn:24; 252 uint32_t rx_hash_symmetric:1; 253 uint32_t tunneled_offload_en:1; 254 uint32_t indirect_table:24; 255 uint32_t rx_hash_fn:4; 256 uint32_t self_lb_block:2; 257 uint32_t transport_domain:24; 258 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 259 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 260 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 261 }; 262 263 /* TIR attributes structure, used by TIR modify. */ 264 struct mlx5_devx_modify_tir_attr { 265 uint32_t tirn:24; 266 uint64_t modify_bitmask; 267 struct mlx5_devx_tir_attr tir; 268 }; 269 270 /* RQT attributes structure, used by RQT operations. */ 271 struct mlx5_devx_rqt_attr { 272 uint8_t rq_type; 273 uint32_t rqt_max_size:16; 274 uint32_t rqt_actual_size:16; 275 uint32_t rq_list[]; 276 }; 277 278 /* TIS attributes structure. */ 279 struct mlx5_devx_tis_attr { 280 uint32_t strict_lag_tx_port_affinity:1; 281 uint32_t tls_en:1; 282 uint32_t lag_tx_port_affinity:4; 283 uint32_t prio:4; 284 uint32_t transport_domain:24; 285 }; 286 287 /* SQ attributes structure, used by SQ create operation. */ 288 struct mlx5_devx_create_sq_attr { 289 uint32_t rlky:1; 290 uint32_t cd_master:1; 291 uint32_t fre:1; 292 uint32_t flush_in_error_en:1; 293 uint32_t allow_multi_pkt_send_wqe:1; 294 uint32_t min_wqe_inline_mode:3; 295 uint32_t state:4; 296 uint32_t reg_umr:1; 297 uint32_t allow_swp:1; 298 uint32_t hairpin:1; 299 uint32_t non_wire:1; 300 uint32_t static_sq_wq:1; 301 uint32_t ts_format:2; 302 uint32_t user_index:24; 303 uint32_t cqn:24; 304 uint32_t packet_pacing_rate_limit_index:16; 305 uint32_t tis_lst_sz:16; 306 uint32_t tis_num:24; 307 struct mlx5_devx_wq_attr wq_attr; 308 }; 309 310 /* SQ attributes structure, used by SQ modify operation. */ 311 struct mlx5_devx_modify_sq_attr { 312 uint32_t sq_state:4; 313 uint32_t state:4; 314 uint32_t hairpin_peer_rq:24; 315 uint32_t hairpin_peer_vhca:16; 316 }; 317 318 319 /* CQ attributes structure, used by CQ operations. */ 320 struct mlx5_devx_cq_attr { 321 uint32_t q_umem_valid:1; 322 uint32_t db_umem_valid:1; 323 uint32_t use_first_only:1; 324 uint32_t overrun_ignore:1; 325 uint32_t cqe_comp_en:1; 326 uint32_t mini_cqe_res_format:2; 327 uint32_t mini_cqe_res_format_ext:2; 328 uint32_t log_cq_size:5; 329 uint32_t log_page_size:5; 330 uint32_t uar_page_id; 331 uint32_t q_umem_id; 332 uint64_t q_umem_offset; 333 uint32_t db_umem_id; 334 uint64_t db_umem_offset; 335 uint32_t eqn; 336 uint64_t db_addr; 337 }; 338 339 /* Virtq attributes structure, used by VIRTQ operations. */ 340 struct mlx5_devx_virtq_attr { 341 uint16_t hw_available_index; 342 uint16_t hw_used_index; 343 uint16_t q_size; 344 uint32_t pd:24; 345 uint32_t virtio_version_1_0:1; 346 uint32_t tso_ipv4:1; 347 uint32_t tso_ipv6:1; 348 uint32_t tx_csum:1; 349 uint32_t rx_csum:1; 350 uint32_t event_mode:3; 351 uint32_t state:4; 352 uint32_t hw_latency_mode:2; 353 uint32_t hw_max_latency_us:12; 354 uint32_t hw_max_pending_comp:16; 355 uint32_t dirty_bitmap_dump_enable:1; 356 uint32_t dirty_bitmap_mkey; 357 uint32_t dirty_bitmap_size; 358 uint32_t mkey; 359 uint32_t qp_id; 360 uint32_t queue_index; 361 uint32_t tis_id; 362 uint32_t counters_obj_id; 363 uint64_t dirty_bitmap_addr; 364 uint64_t type; 365 uint64_t desc_addr; 366 uint64_t used_addr; 367 uint64_t available_addr; 368 struct { 369 uint32_t id; 370 uint32_t size; 371 uint64_t offset; 372 } umems[3]; 373 uint8_t error_type; 374 }; 375 376 377 struct mlx5_devx_qp_attr { 378 uint32_t pd:24; 379 uint32_t uar_index:24; 380 uint32_t cqn:24; 381 uint32_t log_page_size:5; 382 uint32_t rq_size:17; /* Must be power of 2. */ 383 uint32_t log_rq_stride:3; 384 uint32_t sq_size:17; /* Must be power of 2. */ 385 uint32_t ts_format:2; 386 uint32_t dbr_umem_valid:1; 387 uint32_t dbr_umem_id; 388 uint64_t dbr_address; 389 uint32_t wq_umem_id; 390 uint64_t wq_umem_offset; 391 }; 392 393 struct mlx5_devx_virtio_q_couners_attr { 394 uint64_t received_desc; 395 uint64_t completed_desc; 396 uint32_t error_cqes; 397 uint32_t bad_desc_errors; 398 uint32_t exceed_max_chain; 399 uint32_t invalid_buffer; 400 }; 401 402 /* 403 * graph flow match sample attributes structure, 404 * used by flex parser operations. 405 */ 406 struct mlx5_devx_match_sample_attr { 407 uint32_t flow_match_sample_en:1; 408 uint32_t flow_match_sample_field_offset:16; 409 uint32_t flow_match_sample_offset_mode:4; 410 uint32_t flow_match_sample_field_offset_mask; 411 uint32_t flow_match_sample_field_offset_shift:4; 412 uint32_t flow_match_sample_field_base_offset:8; 413 uint32_t flow_match_sample_tunnel_mode:3; 414 uint32_t flow_match_sample_field_id; 415 }; 416 417 /* graph node arc attributes structure, used by flex parser operations. */ 418 struct mlx5_devx_graph_arc_attr { 419 uint32_t compare_condition_value:16; 420 uint32_t start_inner_tunnel:1; 421 uint32_t arc_parse_graph_node:8; 422 uint32_t parse_graph_node_handle; 423 }; 424 425 /* Maximal number of samples per graph node. */ 426 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 427 428 /* Maximal number of input/output arcs per graph node. */ 429 #define MLX5_GRAPH_NODE_ARC_NUM 8 430 431 /* parse graph node attributes structure, used by flex parser operations. */ 432 struct mlx5_devx_graph_node_attr { 433 uint32_t modify_field_select; 434 uint32_t header_length_mode:4; 435 uint32_t header_length_base_value:16; 436 uint32_t header_length_field_shift:4; 437 uint32_t header_length_field_offset:16; 438 uint32_t header_length_field_mask; 439 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 440 uint32_t next_header_field_offset:16; 441 uint32_t next_header_field_size:5; 442 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 443 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 444 }; 445 446 /* Encryption key size is up to 1024 bit, 128 bytes. */ 447 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 448 449 struct mlx5_devx_dek_attr { 450 uint32_t key_size:4; 451 uint32_t has_keytag:1; 452 uint32_t key_purpose:4; 453 uint32_t pd:24; 454 uint64_t opaque; 455 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 456 }; 457 458 struct mlx5_devx_import_kek_attr { 459 uint64_t modify_field_select; 460 uint32_t state:8; 461 uint32_t key_size:4; 462 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 463 }; 464 465 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 466 467 struct mlx5_devx_credential_attr { 468 uint64_t modify_field_select; 469 uint32_t state:8; 470 uint32_t credential_role:8; 471 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 472 }; 473 474 struct mlx5_devx_crypto_login_attr { 475 uint64_t modify_field_select; 476 uint32_t credential_pointer:24; 477 uint32_t session_import_kek_ptr:24; 478 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 479 }; 480 481 /* mlx5_devx_cmds.c */ 482 483 __rte_internal 484 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 485 uint32_t bulk_sz); 486 __rte_internal 487 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 488 __rte_internal 489 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 490 int clear, uint32_t n_counters, 491 uint64_t *pkts, uint64_t *bytes, 492 uint32_t mkey, void *addr, 493 void *cmd_comp, 494 uint64_t async_id); 495 __rte_internal 496 int mlx5_devx_cmd_query_hca_attr(void *ctx, 497 struct mlx5_hca_attr *attr); 498 __rte_internal 499 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 500 struct mlx5_devx_mkey_attr *attr); 501 __rte_internal 502 int mlx5_devx_get_out_command_status(void *out); 503 __rte_internal 504 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 505 uint32_t *tis_td); 506 __rte_internal 507 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 508 struct mlx5_devx_create_rq_attr *rq_attr, 509 int socket); 510 __rte_internal 511 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 512 struct mlx5_devx_modify_rq_attr *rq_attr); 513 __rte_internal 514 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 515 struct mlx5_devx_tir_attr *tir_attr); 516 __rte_internal 517 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 518 struct mlx5_devx_rqt_attr *rqt_attr); 519 __rte_internal 520 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 521 struct mlx5_devx_create_sq_attr *sq_attr); 522 __rte_internal 523 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 524 struct mlx5_devx_modify_sq_attr *sq_attr); 525 __rte_internal 526 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 527 struct mlx5_devx_tis_attr *tis_attr); 528 __rte_internal 529 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 530 __rte_internal 531 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 532 FILE *file); 533 __rte_internal 534 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 535 __rte_internal 536 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 537 struct mlx5_devx_cq_attr *attr); 538 __rte_internal 539 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 540 struct mlx5_devx_virtq_attr *attr); 541 __rte_internal 542 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 543 struct mlx5_devx_virtq_attr *attr); 544 __rte_internal 545 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 546 struct mlx5_devx_virtq_attr *attr); 547 __rte_internal 548 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 549 struct mlx5_devx_qp_attr *attr); 550 __rte_internal 551 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 552 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 553 __rte_internal 554 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 555 struct mlx5_devx_rqt_attr *rqt_attr); 556 __rte_internal 557 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 558 struct mlx5_devx_modify_tir_attr *tir_attr); 559 __rte_internal 560 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 561 uint32_t ids[], uint32_t num); 562 563 __rte_internal 564 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 565 struct mlx5_devx_graph_node_attr *data); 566 567 __rte_internal 568 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 569 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 570 571 __rte_internal 572 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 573 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 574 575 __rte_internal 576 struct mlx5_devx_obj * 577 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 578 uint16_t class, uint8_t type, uint8_t len); 579 580 /** 581 * Create virtio queue counters object DevX API. 582 * 583 * @param[in] ctx 584 * Device context. 585 586 * @return 587 * The DevX object created, NULL otherwise and rte_errno is set. 588 */ 589 __rte_internal 590 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 591 592 /** 593 * Query virtio queue counters object using DevX API. 594 * 595 * @param[in] couners_obj 596 * Pointer to virtq object structure. 597 * @param [in/out] attr 598 * Pointer to virtio queue counters attributes structure. 599 * 600 * @return 601 * 0 on success, a negative errno value otherwise and rte_errno is set. 602 */ 603 __rte_internal 604 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 605 struct mlx5_devx_virtio_q_couners_attr *attr); 606 __rte_internal 607 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 608 uint32_t pd); 609 __rte_internal 610 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 611 612 __rte_internal 613 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 614 615 __rte_internal 616 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 617 __rte_internal 618 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 619 uint32_t *out_of_buffers); 620 __rte_internal 621 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 622 uint32_t pd, uint32_t log_obj_size); 623 624 /** 625 * Create general object of type FLOW_METER_ASO using DevX API.. 626 * 627 * @param[in] ctx 628 * Device context. 629 * @param [in] pd 630 * PD value to associate the FLOW_METER_ASO object with. 631 * @param [in] log_obj_size 632 * log_obj_size define to allocate number of 2 * meters 633 * in one FLOW_METER_ASO object. 634 * 635 * @return 636 * The DevX object created, NULL otherwise and rte_errno is set. 637 */ 638 __rte_internal 639 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 640 uint32_t pd, uint32_t log_obj_size); 641 __rte_internal 642 struct mlx5_devx_obj * 643 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 644 645 __rte_internal 646 struct mlx5_devx_obj * 647 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 648 struct mlx5_devx_import_kek_attr *attr); 649 650 __rte_internal 651 struct mlx5_devx_obj * 652 mlx5_devx_cmd_create_credential_obj(void *ctx, 653 struct mlx5_devx_credential_attr *attr); 654 655 __rte_internal 656 struct mlx5_devx_obj * 657 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 658 struct mlx5_devx_crypto_login_attr *attr); 659 660 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 661