1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 11 12 /* This is limitation of libibverbs: in length variable type is u16. */ 13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 15 16 struct mlx5_devx_mkey_attr { 17 uint64_t addr; 18 uint64_t size; 19 uint32_t umem_id; 20 uint32_t pd; 21 uint32_t log_entity_size; 22 uint32_t pg_access:1; 23 uint32_t relaxed_ordering_write:1; 24 uint32_t relaxed_ordering_read:1; 25 struct mlx5_klm *klm_array; 26 int klm_num; 27 }; 28 29 /* HCA qos attributes. */ 30 struct mlx5_hca_qos_attr { 31 uint32_t sup:1; /* Whether QOS is supported. */ 32 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ 33 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 34 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 35 uint32_t flow_meter_reg_share:1; 36 /* Whether reg_c share is supported. */ 37 uint8_t log_max_flow_meter; 38 /* Power of the maximum supported meters. */ 39 uint8_t flow_meter_reg_c_ids; 40 /* Bitmap of the reg_Cs available for flow meter to use. */ 41 42 }; 43 44 struct mlx5_hca_vdpa_attr { 45 uint8_t virtio_queue_type; 46 uint32_t valid:1; 47 uint32_t desc_tunnel_offload_type:1; 48 uint32_t eth_frame_offload_type:1; 49 uint32_t virtio_version_1_0:1; 50 uint32_t tso_ipv4:1; 51 uint32_t tso_ipv6:1; 52 uint32_t tx_csum:1; 53 uint32_t rx_csum:1; 54 uint32_t event_mode:3; 55 uint32_t log_doorbell_stride:5; 56 uint32_t log_doorbell_bar_size:5; 57 uint32_t queue_counters_valid:1; 58 uint32_t max_num_virtio_queues; 59 struct { 60 uint32_t a; 61 uint32_t b; 62 } umems[3]; 63 uint64_t doorbell_bar_offset; 64 }; 65 66 /* HCA supports this number of time periods for LRO. */ 67 #define MLX5_LRO_NUM_SUPP_PERIODS 4 68 69 /* HCA attributes. */ 70 struct mlx5_hca_attr { 71 uint32_t eswitch_manager:1; 72 uint32_t flow_counters_dump:1; 73 uint32_t log_max_rqt_size:5; 74 uint32_t parse_graph_flex_node:1; 75 uint8_t flow_counter_bulk_alloc_bitmap; 76 uint32_t eth_net_offloads:1; 77 uint32_t eth_virt:1; 78 uint32_t wqe_vlan_insert:1; 79 uint32_t wqe_inline_mode:2; 80 uint32_t vport_inline_mode:3; 81 uint32_t tunnel_stateless_geneve_rx:1; 82 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 83 uint32_t tunnel_stateless_gtp:1; 84 uint32_t lro_cap:1; 85 uint32_t tunnel_lro_gre:1; 86 uint32_t tunnel_lro_vxlan:1; 87 uint32_t lro_max_msg_sz_mode:2; 88 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 89 uint16_t lro_min_mss_size; 90 uint32_t flex_parser_protocols; 91 uint32_t hairpin:1; 92 uint32_t log_max_hairpin_queues:5; 93 uint32_t log_max_hairpin_wq_data_sz:5; 94 uint32_t log_max_hairpin_num_packets:5; 95 uint32_t vhca_id:16; 96 uint32_t relaxed_ordering_write:1; 97 uint32_t relaxed_ordering_read:1; 98 uint32_t access_register_user:1; 99 uint32_t wqe_index_ignore:1; 100 uint32_t cross_channel:1; 101 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 102 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 103 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 104 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 105 uint32_t scatter_fcs_w_decap_disable:1; 106 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 107 uint32_t regex:1; 108 uint32_t regexp_num_of_engines; 109 uint32_t log_max_ft_sampler_num:8; 110 struct mlx5_hca_qos_attr qos; 111 struct mlx5_hca_vdpa_attr vdpa; 112 }; 113 114 struct mlx5_devx_wq_attr { 115 uint32_t wq_type:4; 116 uint32_t wq_signature:1; 117 uint32_t end_padding_mode:2; 118 uint32_t cd_slave:1; 119 uint32_t hds_skip_first_sge:1; 120 uint32_t log2_hds_buf_size:3; 121 uint32_t page_offset:5; 122 uint32_t lwm:16; 123 uint32_t pd:24; 124 uint32_t uar_page:24; 125 uint64_t dbr_addr; 126 uint32_t hw_counter; 127 uint32_t sw_counter; 128 uint32_t log_wq_stride:4; 129 uint32_t log_wq_pg_sz:5; 130 uint32_t log_wq_sz:5; 131 uint32_t dbr_umem_valid:1; 132 uint32_t wq_umem_valid:1; 133 uint32_t log_hairpin_num_packets:5; 134 uint32_t log_hairpin_data_sz:5; 135 uint32_t single_wqe_log_num_of_strides:4; 136 uint32_t two_byte_shift_en:1; 137 uint32_t single_stride_log_num_of_bytes:3; 138 uint32_t dbr_umem_id; 139 uint32_t wq_umem_id; 140 uint64_t wq_umem_offset; 141 }; 142 143 /* Create RQ attributes structure, used by create RQ operation. */ 144 struct mlx5_devx_create_rq_attr { 145 uint32_t rlky:1; 146 uint32_t delay_drop_en:1; 147 uint32_t scatter_fcs:1; 148 uint32_t vsd:1; 149 uint32_t mem_rq_type:4; 150 uint32_t state:4; 151 uint32_t flush_in_error_en:1; 152 uint32_t hairpin:1; 153 uint32_t user_index:24; 154 uint32_t cqn:24; 155 uint32_t counter_set_id:8; 156 uint32_t rmpn:24; 157 struct mlx5_devx_wq_attr wq_attr; 158 }; 159 160 /* Modify RQ attributes structure, used by modify RQ operation. */ 161 struct mlx5_devx_modify_rq_attr { 162 uint32_t rqn:24; 163 uint32_t rq_state:4; /* Current RQ state. */ 164 uint32_t state:4; /* Required RQ state. */ 165 uint32_t scatter_fcs:1; 166 uint32_t vsd:1; 167 uint32_t counter_set_id:8; 168 uint32_t hairpin_peer_sq:24; 169 uint32_t hairpin_peer_vhca:16; 170 uint64_t modify_bitmask; 171 uint32_t lwm:16; /* Contained WQ lwm. */ 172 }; 173 174 struct mlx5_rx_hash_field_select { 175 uint32_t l3_prot_type:1; 176 uint32_t l4_prot_type:1; 177 uint32_t selected_fields:30; 178 }; 179 180 /* TIR attributes structure, used by TIR operations. */ 181 struct mlx5_devx_tir_attr { 182 uint32_t disp_type:4; 183 uint32_t lro_timeout_period_usecs:16; 184 uint32_t lro_enable_mask:4; 185 uint32_t lro_max_msg_sz:8; 186 uint32_t inline_rqn:24; 187 uint32_t rx_hash_symmetric:1; 188 uint32_t tunneled_offload_en:1; 189 uint32_t indirect_table:24; 190 uint32_t rx_hash_fn:4; 191 uint32_t self_lb_block:2; 192 uint32_t transport_domain:24; 193 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 194 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 195 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 196 }; 197 198 /* TIR attributes structure, used by TIR modify. */ 199 struct mlx5_devx_modify_tir_attr { 200 uint32_t tirn:24; 201 uint64_t modify_bitmask; 202 struct mlx5_devx_tir_attr tir; 203 }; 204 205 /* RQT attributes structure, used by RQT operations. */ 206 struct mlx5_devx_rqt_attr { 207 uint8_t rq_type; 208 uint32_t rqt_max_size:16; 209 uint32_t rqt_actual_size:16; 210 uint32_t rq_list[]; 211 }; 212 213 /* TIS attributes structure. */ 214 struct mlx5_devx_tis_attr { 215 uint32_t strict_lag_tx_port_affinity:1; 216 uint32_t tls_en:1; 217 uint32_t lag_tx_port_affinity:4; 218 uint32_t prio:4; 219 uint32_t transport_domain:24; 220 }; 221 222 /* SQ attributes structure, used by SQ create operation. */ 223 struct mlx5_devx_create_sq_attr { 224 uint32_t rlky:1; 225 uint32_t cd_master:1; 226 uint32_t fre:1; 227 uint32_t flush_in_error_en:1; 228 uint32_t allow_multi_pkt_send_wqe:1; 229 uint32_t min_wqe_inline_mode:3; 230 uint32_t state:4; 231 uint32_t reg_umr:1; 232 uint32_t allow_swp:1; 233 uint32_t hairpin:1; 234 uint32_t non_wire:1; 235 uint32_t static_sq_wq:1; 236 uint32_t user_index:24; 237 uint32_t cqn:24; 238 uint32_t packet_pacing_rate_limit_index:16; 239 uint32_t tis_lst_sz:16; 240 uint32_t tis_num:24; 241 struct mlx5_devx_wq_attr wq_attr; 242 }; 243 244 /* SQ attributes structure, used by SQ modify operation. */ 245 struct mlx5_devx_modify_sq_attr { 246 uint32_t sq_state:4; 247 uint32_t state:4; 248 uint32_t hairpin_peer_rq:24; 249 uint32_t hairpin_peer_vhca:16; 250 }; 251 252 253 /* CQ attributes structure, used by CQ operations. */ 254 struct mlx5_devx_cq_attr { 255 uint32_t q_umem_valid:1; 256 uint32_t db_umem_valid:1; 257 uint32_t use_first_only:1; 258 uint32_t overrun_ignore:1; 259 uint32_t cqe_comp_en:1; 260 uint32_t mini_cqe_res_format:2; 261 uint32_t mini_cqe_res_format_ext:2; 262 uint32_t cqe_size:3; 263 uint32_t log_cq_size:5; 264 uint32_t log_page_size:5; 265 uint32_t uar_page_id; 266 uint32_t q_umem_id; 267 uint64_t q_umem_offset; 268 uint32_t db_umem_id; 269 uint64_t db_umem_offset; 270 uint32_t eqn; 271 uint64_t db_addr; 272 }; 273 274 /* Virtq attributes structure, used by VIRTQ operations. */ 275 struct mlx5_devx_virtq_attr { 276 uint16_t hw_available_index; 277 uint16_t hw_used_index; 278 uint16_t q_size; 279 uint32_t pd:24; 280 uint32_t virtio_version_1_0:1; 281 uint32_t tso_ipv4:1; 282 uint32_t tso_ipv6:1; 283 uint32_t tx_csum:1; 284 uint32_t rx_csum:1; 285 uint32_t event_mode:3; 286 uint32_t state:4; 287 uint32_t dirty_bitmap_dump_enable:1; 288 uint32_t dirty_bitmap_mkey; 289 uint32_t dirty_bitmap_size; 290 uint32_t mkey; 291 uint32_t qp_id; 292 uint32_t queue_index; 293 uint32_t tis_id; 294 uint32_t counters_obj_id; 295 uint64_t dirty_bitmap_addr; 296 uint64_t type; 297 uint64_t desc_addr; 298 uint64_t used_addr; 299 uint64_t available_addr; 300 struct { 301 uint32_t id; 302 uint32_t size; 303 uint64_t offset; 304 } umems[3]; 305 uint8_t error_type; 306 }; 307 308 309 struct mlx5_devx_qp_attr { 310 uint32_t pd:24; 311 uint32_t uar_index:24; 312 uint32_t cqn:24; 313 uint32_t log_page_size:5; 314 uint32_t rq_size:17; /* Must be power of 2. */ 315 uint32_t log_rq_stride:3; 316 uint32_t sq_size:17; /* Must be power of 2. */ 317 uint32_t dbr_umem_valid:1; 318 uint32_t dbr_umem_id; 319 uint64_t dbr_address; 320 uint32_t wq_umem_id; 321 uint64_t wq_umem_offset; 322 }; 323 324 struct mlx5_devx_virtio_q_couners_attr { 325 uint64_t received_desc; 326 uint64_t completed_desc; 327 uint32_t error_cqes; 328 uint32_t bad_desc_errors; 329 uint32_t exceed_max_chain; 330 uint32_t invalid_buffer; 331 }; 332 333 /* 334 * graph flow match sample attributes structure, 335 * used by flex parser operations. 336 */ 337 struct mlx5_devx_match_sample_attr { 338 uint32_t flow_match_sample_en:1; 339 uint32_t flow_match_sample_field_offset:16; 340 uint32_t flow_match_sample_offset_mode:4; 341 uint32_t flow_match_sample_field_offset_mask; 342 uint32_t flow_match_sample_field_offset_shift:4; 343 uint32_t flow_match_sample_field_base_offset:8; 344 uint32_t flow_match_sample_tunnel_mode:3; 345 uint32_t flow_match_sample_field_id; 346 }; 347 348 /* graph node arc attributes structure, used by flex parser operations. */ 349 struct mlx5_devx_graph_arc_attr { 350 uint32_t compare_condition_value:16; 351 uint32_t start_inner_tunnel:1; 352 uint32_t arc_parse_graph_node:8; 353 uint32_t parse_graph_node_handle; 354 }; 355 356 /* Maximal number of samples per graph node. */ 357 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 358 359 /* Maximal number of input/output arcs per graph node. */ 360 #define MLX5_GRAPH_NODE_ARC_NUM 8 361 362 /* parse graph node attributes structure, used by flex parser operations. */ 363 struct mlx5_devx_graph_node_attr { 364 uint32_t modify_field_select; 365 uint32_t header_length_mode:4; 366 uint32_t header_length_base_value:16; 367 uint32_t header_length_field_shift:4; 368 uint32_t header_length_field_offset:16; 369 uint32_t header_length_field_mask; 370 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 371 uint32_t next_header_field_offset:16; 372 uint32_t next_header_field_size:5; 373 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 374 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 375 }; 376 377 /* mlx5_devx_cmds.c */ 378 379 __rte_internal 380 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 381 uint32_t bulk_sz); 382 __rte_internal 383 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 384 __rte_internal 385 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 386 int clear, uint32_t n_counters, 387 uint64_t *pkts, uint64_t *bytes, 388 uint32_t mkey, void *addr, 389 void *cmd_comp, 390 uint64_t async_id); 391 __rte_internal 392 int mlx5_devx_cmd_query_hca_attr(void *ctx, 393 struct mlx5_hca_attr *attr); 394 __rte_internal 395 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 396 struct mlx5_devx_mkey_attr *attr); 397 __rte_internal 398 int mlx5_devx_get_out_command_status(void *out); 399 __rte_internal 400 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 401 uint32_t *tis_td); 402 __rte_internal 403 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 404 struct mlx5_devx_create_rq_attr *rq_attr, 405 int socket); 406 __rte_internal 407 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 408 struct mlx5_devx_modify_rq_attr *rq_attr); 409 __rte_internal 410 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 411 struct mlx5_devx_tir_attr *tir_attr); 412 __rte_internal 413 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 414 struct mlx5_devx_rqt_attr *rqt_attr); 415 __rte_internal 416 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 417 struct mlx5_devx_create_sq_attr *sq_attr); 418 __rte_internal 419 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 420 struct mlx5_devx_modify_sq_attr *sq_attr); 421 __rte_internal 422 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 423 struct mlx5_devx_tis_attr *tis_attr); 424 __rte_internal 425 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 426 __rte_internal 427 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 428 FILE *file); 429 __rte_internal 430 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 431 struct mlx5_devx_cq_attr *attr); 432 __rte_internal 433 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 434 struct mlx5_devx_virtq_attr *attr); 435 __rte_internal 436 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 437 struct mlx5_devx_virtq_attr *attr); 438 __rte_internal 439 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 440 struct mlx5_devx_virtq_attr *attr); 441 __rte_internal 442 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 443 struct mlx5_devx_qp_attr *attr); 444 __rte_internal 445 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 446 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 447 __rte_internal 448 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 449 struct mlx5_devx_rqt_attr *rqt_attr); 450 __rte_internal 451 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 452 struct mlx5_devx_modify_tir_attr *tir_attr); 453 __rte_internal 454 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 455 uint32_t ids[], uint32_t num); 456 457 __rte_internal 458 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 459 struct mlx5_devx_graph_node_attr *data); 460 461 __rte_internal 462 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 463 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 464 /** 465 * Create virtio queue counters object DevX API. 466 * 467 * @param[in] ctx 468 * Device context. 469 470 * @return 471 * The DevX object created, NULL otherwise and rte_errno is set. 472 */ 473 __rte_internal 474 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 475 476 /** 477 * Query virtio queue counters object using DevX API. 478 * 479 * @param[in] couners_obj 480 * Pointer to virtq object structure. 481 * @param [in/out] attr 482 * Pointer to virtio queue counters attributes structure. 483 * 484 * @return 485 * 0 on success, a negative errno value otherwise and rte_errno is set. 486 */ 487 __rte_internal 488 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 489 struct mlx5_devx_virtio_q_couners_attr *attr); 490 491 __rte_internal 492 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 493 uint32_t pd); 494 495 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 496