1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 uint32_t umr_en:1; 35 struct mlx5_klm *klm_array; 36 int klm_num; 37 }; 38 39 /* HCA qos attributes. */ 40 struct mlx5_hca_qos_attr { 41 uint32_t sup:1; /* Whether QOS is supported. */ 42 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 43 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 44 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 45 uint32_t flow_meter:1; 46 /* 47 * Flow meter is supported, updated version. 48 * When flow_meter is 1, it indicates that REG_C sharing is supported. 49 * If flow_meter is 1, flow_meter_old is also 1. 50 * Using older driver versions, flow_meter_old can be 1 51 * while flow_meter is 0. 52 */ 53 uint32_t flow_meter_aso_sup:1; 54 /* Whether FLOW_METER_ASO Object is supported. */ 55 uint8_t log_max_flow_meter; 56 /* Power of the maximum supported meters. */ 57 uint8_t flow_meter_reg_c_ids; 58 /* Bitmap of the reg_Cs available for flow meter to use. */ 59 uint32_t log_meter_aso_granularity:5; 60 /* Power of the minimum allocation granularity Object. */ 61 uint32_t log_meter_aso_max_alloc:5; 62 /* Power of the maximum allocation granularity Object. */ 63 uint32_t log_max_num_meter_aso:5; 64 /* Power of the maximum number of supported objects. */ 65 66 }; 67 68 struct mlx5_hca_vdpa_attr { 69 uint8_t virtio_queue_type; 70 uint32_t valid:1; 71 uint32_t desc_tunnel_offload_type:1; 72 uint32_t eth_frame_offload_type:1; 73 uint32_t virtio_version_1_0:1; 74 uint32_t tso_ipv4:1; 75 uint32_t tso_ipv6:1; 76 uint32_t tx_csum:1; 77 uint32_t rx_csum:1; 78 uint32_t event_mode:3; 79 uint32_t log_doorbell_stride:5; 80 uint32_t log_doorbell_bar_size:5; 81 uint32_t queue_counters_valid:1; 82 uint32_t max_num_virtio_queues; 83 struct { 84 uint32_t a; 85 uint32_t b; 86 } umems[3]; 87 uint64_t doorbell_bar_offset; 88 }; 89 90 /* HCA supports this number of time periods for LRO. */ 91 #define MLX5_LRO_NUM_SUPP_PERIODS 4 92 93 /* HCA attributes. */ 94 struct mlx5_hca_attr { 95 uint32_t eswitch_manager:1; 96 uint32_t flow_counters_dump:1; 97 uint32_t log_max_rqt_size:5; 98 uint32_t parse_graph_flex_node:1; 99 uint8_t flow_counter_bulk_alloc_bitmap; 100 uint32_t eth_net_offloads:1; 101 uint32_t eth_virt:1; 102 uint32_t wqe_vlan_insert:1; 103 uint32_t wqe_inline_mode:2; 104 uint32_t vport_inline_mode:3; 105 uint32_t tunnel_stateless_geneve_rx:1; 106 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 107 uint32_t tunnel_stateless_gtp:1; 108 uint32_t lro_cap:1; 109 uint32_t tunnel_lro_gre:1; 110 uint32_t tunnel_lro_vxlan:1; 111 uint32_t lro_max_msg_sz_mode:2; 112 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 113 uint16_t lro_min_mss_size; 114 uint32_t flex_parser_protocols; 115 uint32_t max_geneve_tlv_options; 116 uint32_t max_geneve_tlv_option_data_len; 117 uint32_t hairpin:1; 118 uint32_t log_max_hairpin_queues:5; 119 uint32_t log_max_hairpin_wq_data_sz:5; 120 uint32_t log_max_hairpin_num_packets:5; 121 uint32_t vhca_id:16; 122 uint32_t relaxed_ordering_write:1; 123 uint32_t relaxed_ordering_read:1; 124 uint32_t access_register_user:1; 125 uint32_t wqe_index_ignore:1; 126 uint32_t cross_channel:1; 127 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 128 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 129 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 130 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 131 uint32_t scatter_fcs_w_decap_disable:1; 132 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 133 uint32_t roce:1; 134 uint32_t rq_ts_format:2; 135 uint32_t sq_ts_format:2; 136 uint32_t qp_ts_format:2; 137 uint32_t regex:1; 138 uint32_t reg_c_preserve:1; 139 uint32_t regexp_num_of_engines; 140 uint32_t log_max_ft_sampler_num:8; 141 uint32_t geneve_tlv_opt; 142 uint32_t cqe_compression:1; 143 uint32_t mini_cqe_resp_flow_tag:1; 144 uint32_t mini_cqe_resp_l3_l4_tag:1; 145 struct mlx5_hca_qos_attr qos; 146 struct mlx5_hca_vdpa_attr vdpa; 147 int log_max_qp_sz; 148 int log_max_cq_sz; 149 int log_max_qp; 150 int log_max_cq; 151 uint32_t log_max_pd; 152 uint32_t log_max_mrw_sz; 153 uint32_t log_max_srq; 154 uint32_t log_max_srq_sz; 155 uint32_t rss_ind_tbl_cap; 156 uint32_t mmo_dma_en:1; 157 uint32_t mmo_compress_en:1; 158 uint32_t mmo_decompress_en:1; 159 uint32_t compress_min_block_size:4; 160 uint32_t log_max_mmo_dma:5; 161 uint32_t log_max_mmo_compress:5; 162 uint32_t log_max_mmo_decompress:5; 163 uint32_t umr_modify_entity_size_disabled:1; 164 uint32_t umr_indirect_mkey_disabled:1; 165 }; 166 167 struct mlx5_devx_wq_attr { 168 uint32_t wq_type:4; 169 uint32_t wq_signature:1; 170 uint32_t end_padding_mode:2; 171 uint32_t cd_slave:1; 172 uint32_t hds_skip_first_sge:1; 173 uint32_t log2_hds_buf_size:3; 174 uint32_t page_offset:5; 175 uint32_t lwm:16; 176 uint32_t pd:24; 177 uint32_t uar_page:24; 178 uint64_t dbr_addr; 179 uint32_t hw_counter; 180 uint32_t sw_counter; 181 uint32_t log_wq_stride:4; 182 uint32_t log_wq_pg_sz:5; 183 uint32_t log_wq_sz:5; 184 uint32_t dbr_umem_valid:1; 185 uint32_t wq_umem_valid:1; 186 uint32_t log_hairpin_num_packets:5; 187 uint32_t log_hairpin_data_sz:5; 188 uint32_t single_wqe_log_num_of_strides:4; 189 uint32_t two_byte_shift_en:1; 190 uint32_t single_stride_log_num_of_bytes:3; 191 uint32_t dbr_umem_id; 192 uint32_t wq_umem_id; 193 uint64_t wq_umem_offset; 194 }; 195 196 /* Create RQ attributes structure, used by create RQ operation. */ 197 struct mlx5_devx_create_rq_attr { 198 uint32_t rlky:1; 199 uint32_t delay_drop_en:1; 200 uint32_t scatter_fcs:1; 201 uint32_t vsd:1; 202 uint32_t mem_rq_type:4; 203 uint32_t state:4; 204 uint32_t flush_in_error_en:1; 205 uint32_t hairpin:1; 206 uint32_t ts_format:2; 207 uint32_t user_index:24; 208 uint32_t cqn:24; 209 uint32_t counter_set_id:8; 210 uint32_t rmpn:24; 211 struct mlx5_devx_wq_attr wq_attr; 212 }; 213 214 /* Modify RQ attributes structure, used by modify RQ operation. */ 215 struct mlx5_devx_modify_rq_attr { 216 uint32_t rqn:24; 217 uint32_t rq_state:4; /* Current RQ state. */ 218 uint32_t state:4; /* Required RQ state. */ 219 uint32_t scatter_fcs:1; 220 uint32_t vsd:1; 221 uint32_t counter_set_id:8; 222 uint32_t hairpin_peer_sq:24; 223 uint32_t hairpin_peer_vhca:16; 224 uint64_t modify_bitmask; 225 uint32_t lwm:16; /* Contained WQ lwm. */ 226 }; 227 228 struct mlx5_rx_hash_field_select { 229 uint32_t l3_prot_type:1; 230 uint32_t l4_prot_type:1; 231 uint32_t selected_fields:30; 232 }; 233 234 /* TIR attributes structure, used by TIR operations. */ 235 struct mlx5_devx_tir_attr { 236 uint32_t disp_type:4; 237 uint32_t lro_timeout_period_usecs:16; 238 uint32_t lro_enable_mask:4; 239 uint32_t lro_max_msg_sz:8; 240 uint32_t inline_rqn:24; 241 uint32_t rx_hash_symmetric:1; 242 uint32_t tunneled_offload_en:1; 243 uint32_t indirect_table:24; 244 uint32_t rx_hash_fn:4; 245 uint32_t self_lb_block:2; 246 uint32_t transport_domain:24; 247 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 248 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 249 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 250 }; 251 252 /* TIR attributes structure, used by TIR modify. */ 253 struct mlx5_devx_modify_tir_attr { 254 uint32_t tirn:24; 255 uint64_t modify_bitmask; 256 struct mlx5_devx_tir_attr tir; 257 }; 258 259 /* RQT attributes structure, used by RQT operations. */ 260 struct mlx5_devx_rqt_attr { 261 uint8_t rq_type; 262 uint32_t rqt_max_size:16; 263 uint32_t rqt_actual_size:16; 264 uint32_t rq_list[]; 265 }; 266 267 /* TIS attributes structure. */ 268 struct mlx5_devx_tis_attr { 269 uint32_t strict_lag_tx_port_affinity:1; 270 uint32_t tls_en:1; 271 uint32_t lag_tx_port_affinity:4; 272 uint32_t prio:4; 273 uint32_t transport_domain:24; 274 }; 275 276 /* SQ attributes structure, used by SQ create operation. */ 277 struct mlx5_devx_create_sq_attr { 278 uint32_t rlky:1; 279 uint32_t cd_master:1; 280 uint32_t fre:1; 281 uint32_t flush_in_error_en:1; 282 uint32_t allow_multi_pkt_send_wqe:1; 283 uint32_t min_wqe_inline_mode:3; 284 uint32_t state:4; 285 uint32_t reg_umr:1; 286 uint32_t allow_swp:1; 287 uint32_t hairpin:1; 288 uint32_t non_wire:1; 289 uint32_t static_sq_wq:1; 290 uint32_t ts_format:2; 291 uint32_t user_index:24; 292 uint32_t cqn:24; 293 uint32_t packet_pacing_rate_limit_index:16; 294 uint32_t tis_lst_sz:16; 295 uint32_t tis_num:24; 296 struct mlx5_devx_wq_attr wq_attr; 297 }; 298 299 /* SQ attributes structure, used by SQ modify operation. */ 300 struct mlx5_devx_modify_sq_attr { 301 uint32_t sq_state:4; 302 uint32_t state:4; 303 uint32_t hairpin_peer_rq:24; 304 uint32_t hairpin_peer_vhca:16; 305 }; 306 307 308 /* CQ attributes structure, used by CQ operations. */ 309 struct mlx5_devx_cq_attr { 310 uint32_t q_umem_valid:1; 311 uint32_t db_umem_valid:1; 312 uint32_t use_first_only:1; 313 uint32_t overrun_ignore:1; 314 uint32_t cqe_comp_en:1; 315 uint32_t mini_cqe_res_format:2; 316 uint32_t mini_cqe_res_format_ext:2; 317 uint32_t log_cq_size:5; 318 uint32_t log_page_size:5; 319 uint32_t uar_page_id; 320 uint32_t q_umem_id; 321 uint64_t q_umem_offset; 322 uint32_t db_umem_id; 323 uint64_t db_umem_offset; 324 uint32_t eqn; 325 uint64_t db_addr; 326 }; 327 328 /* Virtq attributes structure, used by VIRTQ operations. */ 329 struct mlx5_devx_virtq_attr { 330 uint16_t hw_available_index; 331 uint16_t hw_used_index; 332 uint16_t q_size; 333 uint32_t pd:24; 334 uint32_t virtio_version_1_0:1; 335 uint32_t tso_ipv4:1; 336 uint32_t tso_ipv6:1; 337 uint32_t tx_csum:1; 338 uint32_t rx_csum:1; 339 uint32_t event_mode:3; 340 uint32_t state:4; 341 uint32_t hw_latency_mode:2; 342 uint32_t hw_max_latency_us:12; 343 uint32_t hw_max_pending_comp:16; 344 uint32_t dirty_bitmap_dump_enable:1; 345 uint32_t dirty_bitmap_mkey; 346 uint32_t dirty_bitmap_size; 347 uint32_t mkey; 348 uint32_t qp_id; 349 uint32_t queue_index; 350 uint32_t tis_id; 351 uint32_t counters_obj_id; 352 uint64_t dirty_bitmap_addr; 353 uint64_t type; 354 uint64_t desc_addr; 355 uint64_t used_addr; 356 uint64_t available_addr; 357 struct { 358 uint32_t id; 359 uint32_t size; 360 uint64_t offset; 361 } umems[3]; 362 uint8_t error_type; 363 }; 364 365 366 struct mlx5_devx_qp_attr { 367 uint32_t pd:24; 368 uint32_t uar_index:24; 369 uint32_t cqn:24; 370 uint32_t log_page_size:5; 371 uint32_t rq_size:17; /* Must be power of 2. */ 372 uint32_t log_rq_stride:3; 373 uint32_t sq_size:17; /* Must be power of 2. */ 374 uint32_t ts_format:2; 375 uint32_t dbr_umem_valid:1; 376 uint32_t dbr_umem_id; 377 uint64_t dbr_address; 378 uint32_t wq_umem_id; 379 uint64_t wq_umem_offset; 380 }; 381 382 struct mlx5_devx_virtio_q_couners_attr { 383 uint64_t received_desc; 384 uint64_t completed_desc; 385 uint32_t error_cqes; 386 uint32_t bad_desc_errors; 387 uint32_t exceed_max_chain; 388 uint32_t invalid_buffer; 389 }; 390 391 /* 392 * graph flow match sample attributes structure, 393 * used by flex parser operations. 394 */ 395 struct mlx5_devx_match_sample_attr { 396 uint32_t flow_match_sample_en:1; 397 uint32_t flow_match_sample_field_offset:16; 398 uint32_t flow_match_sample_offset_mode:4; 399 uint32_t flow_match_sample_field_offset_mask; 400 uint32_t flow_match_sample_field_offset_shift:4; 401 uint32_t flow_match_sample_field_base_offset:8; 402 uint32_t flow_match_sample_tunnel_mode:3; 403 uint32_t flow_match_sample_field_id; 404 }; 405 406 /* graph node arc attributes structure, used by flex parser operations. */ 407 struct mlx5_devx_graph_arc_attr { 408 uint32_t compare_condition_value:16; 409 uint32_t start_inner_tunnel:1; 410 uint32_t arc_parse_graph_node:8; 411 uint32_t parse_graph_node_handle; 412 }; 413 414 /* Maximal number of samples per graph node. */ 415 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 416 417 /* Maximal number of input/output arcs per graph node. */ 418 #define MLX5_GRAPH_NODE_ARC_NUM 8 419 420 /* parse graph node attributes structure, used by flex parser operations. */ 421 struct mlx5_devx_graph_node_attr { 422 uint32_t modify_field_select; 423 uint32_t header_length_mode:4; 424 uint32_t header_length_base_value:16; 425 uint32_t header_length_field_shift:4; 426 uint32_t header_length_field_offset:16; 427 uint32_t header_length_field_mask; 428 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 429 uint32_t next_header_field_offset:16; 430 uint32_t next_header_field_size:5; 431 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 432 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 433 }; 434 435 /* mlx5_devx_cmds.c */ 436 437 __rte_internal 438 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 439 uint32_t bulk_sz); 440 __rte_internal 441 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 442 __rte_internal 443 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 444 int clear, uint32_t n_counters, 445 uint64_t *pkts, uint64_t *bytes, 446 uint32_t mkey, void *addr, 447 void *cmd_comp, 448 uint64_t async_id); 449 __rte_internal 450 int mlx5_devx_cmd_query_hca_attr(void *ctx, 451 struct mlx5_hca_attr *attr); 452 __rte_internal 453 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 454 struct mlx5_devx_mkey_attr *attr); 455 __rte_internal 456 int mlx5_devx_get_out_command_status(void *out); 457 __rte_internal 458 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 459 uint32_t *tis_td); 460 __rte_internal 461 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 462 struct mlx5_devx_create_rq_attr *rq_attr, 463 int socket); 464 __rte_internal 465 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 466 struct mlx5_devx_modify_rq_attr *rq_attr); 467 __rte_internal 468 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 469 struct mlx5_devx_tir_attr *tir_attr); 470 __rte_internal 471 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 472 struct mlx5_devx_rqt_attr *rqt_attr); 473 __rte_internal 474 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 475 struct mlx5_devx_create_sq_attr *sq_attr); 476 __rte_internal 477 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 478 struct mlx5_devx_modify_sq_attr *sq_attr); 479 __rte_internal 480 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 481 struct mlx5_devx_tis_attr *tis_attr); 482 __rte_internal 483 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 484 __rte_internal 485 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 486 FILE *file); 487 __rte_internal 488 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 489 __rte_internal 490 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 491 struct mlx5_devx_cq_attr *attr); 492 __rte_internal 493 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 494 struct mlx5_devx_virtq_attr *attr); 495 __rte_internal 496 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 497 struct mlx5_devx_virtq_attr *attr); 498 __rte_internal 499 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 500 struct mlx5_devx_virtq_attr *attr); 501 __rte_internal 502 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 503 struct mlx5_devx_qp_attr *attr); 504 __rte_internal 505 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 506 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 507 __rte_internal 508 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 509 struct mlx5_devx_rqt_attr *rqt_attr); 510 __rte_internal 511 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 512 struct mlx5_devx_modify_tir_attr *tir_attr); 513 __rte_internal 514 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 515 uint32_t ids[], uint32_t num); 516 517 __rte_internal 518 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 519 struct mlx5_devx_graph_node_attr *data); 520 521 __rte_internal 522 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 523 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 524 525 __rte_internal 526 struct mlx5_devx_obj * 527 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 528 uint16_t class, uint8_t type, uint8_t len); 529 530 /** 531 * Create virtio queue counters object DevX API. 532 * 533 * @param[in] ctx 534 * Device context. 535 536 * @return 537 * The DevX object created, NULL otherwise and rte_errno is set. 538 */ 539 __rte_internal 540 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 541 542 /** 543 * Query virtio queue counters object using DevX API. 544 * 545 * @param[in] couners_obj 546 * Pointer to virtq object structure. 547 * @param [in/out] attr 548 * Pointer to virtio queue counters attributes structure. 549 * 550 * @return 551 * 0 on success, a negative errno value otherwise and rte_errno is set. 552 */ 553 __rte_internal 554 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 555 struct mlx5_devx_virtio_q_couners_attr *attr); 556 __rte_internal 557 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 558 uint32_t pd); 559 __rte_internal 560 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 561 562 __rte_internal 563 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 564 565 __rte_internal 566 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 567 __rte_internal 568 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 569 uint32_t *out_of_buffers); 570 /** 571 * Create general object of type FLOW_METER_ASO using DevX API.. 572 * 573 * @param[in] ctx 574 * Device context. 575 * @param [in] pd 576 * PD value to associate the FLOW_METER_ASO object with. 577 * @param [in] log_obj_size 578 * log_obj_size define to allocate number of 2 * meters 579 * in one FLOW_METER_ASO object. 580 * 581 * @return 582 * The DevX object created, NULL otherwise and rte_errno is set. 583 */ 584 __rte_internal 585 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 586 uint32_t pd, uint32_t log_obj_size); 587 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 588