1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 struct mlx5_klm *klm_array; 35 int klm_num; 36 }; 37 38 /* HCA qos attributes. */ 39 struct mlx5_hca_qos_attr { 40 uint32_t sup:1; /* Whether QOS is supported. */ 41 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 42 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 43 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 44 uint32_t flow_meter:1; 45 /* 46 * Flow meter is supported, updated version. 47 * When flow_meter is 1, it indicates that REG_C sharing is supported. 48 * If flow_meter is 1, flow_meter_old is also 1. 49 * Using older driver versions, flow_meter_old can be 1 50 * while flow_meter is 0. 51 */ 52 uint8_t log_max_flow_meter; 53 /* Power of the maximum supported meters. */ 54 uint8_t flow_meter_reg_c_ids; 55 /* Bitmap of the reg_Cs available for flow meter to use. */ 56 57 }; 58 59 struct mlx5_hca_vdpa_attr { 60 uint8_t virtio_queue_type; 61 uint32_t valid:1; 62 uint32_t desc_tunnel_offload_type:1; 63 uint32_t eth_frame_offload_type:1; 64 uint32_t virtio_version_1_0:1; 65 uint32_t tso_ipv4:1; 66 uint32_t tso_ipv6:1; 67 uint32_t tx_csum:1; 68 uint32_t rx_csum:1; 69 uint32_t event_mode:3; 70 uint32_t log_doorbell_stride:5; 71 uint32_t log_doorbell_bar_size:5; 72 uint32_t queue_counters_valid:1; 73 uint32_t max_num_virtio_queues; 74 struct { 75 uint32_t a; 76 uint32_t b; 77 } umems[3]; 78 uint64_t doorbell_bar_offset; 79 }; 80 81 /* HCA supports this number of time periods for LRO. */ 82 #define MLX5_LRO_NUM_SUPP_PERIODS 4 83 84 /* HCA attributes. */ 85 struct mlx5_hca_attr { 86 uint32_t eswitch_manager:1; 87 uint32_t flow_counters_dump:1; 88 uint32_t log_max_rqt_size:5; 89 uint32_t parse_graph_flex_node:1; 90 uint8_t flow_counter_bulk_alloc_bitmap; 91 uint32_t eth_net_offloads:1; 92 uint32_t eth_virt:1; 93 uint32_t wqe_vlan_insert:1; 94 uint32_t wqe_inline_mode:2; 95 uint32_t vport_inline_mode:3; 96 uint32_t tunnel_stateless_geneve_rx:1; 97 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 98 uint32_t tunnel_stateless_gtp:1; 99 uint32_t lro_cap:1; 100 uint32_t tunnel_lro_gre:1; 101 uint32_t tunnel_lro_vxlan:1; 102 uint32_t lro_max_msg_sz_mode:2; 103 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 104 uint16_t lro_min_mss_size; 105 uint32_t flex_parser_protocols; 106 uint32_t max_geneve_tlv_options; 107 uint32_t max_geneve_tlv_option_data_len; 108 uint32_t hairpin:1; 109 uint32_t log_max_hairpin_queues:5; 110 uint32_t log_max_hairpin_wq_data_sz:5; 111 uint32_t log_max_hairpin_num_packets:5; 112 uint32_t vhca_id:16; 113 uint32_t relaxed_ordering_write:1; 114 uint32_t relaxed_ordering_read:1; 115 uint32_t access_register_user:1; 116 uint32_t wqe_index_ignore:1; 117 uint32_t cross_channel:1; 118 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 119 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 120 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 121 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 122 uint32_t scatter_fcs_w_decap_disable:1; 123 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 124 uint32_t regex:1; 125 uint32_t reg_c_preserve:1; 126 uint32_t regexp_num_of_engines; 127 uint32_t log_max_ft_sampler_num:8; 128 uint32_t geneve_tlv_opt; 129 uint32_t cqe_compression:1; 130 uint32_t mini_cqe_resp_flow_tag:1; 131 uint32_t mini_cqe_resp_l3_l4_tag:1; 132 struct mlx5_hca_qos_attr qos; 133 struct mlx5_hca_vdpa_attr vdpa; 134 int log_max_qp_sz; 135 int log_max_cq_sz; 136 int log_max_qp; 137 int log_max_cq; 138 uint32_t log_max_pd; 139 uint32_t log_max_mrw_sz; 140 uint32_t log_max_srq; 141 uint32_t log_max_srq_sz; 142 uint32_t rss_ind_tbl_cap; 143 uint32_t mmo_dma_en:1; 144 uint32_t mmo_compress_en:1; 145 uint32_t mmo_decompress_en:1; 146 uint32_t compress_min_block_size:4; 147 uint32_t log_max_mmo_dma:5; 148 uint32_t log_max_mmo_compress:5; 149 uint32_t log_max_mmo_decompress:5; 150 }; 151 152 struct mlx5_devx_wq_attr { 153 uint32_t wq_type:4; 154 uint32_t wq_signature:1; 155 uint32_t end_padding_mode:2; 156 uint32_t cd_slave:1; 157 uint32_t hds_skip_first_sge:1; 158 uint32_t log2_hds_buf_size:3; 159 uint32_t page_offset:5; 160 uint32_t lwm:16; 161 uint32_t pd:24; 162 uint32_t uar_page:24; 163 uint64_t dbr_addr; 164 uint32_t hw_counter; 165 uint32_t sw_counter; 166 uint32_t log_wq_stride:4; 167 uint32_t log_wq_pg_sz:5; 168 uint32_t log_wq_sz:5; 169 uint32_t dbr_umem_valid:1; 170 uint32_t wq_umem_valid:1; 171 uint32_t log_hairpin_num_packets:5; 172 uint32_t log_hairpin_data_sz:5; 173 uint32_t single_wqe_log_num_of_strides:4; 174 uint32_t two_byte_shift_en:1; 175 uint32_t single_stride_log_num_of_bytes:3; 176 uint32_t dbr_umem_id; 177 uint32_t wq_umem_id; 178 uint64_t wq_umem_offset; 179 }; 180 181 /* Create RQ attributes structure, used by create RQ operation. */ 182 struct mlx5_devx_create_rq_attr { 183 uint32_t rlky:1; 184 uint32_t delay_drop_en:1; 185 uint32_t scatter_fcs:1; 186 uint32_t vsd:1; 187 uint32_t mem_rq_type:4; 188 uint32_t state:4; 189 uint32_t flush_in_error_en:1; 190 uint32_t hairpin:1; 191 uint32_t user_index:24; 192 uint32_t cqn:24; 193 uint32_t counter_set_id:8; 194 uint32_t rmpn:24; 195 struct mlx5_devx_wq_attr wq_attr; 196 }; 197 198 /* Modify RQ attributes structure, used by modify RQ operation. */ 199 struct mlx5_devx_modify_rq_attr { 200 uint32_t rqn:24; 201 uint32_t rq_state:4; /* Current RQ state. */ 202 uint32_t state:4; /* Required RQ state. */ 203 uint32_t scatter_fcs:1; 204 uint32_t vsd:1; 205 uint32_t counter_set_id:8; 206 uint32_t hairpin_peer_sq:24; 207 uint32_t hairpin_peer_vhca:16; 208 uint64_t modify_bitmask; 209 uint32_t lwm:16; /* Contained WQ lwm. */ 210 }; 211 212 struct mlx5_rx_hash_field_select { 213 uint32_t l3_prot_type:1; 214 uint32_t l4_prot_type:1; 215 uint32_t selected_fields:30; 216 }; 217 218 /* TIR attributes structure, used by TIR operations. */ 219 struct mlx5_devx_tir_attr { 220 uint32_t disp_type:4; 221 uint32_t lro_timeout_period_usecs:16; 222 uint32_t lro_enable_mask:4; 223 uint32_t lro_max_msg_sz:8; 224 uint32_t inline_rqn:24; 225 uint32_t rx_hash_symmetric:1; 226 uint32_t tunneled_offload_en:1; 227 uint32_t indirect_table:24; 228 uint32_t rx_hash_fn:4; 229 uint32_t self_lb_block:2; 230 uint32_t transport_domain:24; 231 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 232 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 233 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 234 }; 235 236 /* TIR attributes structure, used by TIR modify. */ 237 struct mlx5_devx_modify_tir_attr { 238 uint32_t tirn:24; 239 uint64_t modify_bitmask; 240 struct mlx5_devx_tir_attr tir; 241 }; 242 243 /* RQT attributes structure, used by RQT operations. */ 244 struct mlx5_devx_rqt_attr { 245 uint8_t rq_type; 246 uint32_t rqt_max_size:16; 247 uint32_t rqt_actual_size:16; 248 uint32_t rq_list[]; 249 }; 250 251 /* TIS attributes structure. */ 252 struct mlx5_devx_tis_attr { 253 uint32_t strict_lag_tx_port_affinity:1; 254 uint32_t tls_en:1; 255 uint32_t lag_tx_port_affinity:4; 256 uint32_t prio:4; 257 uint32_t transport_domain:24; 258 }; 259 260 /* SQ attributes structure, used by SQ create operation. */ 261 struct mlx5_devx_create_sq_attr { 262 uint32_t rlky:1; 263 uint32_t cd_master:1; 264 uint32_t fre:1; 265 uint32_t flush_in_error_en:1; 266 uint32_t allow_multi_pkt_send_wqe:1; 267 uint32_t min_wqe_inline_mode:3; 268 uint32_t state:4; 269 uint32_t reg_umr:1; 270 uint32_t allow_swp:1; 271 uint32_t hairpin:1; 272 uint32_t non_wire:1; 273 uint32_t static_sq_wq:1; 274 uint32_t user_index:24; 275 uint32_t cqn:24; 276 uint32_t packet_pacing_rate_limit_index:16; 277 uint32_t tis_lst_sz:16; 278 uint32_t tis_num:24; 279 struct mlx5_devx_wq_attr wq_attr; 280 }; 281 282 /* SQ attributes structure, used by SQ modify operation. */ 283 struct mlx5_devx_modify_sq_attr { 284 uint32_t sq_state:4; 285 uint32_t state:4; 286 uint32_t hairpin_peer_rq:24; 287 uint32_t hairpin_peer_vhca:16; 288 }; 289 290 291 /* CQ attributes structure, used by CQ operations. */ 292 struct mlx5_devx_cq_attr { 293 uint32_t q_umem_valid:1; 294 uint32_t db_umem_valid:1; 295 uint32_t use_first_only:1; 296 uint32_t overrun_ignore:1; 297 uint32_t cqe_comp_en:1; 298 uint32_t mini_cqe_res_format:2; 299 uint32_t mini_cqe_res_format_ext:2; 300 uint32_t log_cq_size:5; 301 uint32_t log_page_size:5; 302 uint32_t uar_page_id; 303 uint32_t q_umem_id; 304 uint64_t q_umem_offset; 305 uint32_t db_umem_id; 306 uint64_t db_umem_offset; 307 uint32_t eqn; 308 uint64_t db_addr; 309 }; 310 311 /* Virtq attributes structure, used by VIRTQ operations. */ 312 struct mlx5_devx_virtq_attr { 313 uint16_t hw_available_index; 314 uint16_t hw_used_index; 315 uint16_t q_size; 316 uint32_t pd:24; 317 uint32_t virtio_version_1_0:1; 318 uint32_t tso_ipv4:1; 319 uint32_t tso_ipv6:1; 320 uint32_t tx_csum:1; 321 uint32_t rx_csum:1; 322 uint32_t event_mode:3; 323 uint32_t state:4; 324 uint32_t hw_latency_mode:2; 325 uint32_t hw_max_latency_us:12; 326 uint32_t hw_max_pending_comp:16; 327 uint32_t dirty_bitmap_dump_enable:1; 328 uint32_t dirty_bitmap_mkey; 329 uint32_t dirty_bitmap_size; 330 uint32_t mkey; 331 uint32_t qp_id; 332 uint32_t queue_index; 333 uint32_t tis_id; 334 uint32_t counters_obj_id; 335 uint64_t dirty_bitmap_addr; 336 uint64_t type; 337 uint64_t desc_addr; 338 uint64_t used_addr; 339 uint64_t available_addr; 340 struct { 341 uint32_t id; 342 uint32_t size; 343 uint64_t offset; 344 } umems[3]; 345 uint8_t error_type; 346 }; 347 348 349 struct mlx5_devx_qp_attr { 350 uint32_t pd:24; 351 uint32_t uar_index:24; 352 uint32_t cqn:24; 353 uint32_t log_page_size:5; 354 uint32_t rq_size:17; /* Must be power of 2. */ 355 uint32_t log_rq_stride:3; 356 uint32_t sq_size:17; /* Must be power of 2. */ 357 uint32_t dbr_umem_valid:1; 358 uint32_t dbr_umem_id; 359 uint64_t dbr_address; 360 uint32_t wq_umem_id; 361 uint64_t wq_umem_offset; 362 }; 363 364 struct mlx5_devx_virtio_q_couners_attr { 365 uint64_t received_desc; 366 uint64_t completed_desc; 367 uint32_t error_cqes; 368 uint32_t bad_desc_errors; 369 uint32_t exceed_max_chain; 370 uint32_t invalid_buffer; 371 }; 372 373 /* 374 * graph flow match sample attributes structure, 375 * used by flex parser operations. 376 */ 377 struct mlx5_devx_match_sample_attr { 378 uint32_t flow_match_sample_en:1; 379 uint32_t flow_match_sample_field_offset:16; 380 uint32_t flow_match_sample_offset_mode:4; 381 uint32_t flow_match_sample_field_offset_mask; 382 uint32_t flow_match_sample_field_offset_shift:4; 383 uint32_t flow_match_sample_field_base_offset:8; 384 uint32_t flow_match_sample_tunnel_mode:3; 385 uint32_t flow_match_sample_field_id; 386 }; 387 388 /* graph node arc attributes structure, used by flex parser operations. */ 389 struct mlx5_devx_graph_arc_attr { 390 uint32_t compare_condition_value:16; 391 uint32_t start_inner_tunnel:1; 392 uint32_t arc_parse_graph_node:8; 393 uint32_t parse_graph_node_handle; 394 }; 395 396 /* Maximal number of samples per graph node. */ 397 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 398 399 /* Maximal number of input/output arcs per graph node. */ 400 #define MLX5_GRAPH_NODE_ARC_NUM 8 401 402 /* parse graph node attributes structure, used by flex parser operations. */ 403 struct mlx5_devx_graph_node_attr { 404 uint32_t modify_field_select; 405 uint32_t header_length_mode:4; 406 uint32_t header_length_base_value:16; 407 uint32_t header_length_field_shift:4; 408 uint32_t header_length_field_offset:16; 409 uint32_t header_length_field_mask; 410 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 411 uint32_t next_header_field_offset:16; 412 uint32_t next_header_field_size:5; 413 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 414 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 415 }; 416 417 /* mlx5_devx_cmds.c */ 418 419 __rte_internal 420 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 421 uint32_t bulk_sz); 422 __rte_internal 423 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 424 __rte_internal 425 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 426 int clear, uint32_t n_counters, 427 uint64_t *pkts, uint64_t *bytes, 428 uint32_t mkey, void *addr, 429 void *cmd_comp, 430 uint64_t async_id); 431 __rte_internal 432 int mlx5_devx_cmd_query_hca_attr(void *ctx, 433 struct mlx5_hca_attr *attr); 434 __rte_internal 435 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 436 struct mlx5_devx_mkey_attr *attr); 437 __rte_internal 438 int mlx5_devx_get_out_command_status(void *out); 439 __rte_internal 440 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 441 uint32_t *tis_td); 442 __rte_internal 443 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 444 struct mlx5_devx_create_rq_attr *rq_attr, 445 int socket); 446 __rte_internal 447 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 448 struct mlx5_devx_modify_rq_attr *rq_attr); 449 __rte_internal 450 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 451 struct mlx5_devx_tir_attr *tir_attr); 452 __rte_internal 453 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 454 struct mlx5_devx_rqt_attr *rqt_attr); 455 __rte_internal 456 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 457 struct mlx5_devx_create_sq_attr *sq_attr); 458 __rte_internal 459 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 460 struct mlx5_devx_modify_sq_attr *sq_attr); 461 __rte_internal 462 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 463 struct mlx5_devx_tis_attr *tis_attr); 464 __rte_internal 465 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 466 __rte_internal 467 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 468 FILE *file); 469 __rte_internal 470 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 471 struct mlx5_devx_cq_attr *attr); 472 __rte_internal 473 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 474 struct mlx5_devx_virtq_attr *attr); 475 __rte_internal 476 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 477 struct mlx5_devx_virtq_attr *attr); 478 __rte_internal 479 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 480 struct mlx5_devx_virtq_attr *attr); 481 __rte_internal 482 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 483 struct mlx5_devx_qp_attr *attr); 484 __rte_internal 485 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 486 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 487 __rte_internal 488 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 489 struct mlx5_devx_rqt_attr *rqt_attr); 490 __rte_internal 491 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 492 struct mlx5_devx_modify_tir_attr *tir_attr); 493 __rte_internal 494 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 495 uint32_t ids[], uint32_t num); 496 497 __rte_internal 498 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 499 struct mlx5_devx_graph_node_attr *data); 500 501 __rte_internal 502 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 503 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 504 505 __rte_internal 506 struct mlx5_devx_obj * 507 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 508 uint16_t class, uint8_t type, uint8_t len); 509 510 /** 511 * Create virtio queue counters object DevX API. 512 * 513 * @param[in] ctx 514 * Device context. 515 516 * @return 517 * The DevX object created, NULL otherwise and rte_errno is set. 518 */ 519 __rte_internal 520 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 521 522 /** 523 * Query virtio queue counters object using DevX API. 524 * 525 * @param[in] couners_obj 526 * Pointer to virtq object structure. 527 * @param [in/out] attr 528 * Pointer to virtio queue counters attributes structure. 529 * 530 * @return 531 * 0 on success, a negative errno value otherwise and rte_errno is set. 532 */ 533 __rte_internal 534 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 535 struct mlx5_devx_virtio_q_couners_attr *attr); 536 __rte_internal 537 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 538 uint32_t pd); 539 540 __rte_internal 541 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 542 543 __rte_internal 544 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 545 546 __rte_internal 547 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 548 __rte_internal 549 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 550 uint32_t *out_of_buffers); 551 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 552