1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include <rte_compat.h> 9 #include <rte_bitops.h> 10 11 #include "mlx5_glue.h" 12 #include "mlx5_prm.h" 13 14 /* This is limitation of libibverbs: in length variable type is u16. */ 15 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 16 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 17 18 struct mlx5_devx_counter_attr { 19 uint32_t pd_valid:1; 20 uint32_t pd:24; 21 uint32_t bulk_log_max_alloc:1; 22 union { 23 uint8_t flow_counter_bulk_log_size; 24 uint8_t bulk_n_128; 25 }; 26 }; 27 28 struct mlx5_devx_mkey_attr { 29 uint64_t addr; 30 uint64_t size; 31 uint32_t umem_id; 32 uint32_t pd; 33 uint32_t log_entity_size; 34 uint32_t pg_access:1; 35 uint32_t relaxed_ordering_write:1; 36 uint32_t relaxed_ordering_read:1; 37 uint32_t umr_en:1; 38 uint32_t crypto_en:2; 39 uint32_t set_remote_rw:1; 40 struct mlx5_klm *klm_array; 41 int klm_num; 42 }; 43 44 /* HCA qos attributes. */ 45 struct mlx5_hca_qos_attr { 46 uint32_t sup:1; /* Whether QOS is supported. */ 47 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 48 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 49 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 50 uint32_t flow_meter:1; 51 /* 52 * Flow meter is supported, updated version. 53 * When flow_meter is 1, it indicates that REG_C sharing is supported. 54 * If flow_meter is 1, flow_meter_old is also 1. 55 * Using older driver versions, flow_meter_old can be 1 56 * while flow_meter is 0. 57 */ 58 uint32_t flow_meter_aso_sup:1; 59 /* Whether FLOW_METER_ASO Object is supported. */ 60 uint8_t log_max_flow_meter; 61 /* Power of the maximum supported meters. */ 62 uint8_t flow_meter_reg_c_ids; 63 /* Bitmap of the reg_Cs available for flow meter to use. */ 64 uint32_t log_meter_aso_granularity:5; 65 /* Power of the minimum allocation granularity Object. */ 66 uint32_t log_meter_aso_max_alloc:5; 67 /* Power of the maximum allocation granularity Object. */ 68 uint32_t log_max_num_meter_aso:5; 69 /* Power of the maximum number of supported objects. */ 70 71 }; 72 73 struct mlx5_hca_vdpa_attr { 74 uint8_t virtio_queue_type; 75 uint32_t valid:1; 76 uint32_t desc_tunnel_offload_type:1; 77 uint32_t eth_frame_offload_type:1; 78 uint32_t virtio_version_1_0:1; 79 uint32_t tso_ipv4:1; 80 uint32_t tso_ipv6:1; 81 uint32_t tx_csum:1; 82 uint32_t rx_csum:1; 83 uint32_t event_mode:3; 84 uint32_t log_doorbell_stride:5; 85 uint32_t log_doorbell_bar_size:5; 86 uint32_t queue_counters_valid:1; 87 uint32_t vnet_modify_ext:1; 88 uint32_t virtio_net_q_addr_modify:1; 89 uint32_t virtio_q_index_modify:1; 90 uint32_t max_num_virtio_queues; 91 struct { 92 uint32_t a; 93 uint32_t b; 94 } umems[3]; 95 uint64_t doorbell_bar_offset; 96 }; 97 98 struct mlx5_hca_flow_attr { 99 uint32_t tunnel_header_0_1; 100 uint32_t tunnel_header_2_3; 101 }; 102 103 /** 104 * Accumulate port PARSE_GRAPH_NODE capabilities from 105 * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables 106 */ 107 __extension__ 108 struct mlx5_hca_flex_attr { 109 uint32_t node_in; 110 uint32_t node_out; 111 uint16_t header_length_mode; 112 uint16_t sample_offset_mode; 113 uint8_t max_num_arc_in; 114 uint8_t max_num_arc_out; 115 uint8_t max_num_sample; 116 uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ 117 uint8_t anchor_en:1; 118 uint8_t ext_sample_id:1; 119 uint8_t sample_tunnel_inner2:1; 120 uint8_t zero_size_supported:1; 121 uint8_t sample_id_in_out:1; 122 uint16_t max_base_header_length; 123 uint8_t max_sample_base_offset; 124 uint16_t max_next_header_offset; 125 uint8_t header_length_mask_width; 126 }; 127 128 /* ISO C restricts enumerator values to range of 'int' */ 129 __extension__ 130 enum { 131 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1), 132 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2), 133 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3), 134 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4), 135 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5), 136 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6), 137 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7), 138 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8), 139 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9), 140 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10), 141 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11), 142 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12), 143 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31) 144 }; 145 146 enum { 147 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0), 148 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1), 149 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2) 150 }; 151 152 /* 153 * DWORD shift is the base for calculating header_length_field_mask 154 * value in the MLX5_GRAPH_NODE_LEN_FIELD mode. 155 */ 156 #define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02 157 158 static inline uint32_t 159 mlx5_hca_parse_graph_node_base_hdr_len_mask 160 (const struct mlx5_hca_flex_attr *attr) 161 { 162 return (1 << attr->header_length_mask_width) - 1; 163 } 164 165 /* HCA supports this number of time periods for LRO. */ 166 #define MLX5_LRO_NUM_SUPP_PERIODS 4 167 168 /* HCA attributes. */ 169 struct mlx5_hca_attr { 170 uint32_t eswitch_manager:1; 171 uint32_t flow_counters_dump:1; 172 uint32_t mem_rq_rmp:1; 173 uint32_t log_max_rmp:5; 174 uint32_t log_max_rqt_size:5; 175 uint32_t parse_graph_flex_node:1; 176 uint8_t flow_counter_bulk_alloc_bitmap; 177 uint32_t eth_net_offloads:1; 178 uint32_t eth_virt:1; 179 uint32_t wqe_vlan_insert:1; 180 uint32_t csum_cap:1; 181 uint32_t vlan_cap:1; 182 uint32_t wqe_inline_mode:2; 183 uint32_t vport_inline_mode:3; 184 uint32_t tunnel_stateless_geneve_rx:1; 185 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 186 uint32_t tunnel_stateless_gtp:1; 187 uint32_t max_lso_cap; 188 uint32_t scatter_fcs:1; 189 uint32_t lro_cap:1; 190 uint32_t tunnel_lro_gre:1; 191 uint32_t tunnel_lro_vxlan:1; 192 uint32_t tunnel_stateless_gre:1; 193 uint32_t tunnel_stateless_vxlan:1; 194 uint32_t swp:1; 195 uint32_t swp_csum:1; 196 uint32_t swp_lso:1; 197 uint32_t lro_max_msg_sz_mode:2; 198 uint32_t rq_delay_drop:1; 199 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 200 uint16_t lro_min_mss_size; 201 uint32_t flex_parser_protocols; 202 uint32_t max_geneve_tlv_options; 203 uint32_t max_geneve_tlv_option_data_len; 204 uint32_t hairpin:1; 205 uint32_t log_max_hairpin_queues:5; 206 uint32_t log_max_hairpin_wq_data_sz:5; 207 uint32_t log_max_hairpin_num_packets:5; 208 uint32_t hairpin_sq_wqe_bb_size:4; 209 uint32_t hairpin_sq_wq_in_host_mem:1; 210 uint32_t hairpin_data_buffer_locked:1; 211 uint32_t vhca_id:16; 212 uint32_t relaxed_ordering_write:1; 213 uint32_t relaxed_ordering_read:1; 214 uint32_t access_register_user:1; 215 uint32_t wqe_index_ignore:1; 216 uint32_t cross_channel:1; 217 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 218 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 219 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 220 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 221 uint32_t scatter_fcs_w_decap_disable:1; 222 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 223 uint32_t roce:1; 224 uint32_t wait_on_time:1; 225 uint32_t rq_ts_format:2; 226 uint32_t sq_ts_format:2; 227 uint32_t steering_format_version:4; 228 uint32_t qp_ts_format:2; 229 uint32_t regexp_params:1; 230 uint32_t regexp_version:3; 231 uint32_t reg_c_preserve:1; 232 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 233 uint32_t crypto:1; /* Crypto engine is supported. */ 234 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 235 uint32_t dek:1; /* General obj type DEK is supported. */ 236 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 237 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 238 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 239 uint32_t regexp_num_of_engines; 240 uint32_t log_max_ft_sampler_num:8; 241 uint32_t inner_ipv4_ihl:1; 242 uint32_t outer_ipv4_ihl:1; 243 uint32_t geneve_tlv_opt; 244 uint32_t cqe_compression:1; 245 uint32_t mini_cqe_resp_flow_tag:1; 246 uint32_t mini_cqe_resp_l3_l4_tag:1; 247 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 248 struct mlx5_hca_qos_attr qos; 249 struct mlx5_hca_vdpa_attr vdpa; 250 struct mlx5_hca_flow_attr flow; 251 struct mlx5_hca_flex_attr flex; 252 int log_max_qp_sz; 253 int log_max_cq_sz; 254 int log_max_qp; 255 int log_max_cq; 256 uint32_t log_max_pd; 257 uint32_t log_max_mrw_sz; 258 uint32_t log_max_srq; 259 uint32_t log_max_srq_sz; 260 uint32_t rss_ind_tbl_cap; 261 uint32_t mmo_dma_sq_en:1; 262 uint32_t mmo_compress_sq_en:1; 263 uint32_t mmo_decompress_sq_en:1; 264 uint32_t mmo_dma_qp_en:1; 265 uint32_t mmo_compress_qp_en:1; 266 uint32_t decomp_deflate_v1_en:1; 267 uint32_t decomp_deflate_v2_en:1; 268 uint32_t mmo_regex_qp_en:1; 269 uint32_t mmo_regex_sq_en:1; 270 uint32_t compress_min_block_size:4; 271 uint32_t log_max_mmo_dma:5; 272 uint32_t log_max_mmo_compress:5; 273 uint32_t log_max_mmo_decompress:5; 274 uint32_t decomp_lz4_data_only_en:1; 275 uint32_t decomp_lz4_no_checksum_en:1; 276 uint32_t decomp_lz4_checksum_en:1; 277 uint32_t umr_modify_entity_size_disabled:1; 278 uint32_t umr_indirect_mkey_disabled:1; 279 uint32_t log_min_stride_wqe_sz:5; 280 uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */ 281 uint32_t crypto_wrapped_import_method:1; 282 uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */ 283 uint16_t max_wqe_sz_sq; 284 uint32_t set_reg_c:8; 285 uint32_t nic_flow_table:1; 286 uint32_t modify_outer_ip_ecn:1; 287 union { 288 uint32_t max_flow_counter; 289 struct { 290 uint16_t max_flow_counter_15_0; 291 uint16_t max_flow_counter_31_16; 292 }; 293 }; 294 uint32_t flow_counter_bulk_log_max_alloc:5; 295 uint32_t flow_counter_bulk_log_granularity:5; 296 uint32_t alloc_flow_counter_pd:1; 297 uint32_t flow_counter_access_aso:1; 298 uint32_t flow_access_aso_opc_mod:8; 299 uint32_t cross_vhca:1; 300 }; 301 302 /* LAG Context. */ 303 struct mlx5_devx_lag_context { 304 uint32_t fdb_selection_mode:1; 305 uint32_t port_select_mode:3; 306 uint32_t lag_state:3; 307 uint32_t tx_remap_affinity_1:4; 308 uint32_t tx_remap_affinity_2:4; 309 }; 310 311 struct mlx5_devx_wq_attr { 312 uint32_t wq_type:4; 313 uint32_t wq_signature:1; 314 uint32_t end_padding_mode:2; 315 uint32_t cd_slave:1; 316 uint32_t hds_skip_first_sge:1; 317 uint32_t log2_hds_buf_size:3; 318 uint32_t page_offset:5; 319 uint32_t lwm:16; 320 uint32_t pd:24; 321 uint32_t uar_page:24; 322 uint64_t dbr_addr; 323 uint32_t hw_counter; 324 uint32_t sw_counter; 325 uint32_t log_wq_stride:4; 326 uint32_t log_wq_pg_sz:5; 327 uint32_t log_wq_sz:5; 328 uint32_t dbr_umem_valid:1; 329 uint32_t wq_umem_valid:1; 330 uint32_t log_hairpin_num_packets:5; 331 uint32_t log_hairpin_data_sz:5; 332 uint32_t single_wqe_log_num_of_strides:4; 333 uint32_t two_byte_shift_en:1; 334 uint32_t single_stride_log_num_of_bytes:3; 335 uint32_t dbr_umem_id; 336 uint32_t wq_umem_id; 337 uint64_t wq_umem_offset; 338 }; 339 340 /* Create RQ attributes structure, used by create RQ operation. */ 341 struct mlx5_devx_create_rq_attr { 342 uint32_t rlky:1; 343 uint32_t delay_drop_en:1; 344 uint32_t scatter_fcs:1; 345 uint32_t vsd:1; 346 uint32_t mem_rq_type:4; 347 uint32_t state:4; 348 uint32_t flush_in_error_en:1; 349 uint32_t hairpin:1; 350 uint32_t hairpin_data_buffer_type:3; 351 uint32_t ts_format:2; 352 uint32_t user_index:24; 353 uint32_t cqn:24; 354 uint32_t counter_set_id:8; 355 uint32_t rmpn:24; 356 struct mlx5_devx_wq_attr wq_attr; 357 }; 358 359 /* Modify RQ attributes structure, used by modify RQ operation. */ 360 struct mlx5_devx_modify_rq_attr { 361 uint32_t rqn:24; 362 uint32_t rq_state:4; /* Current RQ state. */ 363 uint32_t state:4; /* Required RQ state. */ 364 uint32_t scatter_fcs:1; 365 uint32_t vsd:1; 366 uint32_t counter_set_id:8; 367 uint32_t hairpin_peer_sq:24; 368 uint32_t hairpin_peer_vhca:16; 369 uint64_t modify_bitmask; 370 uint32_t lwm:16; /* Contained WQ lwm. */ 371 }; 372 373 /* Create RMP attributes structure, used by create RMP operation. */ 374 struct mlx5_devx_create_rmp_attr { 375 uint32_t rsvd0:8; 376 uint32_t state:4; 377 uint32_t rsvd1:20; 378 uint32_t basic_cyclic_rcv_wqe:1; 379 uint32_t rsvd4:31; 380 uint32_t rsvd8[10]; 381 struct mlx5_devx_wq_attr wq_attr; 382 }; 383 384 struct mlx5_rx_hash_field_select { 385 uint32_t l3_prot_type:1; 386 uint32_t l4_prot_type:1; 387 uint32_t selected_fields:30; 388 }; 389 390 /* TIR attributes structure, used by TIR operations. */ 391 struct mlx5_devx_tir_attr { 392 uint32_t disp_type:4; 393 uint32_t lro_timeout_period_usecs:16; 394 uint32_t lro_enable_mask:4; 395 uint32_t lro_max_msg_sz:8; 396 uint32_t inline_rqn:24; 397 uint32_t rx_hash_symmetric:1; 398 uint32_t tunneled_offload_en:1; 399 uint32_t indirect_table:24; 400 uint32_t rx_hash_fn:4; 401 uint32_t self_lb_block:2; 402 uint32_t transport_domain:24; 403 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 404 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 405 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 406 }; 407 408 /* TIR attributes structure, used by TIR modify. */ 409 struct mlx5_devx_modify_tir_attr { 410 uint32_t tirn:24; 411 uint64_t modify_bitmask; 412 struct mlx5_devx_tir_attr tir; 413 }; 414 415 /* RQT attributes structure, used by RQT operations. */ 416 struct mlx5_devx_rqt_attr { 417 uint8_t rq_type; 418 uint32_t rqt_max_size:16; 419 uint32_t rqt_actual_size:16; 420 uint32_t rq_list[]; 421 }; 422 423 /* TIS attributes structure. */ 424 struct mlx5_devx_tis_attr { 425 uint32_t strict_lag_tx_port_affinity:1; 426 uint32_t tls_en:1; 427 uint32_t lag_tx_port_affinity:4; 428 uint32_t prio:4; 429 uint32_t transport_domain:24; 430 }; 431 432 /* SQ attributes structure, used by SQ create operation. */ 433 struct mlx5_devx_create_sq_attr { 434 uint32_t rlky:1; 435 uint32_t cd_master:1; 436 uint32_t fre:1; 437 uint32_t flush_in_error_en:1; 438 uint32_t allow_multi_pkt_send_wqe:1; 439 uint32_t min_wqe_inline_mode:3; 440 uint32_t state:4; 441 uint32_t reg_umr:1; 442 uint32_t allow_swp:1; 443 uint32_t hairpin:1; 444 uint32_t non_wire:1; 445 uint32_t static_sq_wq:1; 446 uint32_t ts_format:2; 447 uint32_t hairpin_wq_buffer_type:3; 448 uint32_t user_index:24; 449 uint32_t cqn:24; 450 uint32_t packet_pacing_rate_limit_index:16; 451 uint32_t tis_lst_sz:16; 452 uint32_t tis_num:24; 453 struct mlx5_devx_wq_attr wq_attr; 454 }; 455 456 /* SQ attributes structure, used by SQ modify operation. */ 457 struct mlx5_devx_modify_sq_attr { 458 uint32_t sq_state:4; 459 uint32_t state:4; 460 uint32_t hairpin_peer_rq:24; 461 uint32_t hairpin_peer_vhca:16; 462 }; 463 464 465 /* CQ attributes structure, used by CQ operations. */ 466 struct mlx5_devx_cq_attr { 467 uint32_t q_umem_valid:1; 468 uint32_t db_umem_valid:1; 469 uint32_t use_first_only:1; 470 uint32_t overrun_ignore:1; 471 uint32_t cqe_comp_en:1; 472 uint32_t mini_cqe_res_format:2; 473 uint32_t mini_cqe_res_format_ext:2; 474 uint32_t log_cq_size:5; 475 uint32_t log_page_size:5; 476 uint32_t uar_page_id; 477 uint32_t q_umem_id; 478 uint64_t q_umem_offset; 479 uint32_t db_umem_id; 480 uint64_t db_umem_offset; 481 uint32_t eqn; 482 uint64_t db_addr; 483 }; 484 485 /* Virtq attributes structure, used by VIRTQ operations. */ 486 struct mlx5_devx_virtq_attr { 487 uint16_t hw_available_index; 488 uint16_t hw_used_index; 489 uint16_t q_size; 490 uint32_t pd:24; 491 uint32_t virtio_version_1_0:1; 492 uint32_t tso_ipv4:1; 493 uint32_t tso_ipv6:1; 494 uint32_t tx_csum:1; 495 uint32_t rx_csum:1; 496 uint32_t event_mode:3; 497 uint32_t state:4; 498 uint32_t hw_latency_mode:2; 499 uint32_t hw_max_latency_us:12; 500 uint32_t hw_max_pending_comp:16; 501 uint32_t dirty_bitmap_dump_enable:1; 502 uint32_t dirty_bitmap_mkey; 503 uint32_t dirty_bitmap_size; 504 uint32_t mkey; 505 uint32_t qp_id; 506 uint32_t queue_index; 507 uint32_t tis_id; 508 uint32_t counters_obj_id; 509 uint64_t dirty_bitmap_addr; 510 uint64_t mod_fields_bitmap; 511 uint64_t desc_addr; 512 uint64_t used_addr; 513 uint64_t available_addr; 514 struct { 515 uint32_t id; 516 uint32_t size; 517 uint64_t offset; 518 } umems[3]; 519 uint8_t error_type; 520 uint8_t q_type; 521 }; 522 523 524 struct mlx5_devx_qp_attr { 525 uint32_t pd:24; 526 uint32_t uar_index:24; 527 uint32_t cqn:24; 528 uint32_t log_page_size:5; 529 uint32_t num_of_receive_wqes:17; /* Must be power of 2. */ 530 uint32_t log_rq_stride:3; 531 uint32_t num_of_send_wqbbs:17; /* Must be power of 2. */ 532 uint32_t ts_format:2; 533 uint32_t dbr_umem_valid:1; 534 uint32_t dbr_umem_id; 535 uint64_t dbr_address; 536 uint32_t wq_umem_id; 537 uint64_t wq_umem_offset; 538 uint32_t user_index:24; 539 uint32_t mmo:1; 540 }; 541 542 struct mlx5_devx_virtio_q_couners_attr { 543 uint64_t received_desc; 544 uint64_t completed_desc; 545 uint32_t error_cqes; 546 uint32_t bad_desc_errors; 547 uint32_t exceed_max_chain; 548 uint32_t invalid_buffer; 549 }; 550 551 /* 552 * graph flow match sample attributes structure, 553 * used by flex parser operations. 554 */ 555 struct mlx5_devx_match_sample_attr { 556 uint32_t flow_match_sample_en:1; 557 uint32_t flow_match_sample_field_offset:16; 558 uint32_t flow_match_sample_offset_mode:4; 559 uint32_t flow_match_sample_field_offset_mask; 560 uint32_t flow_match_sample_field_offset_shift:4; 561 uint32_t flow_match_sample_field_base_offset:8; 562 uint32_t flow_match_sample_tunnel_mode:3; 563 uint32_t flow_match_sample_field_id; 564 }; 565 566 /* graph node arc attributes structure, used by flex parser operations. */ 567 struct mlx5_devx_graph_arc_attr { 568 uint32_t compare_condition_value:16; 569 uint32_t start_inner_tunnel:1; 570 uint32_t arc_parse_graph_node:8; 571 uint32_t parse_graph_node_handle; 572 }; 573 574 /* Maximal number of samples per graph node. */ 575 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 576 577 /* Maximal number of input/output arcs per graph node. */ 578 #define MLX5_GRAPH_NODE_ARC_NUM 8 579 580 /* parse graph node attributes structure, used by flex parser operations. */ 581 struct mlx5_devx_graph_node_attr { 582 uint32_t modify_field_select; 583 uint32_t header_length_mode:4; 584 uint32_t header_length_base_value:16; 585 uint32_t header_length_field_shift:4; 586 uint32_t header_length_field_offset:16; 587 uint32_t header_length_field_mask; 588 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 589 uint32_t next_header_field_offset:16; 590 uint32_t next_header_field_size:5; 591 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 592 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 593 }; 594 595 /* Encryption key size is up to 1024 bit, 128 bytes. */ 596 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 597 598 struct mlx5_devx_dek_attr { 599 uint32_t key_size:4; 600 uint32_t has_keytag:1; 601 uint32_t key_purpose:4; 602 uint32_t pd:24; 603 uint64_t opaque; 604 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 605 }; 606 607 struct mlx5_devx_import_kek_attr { 608 uint64_t modify_field_select; 609 uint32_t state:8; 610 uint32_t key_size:4; 611 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 612 }; 613 614 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 615 616 struct mlx5_devx_credential_attr { 617 uint64_t modify_field_select; 618 uint32_t state:8; 619 uint32_t credential_role:8; 620 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 621 }; 622 623 struct mlx5_devx_crypto_login_attr { 624 uint64_t modify_field_select; 625 uint32_t credential_pointer:24; 626 uint32_t session_import_kek_ptr:24; 627 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 628 }; 629 630 /* mlx5_devx_cmds.c */ 631 632 __rte_internal 633 struct mlx5_devx_obj * 634 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 635 struct mlx5_devx_counter_attr *attr); 636 637 __rte_internal 638 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 639 uint32_t bulk_sz); 640 __rte_internal 641 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 642 __rte_internal 643 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 644 int clear, uint32_t n_counters, 645 uint64_t *pkts, uint64_t *bytes, 646 uint32_t mkey, void *addr, 647 void *cmd_comp, 648 uint64_t async_id); 649 __rte_internal 650 int mlx5_devx_cmd_query_hca_attr(void *ctx, 651 struct mlx5_hca_attr *attr); 652 __rte_internal 653 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 654 struct mlx5_devx_mkey_attr *attr); 655 __rte_internal 656 int mlx5_devx_get_out_command_status(void *out); 657 __rte_internal 658 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 659 uint32_t *tis_td); 660 __rte_internal 661 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 662 struct mlx5_devx_create_rq_attr *rq_attr, 663 int socket); 664 __rte_internal 665 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 666 struct mlx5_devx_modify_rq_attr *rq_attr); 667 __rte_internal 668 struct mlx5_devx_obj *mlx5_devx_cmd_create_rmp(void *ctx, 669 struct mlx5_devx_create_rmp_attr *rq_attr, int socket); 670 __rte_internal 671 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 672 struct mlx5_devx_tir_attr *tir_attr); 673 __rte_internal 674 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 675 struct mlx5_devx_rqt_attr *rqt_attr); 676 __rte_internal 677 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 678 struct mlx5_devx_create_sq_attr *sq_attr); 679 __rte_internal 680 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 681 struct mlx5_devx_modify_sq_attr *sq_attr); 682 __rte_internal 683 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 684 struct mlx5_devx_tis_attr *tis_attr); 685 __rte_internal 686 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 687 __rte_internal 688 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 689 FILE *file); 690 __rte_internal 691 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 692 __rte_internal 693 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 694 struct mlx5_devx_cq_attr *attr); 695 __rte_internal 696 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 697 struct mlx5_devx_virtq_attr *attr); 698 __rte_internal 699 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 700 struct mlx5_devx_virtq_attr *attr); 701 __rte_internal 702 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 703 struct mlx5_devx_virtq_attr *attr); 704 __rte_internal 705 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 706 struct mlx5_devx_qp_attr *attr); 707 __rte_internal 708 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 709 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 710 __rte_internal 711 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 712 struct mlx5_devx_rqt_attr *rqt_attr); 713 __rte_internal 714 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 715 struct mlx5_devx_modify_tir_attr *tir_attr); 716 __rte_internal 717 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 718 struct mlx5_ext_sample_id ids[], 719 uint32_t num, uint8_t *anchor); 720 721 __rte_internal 722 struct mlx5_devx_obj * 723 mlx5_devx_cmd_create_flex_parser(void *ctx, 724 struct mlx5_devx_graph_node_attr *data); 725 726 __rte_internal 727 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 728 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 729 730 __rte_internal 731 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 732 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 733 734 __rte_internal 735 struct mlx5_devx_obj * 736 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 737 uint16_t class, uint8_t type, uint8_t len); 738 739 /** 740 * Create virtio queue counters object DevX API. 741 * 742 * @param[in] ctx 743 * Device context. 744 745 * @return 746 * The DevX object created, NULL otherwise and rte_errno is set. 747 */ 748 __rte_internal 749 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 750 751 /** 752 * Query virtio queue counters object using DevX API. 753 * 754 * @param[in] couners_obj 755 * Pointer to virtq object structure. 756 * @param [in/out] attr 757 * Pointer to virtio queue counters attributes structure. 758 * 759 * @return 760 * 0 on success, a negative errno value otherwise and rte_errno is set. 761 */ 762 __rte_internal 763 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 764 struct mlx5_devx_virtio_q_couners_attr *attr); 765 __rte_internal 766 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 767 uint32_t pd); 768 __rte_internal 769 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 770 771 __rte_internal 772 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 773 774 __rte_internal 775 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 776 __rte_internal 777 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 778 uint32_t *out_of_buffers); 779 __rte_internal 780 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 781 uint32_t pd, uint32_t log_obj_size); 782 783 /** 784 * Create general object of type FLOW_METER_ASO using DevX API.. 785 * 786 * @param[in] ctx 787 * Device context. 788 * @param [in] pd 789 * PD value to associate the FLOW_METER_ASO object with. 790 * @param [in] log_obj_size 791 * log_obj_size define to allocate number of 2 * meters 792 * in one FLOW_METER_ASO object. 793 * 794 * @return 795 * The DevX object created, NULL otherwise and rte_errno is set. 796 */ 797 __rte_internal 798 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 799 uint32_t pd, uint32_t log_obj_size); 800 __rte_internal 801 struct mlx5_devx_obj * 802 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 803 804 __rte_internal 805 struct mlx5_devx_obj * 806 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 807 struct mlx5_devx_import_kek_attr *attr); 808 809 __rte_internal 810 struct mlx5_devx_obj * 811 mlx5_devx_cmd_create_credential_obj(void *ctx, 812 struct mlx5_devx_credential_attr *attr); 813 814 __rte_internal 815 struct mlx5_devx_obj * 816 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 817 struct mlx5_devx_crypto_login_attr *attr); 818 819 __rte_internal 820 int 821 mlx5_devx_cmd_query_lag(void *ctx, 822 struct mlx5_devx_lag_context *lag_ctx); 823 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 824