1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 11 12 /* devX creation object */ 13 struct mlx5_devx_obj { 14 void *obj; /* The DV object. */ 15 int id; /* The object ID. */ 16 }; 17 18 /* UMR memory buffer used to define 1 entry in indirect mkey. */ 19 struct mlx5_klm { 20 uint32_t byte_count; 21 uint32_t mkey; 22 uint64_t address; 23 }; 24 25 /* This is limitation of libibverbs: in length variable type is u16. */ 26 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 27 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 28 29 struct mlx5_devx_mkey_attr { 30 uint64_t addr; 31 uint64_t size; 32 uint32_t umem_id; 33 uint32_t pd; 34 uint32_t log_entity_size; 35 uint32_t pg_access:1; 36 uint32_t relaxed_ordering:1; 37 struct mlx5_klm *klm_array; 38 int klm_num; 39 }; 40 41 /* HCA qos attributes. */ 42 struct mlx5_hca_qos_attr { 43 uint32_t sup:1; /* Whether QOS is supported. */ 44 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ 45 uint32_t flow_meter_reg_share:1; 46 /* Whether reg_c share is supported. */ 47 uint8_t log_max_flow_meter; 48 /* Power of the maximum supported meters. */ 49 uint8_t flow_meter_reg_c_ids; 50 /* Bitmap of the reg_Cs available for flow meter to use. */ 51 52 }; 53 54 struct mlx5_hca_vdpa_attr { 55 uint8_t virtio_queue_type; 56 uint32_t valid:1; 57 uint32_t desc_tunnel_offload_type:1; 58 uint32_t eth_frame_offload_type:1; 59 uint32_t virtio_version_1_0:1; 60 uint32_t tso_ipv4:1; 61 uint32_t tso_ipv6:1; 62 uint32_t tx_csum:1; 63 uint32_t rx_csum:1; 64 uint32_t event_mode:3; 65 uint32_t log_doorbell_stride:5; 66 uint32_t log_doorbell_bar_size:5; 67 uint32_t max_num_virtio_queues; 68 struct { 69 uint32_t a; 70 uint32_t b; 71 } umems[3]; 72 uint64_t doorbell_bar_offset; 73 }; 74 75 /* HCA supports this number of time periods for LRO. */ 76 #define MLX5_LRO_NUM_SUPP_PERIODS 4 77 78 /* HCA attributes. */ 79 struct mlx5_hca_attr { 80 uint32_t eswitch_manager:1; 81 uint32_t flow_counters_dump:1; 82 uint32_t log_max_rqt_size:5; 83 uint8_t flow_counter_bulk_alloc_bitmap; 84 uint32_t eth_net_offloads:1; 85 uint32_t eth_virt:1; 86 uint32_t wqe_vlan_insert:1; 87 uint32_t wqe_inline_mode:2; 88 uint32_t vport_inline_mode:3; 89 uint32_t tunnel_stateless_geneve_rx:1; 90 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 91 uint32_t tunnel_stateless_gtp:1; 92 uint32_t lro_cap:1; 93 uint32_t tunnel_lro_gre:1; 94 uint32_t tunnel_lro_vxlan:1; 95 uint32_t lro_max_msg_sz_mode:2; 96 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 97 uint32_t flex_parser_protocols; 98 uint32_t hairpin:1; 99 uint32_t log_max_hairpin_queues:5; 100 uint32_t log_max_hairpin_wq_data_sz:5; 101 uint32_t log_max_hairpin_num_packets:5; 102 uint32_t vhca_id:16; 103 uint32_t relaxed_ordering_write:1; 104 uint32_t relaxed_ordering_read:1; 105 struct mlx5_hca_qos_attr qos; 106 struct mlx5_hca_vdpa_attr vdpa; 107 }; 108 109 struct mlx5_devx_wq_attr { 110 uint32_t wq_type:4; 111 uint32_t wq_signature:1; 112 uint32_t end_padding_mode:2; 113 uint32_t cd_slave:1; 114 uint32_t hds_skip_first_sge:1; 115 uint32_t log2_hds_buf_size:3; 116 uint32_t page_offset:5; 117 uint32_t lwm:16; 118 uint32_t pd:24; 119 uint32_t uar_page:24; 120 uint64_t dbr_addr; 121 uint32_t hw_counter; 122 uint32_t sw_counter; 123 uint32_t log_wq_stride:4; 124 uint32_t log_wq_pg_sz:5; 125 uint32_t log_wq_sz:5; 126 uint32_t dbr_umem_valid:1; 127 uint32_t wq_umem_valid:1; 128 uint32_t log_hairpin_num_packets:5; 129 uint32_t log_hairpin_data_sz:5; 130 uint32_t single_wqe_log_num_of_strides:4; 131 uint32_t two_byte_shift_en:1; 132 uint32_t single_stride_log_num_of_bytes:3; 133 uint32_t dbr_umem_id; 134 uint32_t wq_umem_id; 135 uint64_t wq_umem_offset; 136 }; 137 138 /* Create RQ attributes structure, used by create RQ operation. */ 139 struct mlx5_devx_create_rq_attr { 140 uint32_t rlky:1; 141 uint32_t delay_drop_en:1; 142 uint32_t scatter_fcs:1; 143 uint32_t vsd:1; 144 uint32_t mem_rq_type:4; 145 uint32_t state:4; 146 uint32_t flush_in_error_en:1; 147 uint32_t hairpin:1; 148 uint32_t user_index:24; 149 uint32_t cqn:24; 150 uint32_t counter_set_id:8; 151 uint32_t rmpn:24; 152 struct mlx5_devx_wq_attr wq_attr; 153 }; 154 155 /* Modify RQ attributes structure, used by modify RQ operation. */ 156 struct mlx5_devx_modify_rq_attr { 157 uint32_t rqn:24; 158 uint32_t rq_state:4; /* Current RQ state. */ 159 uint32_t state:4; /* Required RQ state. */ 160 uint32_t scatter_fcs:1; 161 uint32_t vsd:1; 162 uint32_t counter_set_id:8; 163 uint32_t hairpin_peer_sq:24; 164 uint32_t hairpin_peer_vhca:16; 165 uint64_t modify_bitmask; 166 uint32_t lwm:16; /* Contained WQ lwm. */ 167 }; 168 169 struct mlx5_rx_hash_field_select { 170 uint32_t l3_prot_type:1; 171 uint32_t l4_prot_type:1; 172 uint32_t selected_fields:30; 173 }; 174 175 /* TIR attributes structure, used by TIR operations. */ 176 struct mlx5_devx_tir_attr { 177 uint32_t disp_type:4; 178 uint32_t lro_timeout_period_usecs:16; 179 uint32_t lro_enable_mask:4; 180 uint32_t lro_max_msg_sz:8; 181 uint32_t inline_rqn:24; 182 uint32_t rx_hash_symmetric:1; 183 uint32_t tunneled_offload_en:1; 184 uint32_t indirect_table:24; 185 uint32_t rx_hash_fn:4; 186 uint32_t self_lb_block:2; 187 uint32_t transport_domain:24; 188 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 189 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 190 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 191 }; 192 193 /* RQT attributes structure, used by RQT operations. */ 194 struct mlx5_devx_rqt_attr { 195 uint8_t rq_type; 196 uint32_t rqt_max_size:16; 197 uint32_t rqt_actual_size:16; 198 uint32_t rq_list[]; 199 }; 200 201 /* TIS attributes structure. */ 202 struct mlx5_devx_tis_attr { 203 uint32_t strict_lag_tx_port_affinity:1; 204 uint32_t tls_en:1; 205 uint32_t lag_tx_port_affinity:4; 206 uint32_t prio:4; 207 uint32_t transport_domain:24; 208 }; 209 210 /* SQ attributes structure, used by SQ create operation. */ 211 struct mlx5_devx_create_sq_attr { 212 uint32_t rlky:1; 213 uint32_t cd_master:1; 214 uint32_t fre:1; 215 uint32_t flush_in_error_en:1; 216 uint32_t allow_multi_pkt_send_wqe:1; 217 uint32_t min_wqe_inline_mode:3; 218 uint32_t state:4; 219 uint32_t reg_umr:1; 220 uint32_t allow_swp:1; 221 uint32_t hairpin:1; 222 uint32_t user_index:24; 223 uint32_t cqn:24; 224 uint32_t packet_pacing_rate_limit_index:16; 225 uint32_t tis_lst_sz:16; 226 uint32_t tis_num:24; 227 struct mlx5_devx_wq_attr wq_attr; 228 }; 229 230 /* SQ attributes structure, used by SQ modify operation. */ 231 struct mlx5_devx_modify_sq_attr { 232 uint32_t sq_state:4; 233 uint32_t state:4; 234 uint32_t hairpin_peer_rq:24; 235 uint32_t hairpin_peer_vhca:16; 236 }; 237 238 239 /* CQ attributes structure, used by CQ operations. */ 240 struct mlx5_devx_cq_attr { 241 uint32_t q_umem_valid:1; 242 uint32_t db_umem_valid:1; 243 uint32_t use_first_only:1; 244 uint32_t overrun_ignore:1; 245 uint32_t log_cq_size:5; 246 uint32_t log_page_size:5; 247 uint32_t uar_page_id; 248 uint32_t q_umem_id; 249 uint64_t q_umem_offset; 250 uint32_t db_umem_id; 251 uint64_t db_umem_offset; 252 uint32_t eqn; 253 uint64_t db_addr; 254 }; 255 256 /* Virtq attributes structure, used by VIRTQ operations. */ 257 struct mlx5_devx_virtq_attr { 258 uint16_t hw_available_index; 259 uint16_t hw_used_index; 260 uint16_t q_size; 261 uint32_t virtio_version_1_0:1; 262 uint32_t tso_ipv4:1; 263 uint32_t tso_ipv6:1; 264 uint32_t tx_csum:1; 265 uint32_t rx_csum:1; 266 uint32_t event_mode:3; 267 uint32_t state:4; 268 uint32_t dirty_bitmap_dump_enable:1; 269 uint32_t dirty_bitmap_mkey; 270 uint32_t dirty_bitmap_size; 271 uint32_t mkey; 272 uint32_t qp_id; 273 uint32_t queue_index; 274 uint32_t tis_id; 275 uint64_t dirty_bitmap_addr; 276 uint64_t type; 277 uint64_t desc_addr; 278 uint64_t used_addr; 279 uint64_t available_addr; 280 struct { 281 uint32_t id; 282 uint32_t size; 283 uint64_t offset; 284 } umems[3]; 285 }; 286 287 288 struct mlx5_devx_qp_attr { 289 uint32_t pd:24; 290 uint32_t uar_index:24; 291 uint32_t cqn:24; 292 uint32_t log_page_size:5; 293 uint32_t rq_size:17; /* Must be power of 2. */ 294 uint32_t log_rq_stride:3; 295 uint32_t sq_size:17; /* Must be power of 2. */ 296 uint32_t dbr_umem_valid:1; 297 uint32_t dbr_umem_id; 298 uint64_t dbr_address; 299 uint32_t wq_umem_id; 300 uint64_t wq_umem_offset; 301 }; 302 303 /* mlx5_devx_cmds.c */ 304 305 __rte_internal 306 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 307 uint32_t bulk_sz); 308 __rte_internal 309 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 310 __rte_internal 311 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 312 int clear, uint32_t n_counters, 313 uint64_t *pkts, uint64_t *bytes, 314 uint32_t mkey, void *addr, 315 void *cmd_comp, 316 uint64_t async_id); 317 __rte_internal 318 int mlx5_devx_cmd_query_hca_attr(void *ctx, 319 struct mlx5_hca_attr *attr); 320 __rte_internal 321 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 322 struct mlx5_devx_mkey_attr *attr); 323 __rte_internal 324 int mlx5_devx_get_out_command_status(void *out); 325 __rte_internal 326 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 327 uint32_t *tis_td); 328 __rte_internal 329 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 330 struct mlx5_devx_create_rq_attr *rq_attr, 331 int socket); 332 __rte_internal 333 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 334 struct mlx5_devx_modify_rq_attr *rq_attr); 335 __rte_internal 336 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 337 struct mlx5_devx_tir_attr *tir_attr); 338 __rte_internal 339 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 340 struct mlx5_devx_rqt_attr *rqt_attr); 341 __rte_internal 342 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 343 struct mlx5_devx_create_sq_attr *sq_attr); 344 __rte_internal 345 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 346 struct mlx5_devx_modify_sq_attr *sq_attr); 347 __rte_internal 348 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 349 struct mlx5_devx_tis_attr *tis_attr); 350 __rte_internal 351 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 352 __rte_internal 353 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 354 FILE *file); 355 __rte_internal 356 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 357 struct mlx5_devx_cq_attr *attr); 358 __rte_internal 359 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 360 struct mlx5_devx_virtq_attr *attr); 361 __rte_internal 362 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 363 struct mlx5_devx_virtq_attr *attr); 364 __rte_internal 365 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 366 struct mlx5_devx_virtq_attr *attr); 367 __rte_internal 368 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 369 struct mlx5_devx_qp_attr *attr); 370 __rte_internal 371 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 372 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 373 __rte_internal 374 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 375 struct mlx5_devx_rqt_attr *rqt_attr); 376 377 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 378