1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include <rte_compat.h> 9 #include <rte_bitops.h> 10 11 #include "mlx5_glue.h" 12 #include "mlx5_prm.h" 13 14 /* This is limitation of libibverbs: in length variable type is u16. */ 15 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 16 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 17 18 struct mlx5_devx_mkey_attr { 19 uint64_t addr; 20 uint64_t size; 21 uint32_t umem_id; 22 uint32_t pd; 23 uint32_t log_entity_size; 24 uint32_t pg_access:1; 25 uint32_t relaxed_ordering_write:1; 26 uint32_t relaxed_ordering_read:1; 27 uint32_t umr_en:1; 28 uint32_t crypto_en:2; 29 uint32_t set_remote_rw:1; 30 struct mlx5_klm *klm_array; 31 int klm_num; 32 }; 33 34 /* HCA qos attributes. */ 35 struct mlx5_hca_qos_attr { 36 uint32_t sup:1; /* Whether QOS is supported. */ 37 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 38 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 39 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 40 uint32_t flow_meter:1; 41 /* 42 * Flow meter is supported, updated version. 43 * When flow_meter is 1, it indicates that REG_C sharing is supported. 44 * If flow_meter is 1, flow_meter_old is also 1. 45 * Using older driver versions, flow_meter_old can be 1 46 * while flow_meter is 0. 47 */ 48 uint32_t flow_meter_aso_sup:1; 49 /* Whether FLOW_METER_ASO Object is supported. */ 50 uint8_t log_max_flow_meter; 51 /* Power of the maximum supported meters. */ 52 uint8_t flow_meter_reg_c_ids; 53 /* Bitmap of the reg_Cs available for flow meter to use. */ 54 uint32_t log_meter_aso_granularity:5; 55 /* Power of the minimum allocation granularity Object. */ 56 uint32_t log_meter_aso_max_alloc:5; 57 /* Power of the maximum allocation granularity Object. */ 58 uint32_t log_max_num_meter_aso:5; 59 /* Power of the maximum number of supported objects. */ 60 61 }; 62 63 struct mlx5_hca_vdpa_attr { 64 uint8_t virtio_queue_type; 65 uint32_t valid:1; 66 uint32_t desc_tunnel_offload_type:1; 67 uint32_t eth_frame_offload_type:1; 68 uint32_t virtio_version_1_0:1; 69 uint32_t tso_ipv4:1; 70 uint32_t tso_ipv6:1; 71 uint32_t tx_csum:1; 72 uint32_t rx_csum:1; 73 uint32_t event_mode:3; 74 uint32_t log_doorbell_stride:5; 75 uint32_t log_doorbell_bar_size:5; 76 uint32_t queue_counters_valid:1; 77 uint32_t vnet_modify_ext:1; 78 uint32_t virtio_net_q_addr_modify:1; 79 uint32_t virtio_q_index_modify:1; 80 uint32_t max_num_virtio_queues; 81 struct { 82 uint32_t a; 83 uint32_t b; 84 } umems[3]; 85 uint64_t doorbell_bar_offset; 86 }; 87 88 struct mlx5_hca_flow_attr { 89 uint32_t tunnel_header_0_1; 90 uint32_t tunnel_header_2_3; 91 }; 92 93 /** 94 * Accumulate port PARSE_GRAPH_NODE capabilities from 95 * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables 96 */ 97 __extension__ 98 struct mlx5_hca_flex_attr { 99 uint32_t node_in; 100 uint32_t node_out; 101 uint16_t header_length_mode; 102 uint16_t sample_offset_mode; 103 uint8_t max_num_arc_in; 104 uint8_t max_num_arc_out; 105 uint8_t max_num_sample; 106 uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ 107 uint8_t sample_id_in_out:1; 108 uint16_t max_base_header_length; 109 uint8_t max_sample_base_offset; 110 uint16_t max_next_header_offset; 111 uint8_t header_length_mask_width; 112 }; 113 114 /* ISO C restricts enumerator values to range of 'int' */ 115 __extension__ 116 enum { 117 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1), 118 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2), 119 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3), 120 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4), 121 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5), 122 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6), 123 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7), 124 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8), 125 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9), 126 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10), 127 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11), 128 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12), 129 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31) 130 }; 131 132 enum { 133 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0), 134 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1), 135 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2) 136 }; 137 138 /* 139 * DWORD shift is the base for calculating header_length_field_mask 140 * value in the MLX5_GRAPH_NODE_LEN_FIELD mode. 141 */ 142 #define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02 143 144 static inline uint32_t 145 mlx5_hca_parse_graph_node_base_hdr_len_mask 146 (const struct mlx5_hca_flex_attr *attr) 147 { 148 return (1 << attr->header_length_mask_width) - 1; 149 } 150 151 /* HCA supports this number of time periods for LRO. */ 152 #define MLX5_LRO_NUM_SUPP_PERIODS 4 153 154 /* HCA attributes. */ 155 struct mlx5_hca_attr { 156 uint32_t eswitch_manager:1; 157 uint32_t flow_counters_dump:1; 158 uint32_t mem_rq_rmp:1; 159 uint32_t log_max_rmp:5; 160 uint32_t log_max_rqt_size:5; 161 uint32_t parse_graph_flex_node:1; 162 uint8_t flow_counter_bulk_alloc_bitmap; 163 uint32_t eth_net_offloads:1; 164 uint32_t eth_virt:1; 165 uint32_t wqe_vlan_insert:1; 166 uint32_t csum_cap:1; 167 uint32_t vlan_cap:1; 168 uint32_t wqe_inline_mode:2; 169 uint32_t vport_inline_mode:3; 170 uint32_t tunnel_stateless_geneve_rx:1; 171 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 172 uint32_t tunnel_stateless_gtp:1; 173 uint32_t max_lso_cap; 174 uint32_t scatter_fcs:1; 175 uint32_t lro_cap:1; 176 uint32_t tunnel_lro_gre:1; 177 uint32_t tunnel_lro_vxlan:1; 178 uint32_t tunnel_stateless_gre:1; 179 uint32_t tunnel_stateless_vxlan:1; 180 uint32_t swp:1; 181 uint32_t swp_csum:1; 182 uint32_t swp_lso:1; 183 uint32_t lro_max_msg_sz_mode:2; 184 uint32_t rq_delay_drop:1; 185 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 186 uint16_t lro_min_mss_size; 187 uint32_t flex_parser_protocols; 188 uint32_t max_geneve_tlv_options; 189 uint32_t max_geneve_tlv_option_data_len; 190 uint32_t hairpin:1; 191 uint32_t log_max_hairpin_queues:5; 192 uint32_t log_max_hairpin_wq_data_sz:5; 193 uint32_t log_max_hairpin_num_packets:5; 194 uint32_t vhca_id:16; 195 uint32_t relaxed_ordering_write:1; 196 uint32_t relaxed_ordering_read:1; 197 uint32_t access_register_user:1; 198 uint32_t wqe_index_ignore:1; 199 uint32_t cross_channel:1; 200 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 201 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 202 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 203 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 204 uint32_t scatter_fcs_w_decap_disable:1; 205 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 206 uint32_t roce:1; 207 uint32_t wait_on_time:1; 208 uint32_t rq_ts_format:2; 209 uint32_t sq_ts_format:2; 210 uint32_t steering_format_version:4; 211 uint32_t qp_ts_format:2; 212 uint32_t regexp_params:1; 213 uint32_t regexp_version:3; 214 uint32_t reg_c_preserve:1; 215 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 216 uint32_t crypto:1; /* Crypto engine is supported. */ 217 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 218 uint32_t dek:1; /* General obj type DEK is supported. */ 219 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 220 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 221 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 222 uint32_t regexp_num_of_engines; 223 uint32_t log_max_ft_sampler_num:8; 224 uint32_t inner_ipv4_ihl:1; 225 uint32_t outer_ipv4_ihl:1; 226 uint32_t geneve_tlv_opt; 227 uint32_t cqe_compression:1; 228 uint32_t mini_cqe_resp_flow_tag:1; 229 uint32_t mini_cqe_resp_l3_l4_tag:1; 230 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 231 struct mlx5_hca_qos_attr qos; 232 struct mlx5_hca_vdpa_attr vdpa; 233 struct mlx5_hca_flow_attr flow; 234 struct mlx5_hca_flex_attr flex; 235 int log_max_qp_sz; 236 int log_max_cq_sz; 237 int log_max_qp; 238 int log_max_cq; 239 uint32_t log_max_pd; 240 uint32_t log_max_mrw_sz; 241 uint32_t log_max_srq; 242 uint32_t log_max_srq_sz; 243 uint32_t rss_ind_tbl_cap; 244 uint32_t mmo_dma_sq_en:1; 245 uint32_t mmo_compress_sq_en:1; 246 uint32_t mmo_decompress_sq_en:1; 247 uint32_t mmo_dma_qp_en:1; 248 uint32_t mmo_compress_qp_en:1; 249 uint32_t mmo_decompress_qp_en:1; 250 uint32_t mmo_regex_qp_en:1; 251 uint32_t mmo_regex_sq_en:1; 252 uint32_t compress_min_block_size:4; 253 uint32_t log_max_mmo_dma:5; 254 uint32_t log_max_mmo_compress:5; 255 uint32_t log_max_mmo_decompress:5; 256 uint32_t umr_modify_entity_size_disabled:1; 257 uint32_t umr_indirect_mkey_disabled:1; 258 uint32_t log_min_stride_wqe_sz:5; 259 uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */ 260 uint32_t crypto_wrapped_import_method:1; 261 uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */ 262 uint16_t max_wqe_sz_sq; 263 }; 264 265 /* LAG Context. */ 266 struct mlx5_devx_lag_context { 267 uint32_t fdb_selection_mode:1; 268 uint32_t port_select_mode:3; 269 uint32_t lag_state:3; 270 uint32_t tx_remap_affinity_1:4; 271 uint32_t tx_remap_affinity_2:4; 272 }; 273 274 struct mlx5_devx_wq_attr { 275 uint32_t wq_type:4; 276 uint32_t wq_signature:1; 277 uint32_t end_padding_mode:2; 278 uint32_t cd_slave:1; 279 uint32_t hds_skip_first_sge:1; 280 uint32_t log2_hds_buf_size:3; 281 uint32_t page_offset:5; 282 uint32_t lwm:16; 283 uint32_t pd:24; 284 uint32_t uar_page:24; 285 uint64_t dbr_addr; 286 uint32_t hw_counter; 287 uint32_t sw_counter; 288 uint32_t log_wq_stride:4; 289 uint32_t log_wq_pg_sz:5; 290 uint32_t log_wq_sz:5; 291 uint32_t dbr_umem_valid:1; 292 uint32_t wq_umem_valid:1; 293 uint32_t log_hairpin_num_packets:5; 294 uint32_t log_hairpin_data_sz:5; 295 uint32_t single_wqe_log_num_of_strides:4; 296 uint32_t two_byte_shift_en:1; 297 uint32_t single_stride_log_num_of_bytes:3; 298 uint32_t dbr_umem_id; 299 uint32_t wq_umem_id; 300 uint64_t wq_umem_offset; 301 }; 302 303 /* Create RQ attributes structure, used by create RQ operation. */ 304 struct mlx5_devx_create_rq_attr { 305 uint32_t rlky:1; 306 uint32_t delay_drop_en:1; 307 uint32_t scatter_fcs:1; 308 uint32_t vsd:1; 309 uint32_t mem_rq_type:4; 310 uint32_t state:4; 311 uint32_t flush_in_error_en:1; 312 uint32_t hairpin:1; 313 uint32_t ts_format:2; 314 uint32_t user_index:24; 315 uint32_t cqn:24; 316 uint32_t counter_set_id:8; 317 uint32_t rmpn:24; 318 struct mlx5_devx_wq_attr wq_attr; 319 }; 320 321 /* Modify RQ attributes structure, used by modify RQ operation. */ 322 struct mlx5_devx_modify_rq_attr { 323 uint32_t rqn:24; 324 uint32_t rq_state:4; /* Current RQ state. */ 325 uint32_t state:4; /* Required RQ state. */ 326 uint32_t scatter_fcs:1; 327 uint32_t vsd:1; 328 uint32_t counter_set_id:8; 329 uint32_t hairpin_peer_sq:24; 330 uint32_t hairpin_peer_vhca:16; 331 uint64_t modify_bitmask; 332 uint32_t lwm:16; /* Contained WQ lwm. */ 333 }; 334 335 /* Create RMP attributes structure, used by create RMP operation. */ 336 struct mlx5_devx_create_rmp_attr { 337 uint32_t rsvd0:8; 338 uint32_t state:4; 339 uint32_t rsvd1:20; 340 uint32_t basic_cyclic_rcv_wqe:1; 341 uint32_t rsvd4:31; 342 uint32_t rsvd8[10]; 343 struct mlx5_devx_wq_attr wq_attr; 344 }; 345 346 struct mlx5_rx_hash_field_select { 347 uint32_t l3_prot_type:1; 348 uint32_t l4_prot_type:1; 349 uint32_t selected_fields:30; 350 }; 351 352 /* TIR attributes structure, used by TIR operations. */ 353 struct mlx5_devx_tir_attr { 354 uint32_t disp_type:4; 355 uint32_t lro_timeout_period_usecs:16; 356 uint32_t lro_enable_mask:4; 357 uint32_t lro_max_msg_sz:8; 358 uint32_t inline_rqn:24; 359 uint32_t rx_hash_symmetric:1; 360 uint32_t tunneled_offload_en:1; 361 uint32_t indirect_table:24; 362 uint32_t rx_hash_fn:4; 363 uint32_t self_lb_block:2; 364 uint32_t transport_domain:24; 365 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 366 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 367 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 368 }; 369 370 /* TIR attributes structure, used by TIR modify. */ 371 struct mlx5_devx_modify_tir_attr { 372 uint32_t tirn:24; 373 uint64_t modify_bitmask; 374 struct mlx5_devx_tir_attr tir; 375 }; 376 377 /* RQT attributes structure, used by RQT operations. */ 378 struct mlx5_devx_rqt_attr { 379 uint8_t rq_type; 380 uint32_t rqt_max_size:16; 381 uint32_t rqt_actual_size:16; 382 uint32_t rq_list[]; 383 }; 384 385 /* TIS attributes structure. */ 386 struct mlx5_devx_tis_attr { 387 uint32_t strict_lag_tx_port_affinity:1; 388 uint32_t tls_en:1; 389 uint32_t lag_tx_port_affinity:4; 390 uint32_t prio:4; 391 uint32_t transport_domain:24; 392 }; 393 394 /* SQ attributes structure, used by SQ create operation. */ 395 struct mlx5_devx_create_sq_attr { 396 uint32_t rlky:1; 397 uint32_t cd_master:1; 398 uint32_t fre:1; 399 uint32_t flush_in_error_en:1; 400 uint32_t allow_multi_pkt_send_wqe:1; 401 uint32_t min_wqe_inline_mode:3; 402 uint32_t state:4; 403 uint32_t reg_umr:1; 404 uint32_t allow_swp:1; 405 uint32_t hairpin:1; 406 uint32_t non_wire:1; 407 uint32_t static_sq_wq:1; 408 uint32_t ts_format:2; 409 uint32_t user_index:24; 410 uint32_t cqn:24; 411 uint32_t packet_pacing_rate_limit_index:16; 412 uint32_t tis_lst_sz:16; 413 uint32_t tis_num:24; 414 struct mlx5_devx_wq_attr wq_attr; 415 }; 416 417 /* SQ attributes structure, used by SQ modify operation. */ 418 struct mlx5_devx_modify_sq_attr { 419 uint32_t sq_state:4; 420 uint32_t state:4; 421 uint32_t hairpin_peer_rq:24; 422 uint32_t hairpin_peer_vhca:16; 423 }; 424 425 426 /* CQ attributes structure, used by CQ operations. */ 427 struct mlx5_devx_cq_attr { 428 uint32_t q_umem_valid:1; 429 uint32_t db_umem_valid:1; 430 uint32_t use_first_only:1; 431 uint32_t overrun_ignore:1; 432 uint32_t cqe_comp_en:1; 433 uint32_t mini_cqe_res_format:2; 434 uint32_t mini_cqe_res_format_ext:2; 435 uint32_t log_cq_size:5; 436 uint32_t log_page_size:5; 437 uint32_t uar_page_id; 438 uint32_t q_umem_id; 439 uint64_t q_umem_offset; 440 uint32_t db_umem_id; 441 uint64_t db_umem_offset; 442 uint32_t eqn; 443 uint64_t db_addr; 444 }; 445 446 /* Virtq attributes structure, used by VIRTQ operations. */ 447 struct mlx5_devx_virtq_attr { 448 uint16_t hw_available_index; 449 uint16_t hw_used_index; 450 uint16_t q_size; 451 uint32_t pd:24; 452 uint32_t virtio_version_1_0:1; 453 uint32_t tso_ipv4:1; 454 uint32_t tso_ipv6:1; 455 uint32_t tx_csum:1; 456 uint32_t rx_csum:1; 457 uint32_t event_mode:3; 458 uint32_t state:4; 459 uint32_t hw_latency_mode:2; 460 uint32_t hw_max_latency_us:12; 461 uint32_t hw_max_pending_comp:16; 462 uint32_t dirty_bitmap_dump_enable:1; 463 uint32_t dirty_bitmap_mkey; 464 uint32_t dirty_bitmap_size; 465 uint32_t mkey; 466 uint32_t qp_id; 467 uint32_t queue_index; 468 uint32_t tis_id; 469 uint32_t counters_obj_id; 470 uint64_t dirty_bitmap_addr; 471 uint64_t mod_fields_bitmap; 472 uint64_t desc_addr; 473 uint64_t used_addr; 474 uint64_t available_addr; 475 struct { 476 uint32_t id; 477 uint32_t size; 478 uint64_t offset; 479 } umems[3]; 480 uint8_t error_type; 481 uint8_t q_type; 482 }; 483 484 485 struct mlx5_devx_qp_attr { 486 uint32_t pd:24; 487 uint32_t uar_index:24; 488 uint32_t cqn:24; 489 uint32_t log_page_size:5; 490 uint32_t num_of_receive_wqes:17; /* Must be power of 2. */ 491 uint32_t log_rq_stride:3; 492 uint32_t num_of_send_wqbbs:17; /* Must be power of 2. */ 493 uint32_t ts_format:2; 494 uint32_t dbr_umem_valid:1; 495 uint32_t dbr_umem_id; 496 uint64_t dbr_address; 497 uint32_t wq_umem_id; 498 uint64_t wq_umem_offset; 499 uint32_t user_index:24; 500 uint32_t mmo:1; 501 }; 502 503 struct mlx5_devx_virtio_q_couners_attr { 504 uint64_t received_desc; 505 uint64_t completed_desc; 506 uint32_t error_cqes; 507 uint32_t bad_desc_errors; 508 uint32_t exceed_max_chain; 509 uint32_t invalid_buffer; 510 }; 511 512 /* 513 * graph flow match sample attributes structure, 514 * used by flex parser operations. 515 */ 516 struct mlx5_devx_match_sample_attr { 517 uint32_t flow_match_sample_en:1; 518 uint32_t flow_match_sample_field_offset:16; 519 uint32_t flow_match_sample_offset_mode:4; 520 uint32_t flow_match_sample_field_offset_mask; 521 uint32_t flow_match_sample_field_offset_shift:4; 522 uint32_t flow_match_sample_field_base_offset:8; 523 uint32_t flow_match_sample_tunnel_mode:3; 524 uint32_t flow_match_sample_field_id; 525 }; 526 527 /* graph node arc attributes structure, used by flex parser operations. */ 528 struct mlx5_devx_graph_arc_attr { 529 uint32_t compare_condition_value:16; 530 uint32_t start_inner_tunnel:1; 531 uint32_t arc_parse_graph_node:8; 532 uint32_t parse_graph_node_handle; 533 }; 534 535 /* Maximal number of samples per graph node. */ 536 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 537 538 /* Maximal number of input/output arcs per graph node. */ 539 #define MLX5_GRAPH_NODE_ARC_NUM 8 540 541 /* parse graph node attributes structure, used by flex parser operations. */ 542 struct mlx5_devx_graph_node_attr { 543 uint32_t modify_field_select; 544 uint32_t header_length_mode:4; 545 uint32_t header_length_base_value:16; 546 uint32_t header_length_field_shift:4; 547 uint32_t header_length_field_offset:16; 548 uint32_t header_length_field_mask; 549 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 550 uint32_t next_header_field_offset:16; 551 uint32_t next_header_field_size:5; 552 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 553 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 554 }; 555 556 /* Encryption key size is up to 1024 bit, 128 bytes. */ 557 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 558 559 struct mlx5_devx_dek_attr { 560 uint32_t key_size:4; 561 uint32_t has_keytag:1; 562 uint32_t key_purpose:4; 563 uint32_t pd:24; 564 uint64_t opaque; 565 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 566 }; 567 568 struct mlx5_devx_import_kek_attr { 569 uint64_t modify_field_select; 570 uint32_t state:8; 571 uint32_t key_size:4; 572 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 573 }; 574 575 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 576 577 struct mlx5_devx_credential_attr { 578 uint64_t modify_field_select; 579 uint32_t state:8; 580 uint32_t credential_role:8; 581 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 582 }; 583 584 struct mlx5_devx_crypto_login_attr { 585 uint64_t modify_field_select; 586 uint32_t credential_pointer:24; 587 uint32_t session_import_kek_ptr:24; 588 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 589 }; 590 591 /* mlx5_devx_cmds.c */ 592 593 __rte_internal 594 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 595 uint32_t bulk_sz); 596 __rte_internal 597 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 598 __rte_internal 599 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 600 int clear, uint32_t n_counters, 601 uint64_t *pkts, uint64_t *bytes, 602 uint32_t mkey, void *addr, 603 void *cmd_comp, 604 uint64_t async_id); 605 __rte_internal 606 int mlx5_devx_cmd_query_hca_attr(void *ctx, 607 struct mlx5_hca_attr *attr); 608 __rte_internal 609 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 610 struct mlx5_devx_mkey_attr *attr); 611 __rte_internal 612 int mlx5_devx_get_out_command_status(void *out); 613 __rte_internal 614 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 615 uint32_t *tis_td); 616 __rte_internal 617 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 618 struct mlx5_devx_create_rq_attr *rq_attr, 619 int socket); 620 __rte_internal 621 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 622 struct mlx5_devx_modify_rq_attr *rq_attr); 623 __rte_internal 624 struct mlx5_devx_obj *mlx5_devx_cmd_create_rmp(void *ctx, 625 struct mlx5_devx_create_rmp_attr *rq_attr, int socket); 626 __rte_internal 627 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 628 struct mlx5_devx_tir_attr *tir_attr); 629 __rte_internal 630 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 631 struct mlx5_devx_rqt_attr *rqt_attr); 632 __rte_internal 633 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 634 struct mlx5_devx_create_sq_attr *sq_attr); 635 __rte_internal 636 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 637 struct mlx5_devx_modify_sq_attr *sq_attr); 638 __rte_internal 639 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 640 struct mlx5_devx_tis_attr *tis_attr); 641 __rte_internal 642 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 643 __rte_internal 644 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 645 FILE *file); 646 __rte_internal 647 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 648 __rte_internal 649 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 650 struct mlx5_devx_cq_attr *attr); 651 __rte_internal 652 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 653 struct mlx5_devx_virtq_attr *attr); 654 __rte_internal 655 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 656 struct mlx5_devx_virtq_attr *attr); 657 __rte_internal 658 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 659 struct mlx5_devx_virtq_attr *attr); 660 __rte_internal 661 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 662 struct mlx5_devx_qp_attr *attr); 663 __rte_internal 664 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 665 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 666 __rte_internal 667 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 668 struct mlx5_devx_rqt_attr *rqt_attr); 669 __rte_internal 670 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 671 struct mlx5_devx_modify_tir_attr *tir_attr); 672 __rte_internal 673 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 674 uint32_t ids[], uint32_t num); 675 676 __rte_internal 677 struct mlx5_devx_obj * 678 mlx5_devx_cmd_create_flex_parser(void *ctx, 679 struct mlx5_devx_graph_node_attr *data); 680 681 __rte_internal 682 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 683 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 684 685 __rte_internal 686 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 687 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 688 689 __rte_internal 690 struct mlx5_devx_obj * 691 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 692 uint16_t class, uint8_t type, uint8_t len); 693 694 /** 695 * Create virtio queue counters object DevX API. 696 * 697 * @param[in] ctx 698 * Device context. 699 700 * @return 701 * The DevX object created, NULL otherwise and rte_errno is set. 702 */ 703 __rte_internal 704 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 705 706 /** 707 * Query virtio queue counters object using DevX API. 708 * 709 * @param[in] couners_obj 710 * Pointer to virtq object structure. 711 * @param [in/out] attr 712 * Pointer to virtio queue counters attributes structure. 713 * 714 * @return 715 * 0 on success, a negative errno value otherwise and rte_errno is set. 716 */ 717 __rte_internal 718 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 719 struct mlx5_devx_virtio_q_couners_attr *attr); 720 __rte_internal 721 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 722 uint32_t pd); 723 __rte_internal 724 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 725 726 __rte_internal 727 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 728 729 __rte_internal 730 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 731 __rte_internal 732 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 733 uint32_t *out_of_buffers); 734 __rte_internal 735 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 736 uint32_t pd, uint32_t log_obj_size); 737 738 /** 739 * Create general object of type FLOW_METER_ASO using DevX API.. 740 * 741 * @param[in] ctx 742 * Device context. 743 * @param [in] pd 744 * PD value to associate the FLOW_METER_ASO object with. 745 * @param [in] log_obj_size 746 * log_obj_size define to allocate number of 2 * meters 747 * in one FLOW_METER_ASO object. 748 * 749 * @return 750 * The DevX object created, NULL otherwise and rte_errno is set. 751 */ 752 __rte_internal 753 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 754 uint32_t pd, uint32_t log_obj_size); 755 __rte_internal 756 struct mlx5_devx_obj * 757 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 758 759 __rte_internal 760 struct mlx5_devx_obj * 761 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 762 struct mlx5_devx_import_kek_attr *attr); 763 764 __rte_internal 765 struct mlx5_devx_obj * 766 mlx5_devx_cmd_create_credential_obj(void *ctx, 767 struct mlx5_devx_credential_attr *attr); 768 769 __rte_internal 770 struct mlx5_devx_obj * 771 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 772 struct mlx5_devx_crypto_login_attr *attr); 773 774 __rte_internal 775 int 776 mlx5_devx_cmd_query_lag(void *ctx, 777 struct mlx5_devx_lag_context *lag_ctx); 778 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 779