1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include <rte_compat.h> 9 #include <rte_bitops.h> 10 11 #include "mlx5_glue.h" 12 #include "mlx5_prm.h" 13 14 /* This is limitation of libibverbs: in length variable type is u16. */ 15 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 16 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 17 18 struct mlx5_devx_counter_attr { 19 uint32_t pd_valid:1; 20 uint32_t pd:24; 21 uint32_t bulk_log_max_alloc:1; 22 union { 23 uint8_t flow_counter_bulk_log_size; 24 uint8_t bulk_n_128; 25 }; 26 }; 27 28 struct mlx5_devx_mkey_attr { 29 uint64_t addr; 30 uint64_t size; 31 uint32_t umem_id; 32 uint32_t pd; 33 uint32_t log_entity_size; 34 uint32_t pg_access:1; 35 uint32_t relaxed_ordering_write:1; 36 uint32_t relaxed_ordering_read:1; 37 uint32_t umr_en:1; 38 uint32_t crypto_en:2; 39 uint32_t set_remote_rw:1; 40 struct mlx5_klm *klm_array; 41 int klm_num; 42 }; 43 44 /* HCA qos attributes. */ 45 struct mlx5_hca_qos_attr { 46 uint32_t sup:1; /* Whether QOS is supported. */ 47 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 48 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 49 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 50 uint32_t flow_meter:1; 51 /* 52 * Flow meter is supported, updated version. 53 * When flow_meter is 1, it indicates that REG_C sharing is supported. 54 * If flow_meter is 1, flow_meter_old is also 1. 55 * Using older driver versions, flow_meter_old can be 1 56 * while flow_meter is 0. 57 */ 58 uint32_t flow_meter_aso_sup:1; 59 /* Whether FLOW_METER_ASO Object is supported. */ 60 uint8_t log_max_flow_meter; 61 /* Power of the maximum supported meters. */ 62 uint8_t flow_meter_reg_c_ids; 63 /* Bitmap of the reg_Cs available for flow meter to use. */ 64 uint32_t log_meter_aso_granularity:5; 65 /* Power of the minimum allocation granularity Object. */ 66 uint32_t log_meter_aso_max_alloc:5; 67 /* Power of the maximum allocation granularity Object. */ 68 uint32_t log_max_num_meter_aso:5; 69 /* Power of the maximum number of supported objects. */ 70 71 }; 72 73 struct mlx5_hca_vdpa_attr { 74 uint8_t virtio_queue_type; 75 uint32_t valid:1; 76 uint32_t desc_tunnel_offload_type:1; 77 uint32_t eth_frame_offload_type:1; 78 uint32_t virtio_version_1_0:1; 79 uint32_t tso_ipv4:1; 80 uint32_t tso_ipv6:1; 81 uint32_t tx_csum:1; 82 uint32_t rx_csum:1; 83 uint32_t event_mode:3; 84 uint32_t log_doorbell_stride:5; 85 uint32_t log_doorbell_bar_size:5; 86 uint32_t queue_counters_valid:1; 87 uint32_t vnet_modify_ext:1; 88 uint32_t virtio_net_q_addr_modify:1; 89 uint32_t virtio_q_index_modify:1; 90 uint32_t max_num_virtio_queues; 91 struct { 92 uint32_t a; 93 uint32_t b; 94 } umems[3]; 95 uint64_t doorbell_bar_offset; 96 }; 97 98 struct mlx5_hca_flow_attr { 99 uint32_t tunnel_header_0_1; 100 uint32_t tunnel_header_2_3; 101 }; 102 103 /** 104 * Accumulate port PARSE_GRAPH_NODE capabilities from 105 * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables 106 */ 107 __extension__ 108 struct mlx5_hca_flex_attr { 109 uint32_t node_in; 110 uint32_t node_out; 111 uint16_t header_length_mode; 112 uint16_t sample_offset_mode; 113 uint8_t max_num_arc_in; 114 uint8_t max_num_arc_out; 115 uint8_t max_num_sample; 116 uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ 117 uint8_t anchor_en:1; 118 uint8_t ext_sample_id:1; 119 uint8_t sample_tunnel_inner2:1; 120 uint8_t zero_size_supported:1; 121 uint8_t sample_id_in_out:1; 122 uint16_t max_base_header_length; 123 uint8_t max_sample_base_offset; 124 uint16_t max_next_header_offset; 125 uint8_t header_length_mask_width; 126 }; 127 128 /* ISO C restricts enumerator values to range of 'int' */ 129 __extension__ 130 enum { 131 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1), 132 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2), 133 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3), 134 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4), 135 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5), 136 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6), 137 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7), 138 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8), 139 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9), 140 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10), 141 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11), 142 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12), 143 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31) 144 }; 145 146 enum { 147 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0), 148 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1), 149 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2) 150 }; 151 152 /* 153 * DWORD shift is the base for calculating header_length_field_mask 154 * value in the MLX5_GRAPH_NODE_LEN_FIELD mode. 155 */ 156 #define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02 157 158 static inline uint32_t 159 mlx5_hca_parse_graph_node_base_hdr_len_mask 160 (const struct mlx5_hca_flex_attr *attr) 161 { 162 return (1 << attr->header_length_mask_width) - 1; 163 } 164 165 /* HCA supports this number of time periods for LRO. */ 166 #define MLX5_LRO_NUM_SUPP_PERIODS 4 167 168 /* HCA attributes. */ 169 struct mlx5_hca_attr { 170 uint32_t eswitch_manager:1; 171 uint32_t flow_counters_dump:1; 172 uint32_t mem_rq_rmp:1; 173 uint32_t log_max_rmp:5; 174 uint32_t log_max_rqt_size:5; 175 uint32_t parse_graph_flex_node:1; 176 uint8_t flow_counter_bulk_alloc_bitmap; 177 uint32_t eth_net_offloads:1; 178 uint32_t eth_virt:1; 179 uint32_t wqe_vlan_insert:1; 180 uint32_t csum_cap:1; 181 uint32_t vlan_cap:1; 182 uint32_t wqe_inline_mode:2; 183 uint32_t vport_inline_mode:3; 184 uint32_t tunnel_stateless_geneve_rx:1; 185 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 186 uint32_t tunnel_stateless_gtp:1; 187 uint32_t max_lso_cap; 188 uint32_t scatter_fcs:1; 189 uint32_t lro_cap:1; 190 uint32_t tunnel_lro_gre:1; 191 uint32_t tunnel_lro_vxlan:1; 192 uint32_t tunnel_stateless_gre:1; 193 uint32_t tunnel_stateless_vxlan:1; 194 uint32_t swp:1; 195 uint32_t swp_csum:1; 196 uint32_t swp_lso:1; 197 uint32_t lro_max_msg_sz_mode:2; 198 uint32_t rq_delay_drop:1; 199 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 200 uint16_t lro_min_mss_size; 201 uint32_t flex_parser_protocols; 202 uint32_t max_geneve_tlv_options; 203 uint32_t max_geneve_tlv_option_data_len; 204 uint32_t hairpin:1; 205 uint32_t log_max_hairpin_queues:5; 206 uint32_t log_max_hairpin_wq_data_sz:5; 207 uint32_t log_max_hairpin_num_packets:5; 208 uint32_t hairpin_sq_wqe_bb_size:4; 209 uint32_t hairpin_sq_wq_in_host_mem:1; 210 uint32_t hairpin_data_buffer_locked:1; 211 uint32_t vhca_id:16; 212 uint32_t relaxed_ordering_write:1; 213 uint32_t relaxed_ordering_read:1; 214 uint32_t access_register_user:1; 215 uint32_t wqe_index_ignore:1; 216 uint32_t cross_channel:1; 217 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 218 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 219 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 220 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 221 uint32_t scatter_fcs_w_decap_disable:1; 222 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 223 uint32_t roce:1; 224 uint32_t wait_on_time:1; 225 uint32_t rq_ts_format:2; 226 uint32_t sq_ts_format:2; 227 uint32_t steering_format_version:4; 228 uint32_t qp_ts_format:2; 229 uint32_t regexp_params:1; 230 uint32_t regexp_version:3; 231 uint32_t reg_c_preserve:1; 232 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 233 uint32_t crypto:1; /* Crypto engine is supported. */ 234 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 235 uint32_t dek:1; /* General obj type DEK is supported. */ 236 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 237 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 238 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 239 uint32_t regexp_num_of_engines; 240 uint32_t log_max_ft_sampler_num:8; 241 uint32_t inner_ipv4_ihl:1; 242 uint32_t outer_ipv4_ihl:1; 243 uint32_t geneve_tlv_opt; 244 uint32_t cqe_compression:1; 245 uint32_t mini_cqe_resp_flow_tag:1; 246 uint32_t mini_cqe_resp_l3_l4_tag:1; 247 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 248 struct mlx5_hca_qos_attr qos; 249 struct mlx5_hca_vdpa_attr vdpa; 250 struct mlx5_hca_flow_attr flow; 251 struct mlx5_hca_flex_attr flex; 252 int log_max_qp_sz; 253 int log_max_cq_sz; 254 int log_max_qp; 255 int log_max_cq; 256 uint32_t log_max_pd; 257 uint32_t log_max_mrw_sz; 258 uint32_t log_max_srq; 259 uint32_t log_max_srq_sz; 260 uint32_t rss_ind_tbl_cap; 261 uint32_t mmo_dma_sq_en:1; 262 uint32_t mmo_compress_sq_en:1; 263 uint32_t mmo_decompress_sq_en:1; 264 uint32_t mmo_dma_qp_en:1; 265 uint32_t mmo_compress_qp_en:1; 266 uint32_t mmo_decompress_qp_en:1; 267 uint32_t mmo_regex_qp_en:1; 268 uint32_t mmo_regex_sq_en:1; 269 uint32_t compress_min_block_size:4; 270 uint32_t log_max_mmo_dma:5; 271 uint32_t log_max_mmo_compress:5; 272 uint32_t log_max_mmo_decompress:5; 273 uint32_t umr_modify_entity_size_disabled:1; 274 uint32_t umr_indirect_mkey_disabled:1; 275 uint32_t log_min_stride_wqe_sz:5; 276 uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */ 277 uint32_t crypto_wrapped_import_method:1; 278 uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */ 279 uint16_t max_wqe_sz_sq; 280 uint32_t set_reg_c:8; 281 uint32_t nic_flow_table:1; 282 uint32_t modify_outer_ip_ecn:1; 283 union { 284 uint32_t max_flow_counter; 285 struct { 286 uint16_t max_flow_counter_15_0; 287 uint16_t max_flow_counter_31_16; 288 }; 289 }; 290 uint32_t flow_counter_bulk_log_max_alloc:5; 291 uint32_t flow_counter_bulk_log_granularity:5; 292 uint32_t alloc_flow_counter_pd:1; 293 uint32_t flow_counter_access_aso:1; 294 uint32_t flow_access_aso_opc_mod:8; 295 uint32_t cross_vhca:1; 296 }; 297 298 /* LAG Context. */ 299 struct mlx5_devx_lag_context { 300 uint32_t fdb_selection_mode:1; 301 uint32_t port_select_mode:3; 302 uint32_t lag_state:3; 303 uint32_t tx_remap_affinity_1:4; 304 uint32_t tx_remap_affinity_2:4; 305 }; 306 307 struct mlx5_devx_wq_attr { 308 uint32_t wq_type:4; 309 uint32_t wq_signature:1; 310 uint32_t end_padding_mode:2; 311 uint32_t cd_slave:1; 312 uint32_t hds_skip_first_sge:1; 313 uint32_t log2_hds_buf_size:3; 314 uint32_t page_offset:5; 315 uint32_t lwm:16; 316 uint32_t pd:24; 317 uint32_t uar_page:24; 318 uint64_t dbr_addr; 319 uint32_t hw_counter; 320 uint32_t sw_counter; 321 uint32_t log_wq_stride:4; 322 uint32_t log_wq_pg_sz:5; 323 uint32_t log_wq_sz:5; 324 uint32_t dbr_umem_valid:1; 325 uint32_t wq_umem_valid:1; 326 uint32_t log_hairpin_num_packets:5; 327 uint32_t log_hairpin_data_sz:5; 328 uint32_t single_wqe_log_num_of_strides:4; 329 uint32_t two_byte_shift_en:1; 330 uint32_t single_stride_log_num_of_bytes:3; 331 uint32_t dbr_umem_id; 332 uint32_t wq_umem_id; 333 uint64_t wq_umem_offset; 334 }; 335 336 /* Create RQ attributes structure, used by create RQ operation. */ 337 struct mlx5_devx_create_rq_attr { 338 uint32_t rlky:1; 339 uint32_t delay_drop_en:1; 340 uint32_t scatter_fcs:1; 341 uint32_t vsd:1; 342 uint32_t mem_rq_type:4; 343 uint32_t state:4; 344 uint32_t flush_in_error_en:1; 345 uint32_t hairpin:1; 346 uint32_t hairpin_data_buffer_type:3; 347 uint32_t ts_format:2; 348 uint32_t user_index:24; 349 uint32_t cqn:24; 350 uint32_t counter_set_id:8; 351 uint32_t rmpn:24; 352 struct mlx5_devx_wq_attr wq_attr; 353 }; 354 355 /* Modify RQ attributes structure, used by modify RQ operation. */ 356 struct mlx5_devx_modify_rq_attr { 357 uint32_t rqn:24; 358 uint32_t rq_state:4; /* Current RQ state. */ 359 uint32_t state:4; /* Required RQ state. */ 360 uint32_t scatter_fcs:1; 361 uint32_t vsd:1; 362 uint32_t counter_set_id:8; 363 uint32_t hairpin_peer_sq:24; 364 uint32_t hairpin_peer_vhca:16; 365 uint64_t modify_bitmask; 366 uint32_t lwm:16; /* Contained WQ lwm. */ 367 }; 368 369 /* Create RMP attributes structure, used by create RMP operation. */ 370 struct mlx5_devx_create_rmp_attr { 371 uint32_t rsvd0:8; 372 uint32_t state:4; 373 uint32_t rsvd1:20; 374 uint32_t basic_cyclic_rcv_wqe:1; 375 uint32_t rsvd4:31; 376 uint32_t rsvd8[10]; 377 struct mlx5_devx_wq_attr wq_attr; 378 }; 379 380 struct mlx5_rx_hash_field_select { 381 uint32_t l3_prot_type:1; 382 uint32_t l4_prot_type:1; 383 uint32_t selected_fields:30; 384 }; 385 386 /* TIR attributes structure, used by TIR operations. */ 387 struct mlx5_devx_tir_attr { 388 uint32_t disp_type:4; 389 uint32_t lro_timeout_period_usecs:16; 390 uint32_t lro_enable_mask:4; 391 uint32_t lro_max_msg_sz:8; 392 uint32_t inline_rqn:24; 393 uint32_t rx_hash_symmetric:1; 394 uint32_t tunneled_offload_en:1; 395 uint32_t indirect_table:24; 396 uint32_t rx_hash_fn:4; 397 uint32_t self_lb_block:2; 398 uint32_t transport_domain:24; 399 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 400 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 401 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 402 }; 403 404 /* TIR attributes structure, used by TIR modify. */ 405 struct mlx5_devx_modify_tir_attr { 406 uint32_t tirn:24; 407 uint64_t modify_bitmask; 408 struct mlx5_devx_tir_attr tir; 409 }; 410 411 /* RQT attributes structure, used by RQT operations. */ 412 struct mlx5_devx_rqt_attr { 413 uint8_t rq_type; 414 uint32_t rqt_max_size:16; 415 uint32_t rqt_actual_size:16; 416 uint32_t rq_list[]; 417 }; 418 419 /* TIS attributes structure. */ 420 struct mlx5_devx_tis_attr { 421 uint32_t strict_lag_tx_port_affinity:1; 422 uint32_t tls_en:1; 423 uint32_t lag_tx_port_affinity:4; 424 uint32_t prio:4; 425 uint32_t transport_domain:24; 426 }; 427 428 /* SQ attributes structure, used by SQ create operation. */ 429 struct mlx5_devx_create_sq_attr { 430 uint32_t rlky:1; 431 uint32_t cd_master:1; 432 uint32_t fre:1; 433 uint32_t flush_in_error_en:1; 434 uint32_t allow_multi_pkt_send_wqe:1; 435 uint32_t min_wqe_inline_mode:3; 436 uint32_t state:4; 437 uint32_t reg_umr:1; 438 uint32_t allow_swp:1; 439 uint32_t hairpin:1; 440 uint32_t non_wire:1; 441 uint32_t static_sq_wq:1; 442 uint32_t ts_format:2; 443 uint32_t hairpin_wq_buffer_type:3; 444 uint32_t user_index:24; 445 uint32_t cqn:24; 446 uint32_t packet_pacing_rate_limit_index:16; 447 uint32_t tis_lst_sz:16; 448 uint32_t tis_num:24; 449 struct mlx5_devx_wq_attr wq_attr; 450 }; 451 452 /* SQ attributes structure, used by SQ modify operation. */ 453 struct mlx5_devx_modify_sq_attr { 454 uint32_t sq_state:4; 455 uint32_t state:4; 456 uint32_t hairpin_peer_rq:24; 457 uint32_t hairpin_peer_vhca:16; 458 }; 459 460 461 /* CQ attributes structure, used by CQ operations. */ 462 struct mlx5_devx_cq_attr { 463 uint32_t q_umem_valid:1; 464 uint32_t db_umem_valid:1; 465 uint32_t use_first_only:1; 466 uint32_t overrun_ignore:1; 467 uint32_t cqe_comp_en:1; 468 uint32_t mini_cqe_res_format:2; 469 uint32_t mini_cqe_res_format_ext:2; 470 uint32_t log_cq_size:5; 471 uint32_t log_page_size:5; 472 uint32_t uar_page_id; 473 uint32_t q_umem_id; 474 uint64_t q_umem_offset; 475 uint32_t db_umem_id; 476 uint64_t db_umem_offset; 477 uint32_t eqn; 478 uint64_t db_addr; 479 }; 480 481 /* Virtq attributes structure, used by VIRTQ operations. */ 482 struct mlx5_devx_virtq_attr { 483 uint16_t hw_available_index; 484 uint16_t hw_used_index; 485 uint16_t q_size; 486 uint32_t pd:24; 487 uint32_t virtio_version_1_0:1; 488 uint32_t tso_ipv4:1; 489 uint32_t tso_ipv6:1; 490 uint32_t tx_csum:1; 491 uint32_t rx_csum:1; 492 uint32_t event_mode:3; 493 uint32_t state:4; 494 uint32_t hw_latency_mode:2; 495 uint32_t hw_max_latency_us:12; 496 uint32_t hw_max_pending_comp:16; 497 uint32_t dirty_bitmap_dump_enable:1; 498 uint32_t dirty_bitmap_mkey; 499 uint32_t dirty_bitmap_size; 500 uint32_t mkey; 501 uint32_t qp_id; 502 uint32_t queue_index; 503 uint32_t tis_id; 504 uint32_t counters_obj_id; 505 uint64_t dirty_bitmap_addr; 506 uint64_t mod_fields_bitmap; 507 uint64_t desc_addr; 508 uint64_t used_addr; 509 uint64_t available_addr; 510 struct { 511 uint32_t id; 512 uint32_t size; 513 uint64_t offset; 514 } umems[3]; 515 uint8_t error_type; 516 uint8_t q_type; 517 }; 518 519 520 struct mlx5_devx_qp_attr { 521 uint32_t pd:24; 522 uint32_t uar_index:24; 523 uint32_t cqn:24; 524 uint32_t log_page_size:5; 525 uint32_t num_of_receive_wqes:17; /* Must be power of 2. */ 526 uint32_t log_rq_stride:3; 527 uint32_t num_of_send_wqbbs:17; /* Must be power of 2. */ 528 uint32_t ts_format:2; 529 uint32_t dbr_umem_valid:1; 530 uint32_t dbr_umem_id; 531 uint64_t dbr_address; 532 uint32_t wq_umem_id; 533 uint64_t wq_umem_offset; 534 uint32_t user_index:24; 535 uint32_t mmo:1; 536 }; 537 538 struct mlx5_devx_virtio_q_couners_attr { 539 uint64_t received_desc; 540 uint64_t completed_desc; 541 uint32_t error_cqes; 542 uint32_t bad_desc_errors; 543 uint32_t exceed_max_chain; 544 uint32_t invalid_buffer; 545 }; 546 547 /* 548 * graph flow match sample attributes structure, 549 * used by flex parser operations. 550 */ 551 struct mlx5_devx_match_sample_attr { 552 uint32_t flow_match_sample_en:1; 553 uint32_t flow_match_sample_field_offset:16; 554 uint32_t flow_match_sample_offset_mode:4; 555 uint32_t flow_match_sample_field_offset_mask; 556 uint32_t flow_match_sample_field_offset_shift:4; 557 uint32_t flow_match_sample_field_base_offset:8; 558 uint32_t flow_match_sample_tunnel_mode:3; 559 uint32_t flow_match_sample_field_id; 560 }; 561 562 /* graph node arc attributes structure, used by flex parser operations. */ 563 struct mlx5_devx_graph_arc_attr { 564 uint32_t compare_condition_value:16; 565 uint32_t start_inner_tunnel:1; 566 uint32_t arc_parse_graph_node:8; 567 uint32_t parse_graph_node_handle; 568 }; 569 570 /* Maximal number of samples per graph node. */ 571 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 572 573 /* Maximal number of input/output arcs per graph node. */ 574 #define MLX5_GRAPH_NODE_ARC_NUM 8 575 576 /* parse graph node attributes structure, used by flex parser operations. */ 577 struct mlx5_devx_graph_node_attr { 578 uint32_t modify_field_select; 579 uint32_t header_length_mode:4; 580 uint32_t header_length_base_value:16; 581 uint32_t header_length_field_shift:4; 582 uint32_t header_length_field_offset:16; 583 uint32_t header_length_field_mask; 584 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 585 uint32_t next_header_field_offset:16; 586 uint32_t next_header_field_size:5; 587 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 588 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 589 }; 590 591 /* Encryption key size is up to 1024 bit, 128 bytes. */ 592 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 593 594 struct mlx5_devx_dek_attr { 595 uint32_t key_size:4; 596 uint32_t has_keytag:1; 597 uint32_t key_purpose:4; 598 uint32_t pd:24; 599 uint64_t opaque; 600 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 601 }; 602 603 struct mlx5_devx_import_kek_attr { 604 uint64_t modify_field_select; 605 uint32_t state:8; 606 uint32_t key_size:4; 607 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 608 }; 609 610 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 611 612 struct mlx5_devx_credential_attr { 613 uint64_t modify_field_select; 614 uint32_t state:8; 615 uint32_t credential_role:8; 616 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 617 }; 618 619 struct mlx5_devx_crypto_login_attr { 620 uint64_t modify_field_select; 621 uint32_t credential_pointer:24; 622 uint32_t session_import_kek_ptr:24; 623 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 624 }; 625 626 /* mlx5_devx_cmds.c */ 627 628 __rte_internal 629 struct mlx5_devx_obj * 630 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 631 struct mlx5_devx_counter_attr *attr); 632 633 __rte_internal 634 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 635 uint32_t bulk_sz); 636 __rte_internal 637 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 638 __rte_internal 639 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 640 int clear, uint32_t n_counters, 641 uint64_t *pkts, uint64_t *bytes, 642 uint32_t mkey, void *addr, 643 void *cmd_comp, 644 uint64_t async_id); 645 __rte_internal 646 int mlx5_devx_cmd_query_hca_attr(void *ctx, 647 struct mlx5_hca_attr *attr); 648 __rte_internal 649 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 650 struct mlx5_devx_mkey_attr *attr); 651 __rte_internal 652 int mlx5_devx_get_out_command_status(void *out); 653 __rte_internal 654 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 655 uint32_t *tis_td); 656 __rte_internal 657 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 658 struct mlx5_devx_create_rq_attr *rq_attr, 659 int socket); 660 __rte_internal 661 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 662 struct mlx5_devx_modify_rq_attr *rq_attr); 663 __rte_internal 664 struct mlx5_devx_obj *mlx5_devx_cmd_create_rmp(void *ctx, 665 struct mlx5_devx_create_rmp_attr *rq_attr, int socket); 666 __rte_internal 667 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 668 struct mlx5_devx_tir_attr *tir_attr); 669 __rte_internal 670 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 671 struct mlx5_devx_rqt_attr *rqt_attr); 672 __rte_internal 673 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 674 struct mlx5_devx_create_sq_attr *sq_attr); 675 __rte_internal 676 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 677 struct mlx5_devx_modify_sq_attr *sq_attr); 678 __rte_internal 679 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 680 struct mlx5_devx_tis_attr *tis_attr); 681 __rte_internal 682 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 683 __rte_internal 684 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 685 FILE *file); 686 __rte_internal 687 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 688 __rte_internal 689 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 690 struct mlx5_devx_cq_attr *attr); 691 __rte_internal 692 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 693 struct mlx5_devx_virtq_attr *attr); 694 __rte_internal 695 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 696 struct mlx5_devx_virtq_attr *attr); 697 __rte_internal 698 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 699 struct mlx5_devx_virtq_attr *attr); 700 __rte_internal 701 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 702 struct mlx5_devx_qp_attr *attr); 703 __rte_internal 704 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 705 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 706 __rte_internal 707 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 708 struct mlx5_devx_rqt_attr *rqt_attr); 709 __rte_internal 710 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 711 struct mlx5_devx_modify_tir_attr *tir_attr); 712 __rte_internal 713 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 714 struct mlx5_ext_sample_id ids[], 715 uint32_t num, uint8_t *anchor); 716 717 __rte_internal 718 struct mlx5_devx_obj * 719 mlx5_devx_cmd_create_flex_parser(void *ctx, 720 struct mlx5_devx_graph_node_attr *data); 721 722 __rte_internal 723 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 724 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 725 726 __rte_internal 727 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 728 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 729 730 __rte_internal 731 struct mlx5_devx_obj * 732 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 733 uint16_t class, uint8_t type, uint8_t len); 734 735 /** 736 * Create virtio queue counters object DevX API. 737 * 738 * @param[in] ctx 739 * Device context. 740 741 * @return 742 * The DevX object created, NULL otherwise and rte_errno is set. 743 */ 744 __rte_internal 745 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 746 747 /** 748 * Query virtio queue counters object using DevX API. 749 * 750 * @param[in] couners_obj 751 * Pointer to virtq object structure. 752 * @param [in/out] attr 753 * Pointer to virtio queue counters attributes structure. 754 * 755 * @return 756 * 0 on success, a negative errno value otherwise and rte_errno is set. 757 */ 758 __rte_internal 759 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 760 struct mlx5_devx_virtio_q_couners_attr *attr); 761 __rte_internal 762 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 763 uint32_t pd); 764 __rte_internal 765 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 766 767 __rte_internal 768 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 769 770 __rte_internal 771 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 772 __rte_internal 773 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 774 uint32_t *out_of_buffers); 775 __rte_internal 776 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 777 uint32_t pd, uint32_t log_obj_size); 778 779 /** 780 * Create general object of type FLOW_METER_ASO using DevX API.. 781 * 782 * @param[in] ctx 783 * Device context. 784 * @param [in] pd 785 * PD value to associate the FLOW_METER_ASO object with. 786 * @param [in] log_obj_size 787 * log_obj_size define to allocate number of 2 * meters 788 * in one FLOW_METER_ASO object. 789 * 790 * @return 791 * The DevX object created, NULL otherwise and rte_errno is set. 792 */ 793 __rte_internal 794 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 795 uint32_t pd, uint32_t log_obj_size); 796 __rte_internal 797 struct mlx5_devx_obj * 798 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 799 800 __rte_internal 801 struct mlx5_devx_obj * 802 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 803 struct mlx5_devx_import_kek_attr *attr); 804 805 __rte_internal 806 struct mlx5_devx_obj * 807 mlx5_devx_cmd_create_credential_obj(void *ctx, 808 struct mlx5_devx_credential_attr *attr); 809 810 __rte_internal 811 struct mlx5_devx_obj * 812 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 813 struct mlx5_devx_crypto_login_attr *attr); 814 815 __rte_internal 816 int 817 mlx5_devx_cmd_query_lag(void *ctx, 818 struct mlx5_devx_lag_context *lag_ctx); 819 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 820