1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 11 12 /* This is limitation of libibverbs: in length variable type is u16. */ 13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 15 16 struct mlx5_devx_mkey_attr { 17 uint64_t addr; 18 uint64_t size; 19 uint32_t umem_id; 20 uint32_t pd; 21 uint32_t log_entity_size; 22 uint32_t pg_access:1; 23 uint32_t relaxed_ordering:1; 24 struct mlx5_klm *klm_array; 25 int klm_num; 26 }; 27 28 /* HCA qos attributes. */ 29 struct mlx5_hca_qos_attr { 30 uint32_t sup:1; /* Whether QOS is supported. */ 31 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ 32 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 33 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 34 uint32_t flow_meter_reg_share:1; 35 /* Whether reg_c share is supported. */ 36 uint8_t log_max_flow_meter; 37 /* Power of the maximum supported meters. */ 38 uint8_t flow_meter_reg_c_ids; 39 /* Bitmap of the reg_Cs available for flow meter to use. */ 40 41 }; 42 43 struct mlx5_hca_vdpa_attr { 44 uint8_t virtio_queue_type; 45 uint32_t valid:1; 46 uint32_t desc_tunnel_offload_type:1; 47 uint32_t eth_frame_offload_type:1; 48 uint32_t virtio_version_1_0:1; 49 uint32_t tso_ipv4:1; 50 uint32_t tso_ipv6:1; 51 uint32_t tx_csum:1; 52 uint32_t rx_csum:1; 53 uint32_t event_mode:3; 54 uint32_t log_doorbell_stride:5; 55 uint32_t log_doorbell_bar_size:5; 56 uint32_t queue_counters_valid:1; 57 uint32_t max_num_virtio_queues; 58 struct { 59 uint32_t a; 60 uint32_t b; 61 } umems[3]; 62 uint64_t doorbell_bar_offset; 63 }; 64 65 /* HCA supports this number of time periods for LRO. */ 66 #define MLX5_LRO_NUM_SUPP_PERIODS 4 67 68 /* HCA attributes. */ 69 struct mlx5_hca_attr { 70 uint32_t eswitch_manager:1; 71 uint32_t flow_counters_dump:1; 72 uint32_t log_max_rqt_size:5; 73 uint32_t parse_graph_flex_node:1; 74 uint8_t flow_counter_bulk_alloc_bitmap; 75 uint32_t eth_net_offloads:1; 76 uint32_t eth_virt:1; 77 uint32_t wqe_vlan_insert:1; 78 uint32_t wqe_inline_mode:2; 79 uint32_t vport_inline_mode:3; 80 uint32_t tunnel_stateless_geneve_rx:1; 81 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 82 uint32_t tunnel_stateless_gtp:1; 83 uint32_t lro_cap:1; 84 uint32_t tunnel_lro_gre:1; 85 uint32_t tunnel_lro_vxlan:1; 86 uint32_t lro_max_msg_sz_mode:2; 87 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 88 uint32_t flex_parser_protocols; 89 uint32_t hairpin:1; 90 uint32_t log_max_hairpin_queues:5; 91 uint32_t log_max_hairpin_wq_data_sz:5; 92 uint32_t log_max_hairpin_num_packets:5; 93 uint32_t vhca_id:16; 94 uint32_t relaxed_ordering_write:1; 95 uint32_t relaxed_ordering_read:1; 96 uint32_t wqe_index_ignore:1; 97 uint32_t cross_channel:1; 98 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 99 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 100 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 101 uint32_t scatter_fcs_w_decap_disable:1; 102 uint32_t regex:1; 103 uint32_t regexp_num_of_engines; 104 struct mlx5_hca_qos_attr qos; 105 struct mlx5_hca_vdpa_attr vdpa; 106 }; 107 108 struct mlx5_devx_wq_attr { 109 uint32_t wq_type:4; 110 uint32_t wq_signature:1; 111 uint32_t end_padding_mode:2; 112 uint32_t cd_slave:1; 113 uint32_t hds_skip_first_sge:1; 114 uint32_t log2_hds_buf_size:3; 115 uint32_t page_offset:5; 116 uint32_t lwm:16; 117 uint32_t pd:24; 118 uint32_t uar_page:24; 119 uint64_t dbr_addr; 120 uint32_t hw_counter; 121 uint32_t sw_counter; 122 uint32_t log_wq_stride:4; 123 uint32_t log_wq_pg_sz:5; 124 uint32_t log_wq_sz:5; 125 uint32_t dbr_umem_valid:1; 126 uint32_t wq_umem_valid:1; 127 uint32_t log_hairpin_num_packets:5; 128 uint32_t log_hairpin_data_sz:5; 129 uint32_t single_wqe_log_num_of_strides:4; 130 uint32_t two_byte_shift_en:1; 131 uint32_t single_stride_log_num_of_bytes:3; 132 uint32_t dbr_umem_id; 133 uint32_t wq_umem_id; 134 uint64_t wq_umem_offset; 135 }; 136 137 /* Create RQ attributes structure, used by create RQ operation. */ 138 struct mlx5_devx_create_rq_attr { 139 uint32_t rlky:1; 140 uint32_t delay_drop_en:1; 141 uint32_t scatter_fcs:1; 142 uint32_t vsd:1; 143 uint32_t mem_rq_type:4; 144 uint32_t state:4; 145 uint32_t flush_in_error_en:1; 146 uint32_t hairpin:1; 147 uint32_t user_index:24; 148 uint32_t cqn:24; 149 uint32_t counter_set_id:8; 150 uint32_t rmpn:24; 151 struct mlx5_devx_wq_attr wq_attr; 152 }; 153 154 /* Modify RQ attributes structure, used by modify RQ operation. */ 155 struct mlx5_devx_modify_rq_attr { 156 uint32_t rqn:24; 157 uint32_t rq_state:4; /* Current RQ state. */ 158 uint32_t state:4; /* Required RQ state. */ 159 uint32_t scatter_fcs:1; 160 uint32_t vsd:1; 161 uint32_t counter_set_id:8; 162 uint32_t hairpin_peer_sq:24; 163 uint32_t hairpin_peer_vhca:16; 164 uint64_t modify_bitmask; 165 uint32_t lwm:16; /* Contained WQ lwm. */ 166 }; 167 168 struct mlx5_rx_hash_field_select { 169 uint32_t l3_prot_type:1; 170 uint32_t l4_prot_type:1; 171 uint32_t selected_fields:30; 172 }; 173 174 /* TIR attributes structure, used by TIR operations. */ 175 struct mlx5_devx_tir_attr { 176 uint32_t disp_type:4; 177 uint32_t lro_timeout_period_usecs:16; 178 uint32_t lro_enable_mask:4; 179 uint32_t lro_max_msg_sz:8; 180 uint32_t inline_rqn:24; 181 uint32_t rx_hash_symmetric:1; 182 uint32_t tunneled_offload_en:1; 183 uint32_t indirect_table:24; 184 uint32_t rx_hash_fn:4; 185 uint32_t self_lb_block:2; 186 uint32_t transport_domain:24; 187 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 188 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 189 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 190 }; 191 192 /* RQT attributes structure, used by RQT operations. */ 193 struct mlx5_devx_rqt_attr { 194 uint8_t rq_type; 195 uint32_t rqt_max_size:16; 196 uint32_t rqt_actual_size:16; 197 uint32_t rq_list[]; 198 }; 199 200 /* TIS attributes structure. */ 201 struct mlx5_devx_tis_attr { 202 uint32_t strict_lag_tx_port_affinity:1; 203 uint32_t tls_en:1; 204 uint32_t lag_tx_port_affinity:4; 205 uint32_t prio:4; 206 uint32_t transport_domain:24; 207 }; 208 209 /* SQ attributes structure, used by SQ create operation. */ 210 struct mlx5_devx_create_sq_attr { 211 uint32_t rlky:1; 212 uint32_t cd_master:1; 213 uint32_t fre:1; 214 uint32_t flush_in_error_en:1; 215 uint32_t allow_multi_pkt_send_wqe:1; 216 uint32_t min_wqe_inline_mode:3; 217 uint32_t state:4; 218 uint32_t reg_umr:1; 219 uint32_t allow_swp:1; 220 uint32_t hairpin:1; 221 uint32_t non_wire:1; 222 uint32_t static_sq_wq:1; 223 uint32_t user_index:24; 224 uint32_t cqn:24; 225 uint32_t packet_pacing_rate_limit_index:16; 226 uint32_t tis_lst_sz:16; 227 uint32_t tis_num:24; 228 struct mlx5_devx_wq_attr wq_attr; 229 }; 230 231 /* SQ attributes structure, used by SQ modify operation. */ 232 struct mlx5_devx_modify_sq_attr { 233 uint32_t sq_state:4; 234 uint32_t state:4; 235 uint32_t hairpin_peer_rq:24; 236 uint32_t hairpin_peer_vhca:16; 237 }; 238 239 240 /* CQ attributes structure, used by CQ operations. */ 241 struct mlx5_devx_cq_attr { 242 uint32_t q_umem_valid:1; 243 uint32_t db_umem_valid:1; 244 uint32_t use_first_only:1; 245 uint32_t overrun_ignore:1; 246 uint32_t cqe_comp_en:1; 247 uint32_t mini_cqe_res_format:2; 248 uint32_t cqe_size:3; 249 uint32_t log_cq_size:5; 250 uint32_t log_page_size:5; 251 uint32_t uar_page_id; 252 uint32_t q_umem_id; 253 uint64_t q_umem_offset; 254 uint32_t db_umem_id; 255 uint64_t db_umem_offset; 256 uint32_t eqn; 257 uint64_t db_addr; 258 }; 259 260 /* Virtq attributes structure, used by VIRTQ operations. */ 261 struct mlx5_devx_virtq_attr { 262 uint16_t hw_available_index; 263 uint16_t hw_used_index; 264 uint16_t q_size; 265 uint32_t pd:24; 266 uint32_t virtio_version_1_0:1; 267 uint32_t tso_ipv4:1; 268 uint32_t tso_ipv6:1; 269 uint32_t tx_csum:1; 270 uint32_t rx_csum:1; 271 uint32_t event_mode:3; 272 uint32_t state:4; 273 uint32_t dirty_bitmap_dump_enable:1; 274 uint32_t dirty_bitmap_mkey; 275 uint32_t dirty_bitmap_size; 276 uint32_t mkey; 277 uint32_t qp_id; 278 uint32_t queue_index; 279 uint32_t tis_id; 280 uint32_t counters_obj_id; 281 uint64_t dirty_bitmap_addr; 282 uint64_t type; 283 uint64_t desc_addr; 284 uint64_t used_addr; 285 uint64_t available_addr; 286 struct { 287 uint32_t id; 288 uint32_t size; 289 uint64_t offset; 290 } umems[3]; 291 }; 292 293 294 struct mlx5_devx_qp_attr { 295 uint32_t pd:24; 296 uint32_t uar_index:24; 297 uint32_t cqn:24; 298 uint32_t log_page_size:5; 299 uint32_t rq_size:17; /* Must be power of 2. */ 300 uint32_t log_rq_stride:3; 301 uint32_t sq_size:17; /* Must be power of 2. */ 302 uint32_t dbr_umem_valid:1; 303 uint32_t dbr_umem_id; 304 uint64_t dbr_address; 305 uint32_t wq_umem_id; 306 uint64_t wq_umem_offset; 307 }; 308 309 struct mlx5_devx_virtio_q_couners_attr { 310 uint64_t received_desc; 311 uint64_t completed_desc; 312 uint32_t error_cqes; 313 uint32_t bad_desc_errors; 314 uint32_t exceed_max_chain; 315 uint32_t invalid_buffer; 316 }; 317 318 /* 319 * graph flow match sample attributes structure, 320 * used by flex parser operations. 321 */ 322 struct mlx5_devx_match_sample_attr { 323 uint32_t flow_match_sample_en:1; 324 uint32_t flow_match_sample_field_offset:16; 325 uint32_t flow_match_sample_offset_mode:4; 326 uint32_t flow_match_sample_field_offset_mask; 327 uint32_t flow_match_sample_field_offset_shift:4; 328 uint32_t flow_match_sample_field_base_offset:8; 329 uint32_t flow_match_sample_tunnel_mode:3; 330 uint32_t flow_match_sample_field_id; 331 }; 332 333 /* graph node arc attributes structure, used by flex parser operations. */ 334 struct mlx5_devx_graph_arc_attr { 335 uint32_t compare_condition_value:16; 336 uint32_t start_inner_tunnel:1; 337 uint32_t arc_parse_graph_node:8; 338 uint32_t parse_graph_node_handle; 339 }; 340 341 /* Maximal number of samples per graph node. */ 342 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 343 344 /* Maximal number of input/output arcs per graph node. */ 345 #define MLX5_GRAPH_NODE_ARC_NUM 8 346 347 /* parse graph node attributes structure, used by flex parser operations. */ 348 struct mlx5_devx_graph_node_attr { 349 uint32_t modify_field_select; 350 uint32_t header_length_mode:4; 351 uint32_t header_length_base_value:16; 352 uint32_t header_length_field_shift:4; 353 uint32_t header_length_field_offset:16; 354 uint32_t header_length_field_mask; 355 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 356 uint32_t next_header_field_offset:16; 357 uint32_t next_header_field_size:5; 358 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 359 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 360 }; 361 362 /* mlx5_devx_cmds.c */ 363 364 __rte_internal 365 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 366 uint32_t bulk_sz); 367 __rte_internal 368 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 369 __rte_internal 370 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 371 int clear, uint32_t n_counters, 372 uint64_t *pkts, uint64_t *bytes, 373 uint32_t mkey, void *addr, 374 void *cmd_comp, 375 uint64_t async_id); 376 __rte_internal 377 int mlx5_devx_cmd_query_hca_attr(void *ctx, 378 struct mlx5_hca_attr *attr); 379 __rte_internal 380 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 381 struct mlx5_devx_mkey_attr *attr); 382 __rte_internal 383 int mlx5_devx_get_out_command_status(void *out); 384 __rte_internal 385 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 386 uint32_t *tis_td); 387 __rte_internal 388 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 389 struct mlx5_devx_create_rq_attr *rq_attr, 390 int socket); 391 __rte_internal 392 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 393 struct mlx5_devx_modify_rq_attr *rq_attr); 394 __rte_internal 395 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 396 struct mlx5_devx_tir_attr *tir_attr); 397 __rte_internal 398 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 399 struct mlx5_devx_rqt_attr *rqt_attr); 400 __rte_internal 401 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 402 struct mlx5_devx_create_sq_attr *sq_attr); 403 __rte_internal 404 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 405 struct mlx5_devx_modify_sq_attr *sq_attr); 406 __rte_internal 407 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 408 struct mlx5_devx_tis_attr *tis_attr); 409 __rte_internal 410 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 411 __rte_internal 412 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 413 FILE *file); 414 __rte_internal 415 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 416 struct mlx5_devx_cq_attr *attr); 417 __rte_internal 418 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 419 struct mlx5_devx_virtq_attr *attr); 420 __rte_internal 421 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 422 struct mlx5_devx_virtq_attr *attr); 423 __rte_internal 424 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 425 struct mlx5_devx_virtq_attr *attr); 426 __rte_internal 427 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 428 struct mlx5_devx_qp_attr *attr); 429 __rte_internal 430 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 431 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 432 __rte_internal 433 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 434 struct mlx5_devx_rqt_attr *rqt_attr); 435 __rte_internal 436 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 437 uint32_t ids[], uint32_t num); 438 439 __rte_internal 440 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 441 struct mlx5_devx_graph_node_attr *data); 442 443 __rte_internal 444 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 445 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 446 /** 447 * Create virtio queue counters object DevX API. 448 * 449 * @param[in] ctx 450 * Device context. 451 452 * @return 453 * The DevX object created, NULL otherwise and rte_errno is set. 454 */ 455 __rte_internal 456 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 457 458 /** 459 * Query virtio queue counters object using DevX API. 460 * 461 * @param[in] couners_obj 462 * Pointer to virtq object structure. 463 * @param [in/out] attr 464 * Pointer to virtio queue counters attributes structure. 465 * 466 * @return 467 * 0 on success, a negative errno value otherwise and rte_errno is set. 468 */ 469 __rte_internal 470 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 471 struct mlx5_devx_virtio_q_couners_attr *attr); 472 473 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 474