1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include <rte_compat.h> 9 #include <rte_bitops.h> 10 11 #include "mlx5_glue.h" 12 #include "mlx5_prm.h" 13 14 /* This is limitation of libibverbs: in length variable type is u16. */ 15 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 16 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 17 18 struct mlx5_devx_counter_attr { 19 uint32_t pd_valid:1; 20 uint32_t pd:24; 21 uint32_t bulk_log_max_alloc:1; 22 union { 23 uint8_t flow_counter_bulk_log_size; 24 uint8_t bulk_n_128; 25 }; 26 }; 27 28 struct mlx5_devx_mkey_attr { 29 uint64_t addr; 30 uint64_t size; 31 uint32_t umem_id; 32 uint32_t pd; 33 uint32_t log_entity_size; 34 uint32_t pg_access:1; 35 uint32_t relaxed_ordering_write:1; 36 uint32_t relaxed_ordering_read:1; 37 uint32_t umr_en:1; 38 uint32_t crypto_en:2; 39 uint32_t set_remote_rw:1; 40 struct mlx5_klm *klm_array; 41 int klm_num; 42 }; 43 44 /* HCA qos attributes. */ 45 struct mlx5_hca_qos_attr { 46 uint32_t sup:1; /* Whether QOS is supported. */ 47 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 48 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 49 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 50 uint32_t flow_meter:1; 51 /* 52 * Flow meter is supported, updated version. 53 * When flow_meter is 1, it indicates that REG_C sharing is supported. 54 * If flow_meter is 1, flow_meter_old is also 1. 55 * Using older driver versions, flow_meter_old can be 1 56 * while flow_meter is 0. 57 */ 58 uint32_t flow_meter_aso_sup:1; 59 /* Whether FLOW_METER_ASO Object is supported. */ 60 uint8_t log_max_flow_meter; 61 /* Power of the maximum supported meters. */ 62 uint8_t flow_meter_reg_c_ids; 63 /* Bitmap of the reg_Cs available for flow meter to use. */ 64 uint32_t log_meter_aso_granularity:5; 65 /* Power of the minimum allocation granularity Object. */ 66 uint32_t log_meter_aso_max_alloc:5; 67 /* Power of the maximum allocation granularity Object. */ 68 uint32_t log_max_num_meter_aso:5; 69 /* Power of the maximum number of supported objects. */ 70 71 }; 72 73 struct mlx5_hca_vdpa_attr { 74 uint8_t virtio_queue_type; 75 uint32_t valid:1; 76 uint32_t desc_tunnel_offload_type:1; 77 uint32_t eth_frame_offload_type:1; 78 uint32_t virtio_version_1_0:1; 79 uint32_t tso_ipv4:1; 80 uint32_t tso_ipv6:1; 81 uint32_t tx_csum:1; 82 uint32_t rx_csum:1; 83 uint32_t event_mode:3; 84 uint32_t log_doorbell_stride:5; 85 uint32_t log_doorbell_bar_size:5; 86 uint32_t queue_counters_valid:1; 87 uint32_t vnet_modify_ext:1; 88 uint32_t virtio_net_q_addr_modify:1; 89 uint32_t virtio_q_index_modify:1; 90 uint32_t max_num_virtio_queues; 91 struct { 92 uint32_t a; 93 uint32_t b; 94 } umems[3]; 95 uint64_t doorbell_bar_offset; 96 }; 97 98 struct mlx5_hca_flow_attr { 99 uint32_t tunnel_header_0_1; 100 uint32_t tunnel_header_2_3; 101 }; 102 103 /** 104 * Accumulate port PARSE_GRAPH_NODE capabilities from 105 * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables 106 */ 107 __extension__ 108 struct mlx5_hca_flex_attr { 109 uint32_t node_in; 110 uint32_t node_out; 111 uint16_t header_length_mode; 112 uint16_t sample_offset_mode; 113 uint8_t max_num_arc_in; 114 uint8_t max_num_arc_out; 115 uint8_t max_num_sample; 116 uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ 117 uint8_t parse_graph_anchor:1; 118 uint8_t query_match_sample_info:1; /* Support DevX query sample info. */ 119 uint8_t sample_tunnel_inner2:1; 120 uint8_t zero_size_supported:1; 121 uint8_t sample_id_in_out:1; 122 uint16_t max_base_header_length; 123 uint8_t max_sample_base_offset; 124 uint16_t max_next_header_offset; 125 uint8_t header_length_mask_width; 126 }; 127 128 __extension__ 129 struct mlx5_hca_crypto_mmo_attr { 130 uint32_t crypto_mmo_qp:1; 131 uint32_t gcm_256_encrypt:1; 132 uint32_t gcm_128_encrypt:1; 133 uint32_t gcm_256_decrypt:1; 134 uint32_t gcm_128_decrypt:1; 135 uint32_t gcm_auth_tag_128:1; 136 uint32_t gcm_auth_tag_96:1; 137 uint32_t log_crypto_mmo_max_size:6; 138 }; 139 140 /* ISO C restricts enumerator values to range of 'int' */ 141 __extension__ 142 enum { 143 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1), 144 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2), 145 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3), 146 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4), 147 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5), 148 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6), 149 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7), 150 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8), 151 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9), 152 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10), 153 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11), 154 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12), 155 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31) 156 }; 157 158 enum { 159 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0), 160 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1), 161 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2) 162 }; 163 164 /* 165 * DWORD shift is the base for calculating header_length_field_mask 166 * value in the MLX5_GRAPH_NODE_LEN_FIELD mode. 167 */ 168 #define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02 169 170 static inline uint32_t 171 mlx5_hca_parse_graph_node_base_hdr_len_mask 172 (const struct mlx5_hca_flex_attr *attr) 173 { 174 return (1 << attr->header_length_mask_width) - 1; 175 } 176 177 /* HCA supports this number of time periods for LRO. */ 178 #define MLX5_LRO_NUM_SUPP_PERIODS 4 179 180 /* HCA attributes. */ 181 struct mlx5_hca_attr { 182 uint32_t eswitch_manager:1; 183 uint32_t flow_counters_dump:1; 184 uint32_t mem_rq_rmp:1; 185 uint32_t log_max_rmp:5; 186 uint32_t log_max_rqt_size:5; 187 uint32_t parse_graph_flex_node:1; 188 uint8_t flow_counter_bulk_alloc_bitmap; 189 uint32_t eth_net_offloads:1; 190 uint32_t eth_virt:1; 191 uint32_t wqe_vlan_insert:1; 192 uint32_t csum_cap:1; 193 uint32_t vlan_cap:1; 194 uint32_t wqe_inline_mode:2; 195 uint32_t vport_inline_mode:3; 196 uint32_t tunnel_stateless_geneve_rx:1; 197 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 198 uint32_t tunnel_stateless_gtp:1; 199 uint32_t tunnel_stateless_vxlan_gpe_nsh:1; 200 uint32_t max_lso_cap; 201 uint32_t scatter_fcs:1; 202 uint32_t lro_cap:1; 203 uint32_t tunnel_lro_gre:1; 204 uint32_t tunnel_lro_vxlan:1; 205 uint32_t tunnel_stateless_gre:1; 206 uint32_t tunnel_stateless_vxlan:1; 207 uint32_t swp:1; 208 uint32_t swp_csum:1; 209 uint32_t swp_lso:1; 210 uint32_t lro_max_msg_sz_mode:2; 211 uint32_t rq_delay_drop:1; 212 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 213 uint16_t lro_min_mss_size; 214 uint32_t flex_parser_protocols; 215 uint32_t max_geneve_tlv_options:8; 216 uint32_t max_geneve_tlv_option_data_len:5; 217 uint32_t geneve_tlv_sample:1; 218 uint32_t geneve_tlv_option_offset:1; 219 uint32_t geneve_tlv_option_sample_id:4; 220 uint32_t hairpin:1; 221 uint32_t log_max_hairpin_queues:5; 222 uint32_t log_max_hairpin_wq_data_sz:5; 223 uint32_t log_max_hairpin_num_packets:5; 224 uint32_t hairpin_sq_wqe_bb_size:4; 225 uint32_t hairpin_sq_wq_in_host_mem:1; 226 uint32_t hairpin_data_buffer_locked:1; 227 uint32_t vhca_id:16; 228 uint32_t relaxed_ordering_write:1; 229 uint32_t relaxed_ordering_read:1; 230 uint32_t access_register_user:1; 231 uint32_t wqe_index_ignore:1; 232 uint32_t cross_channel:1; 233 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 234 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 235 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 236 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 237 uint32_t scatter_fcs_w_decap_disable:1; 238 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 239 uint32_t roce:1; 240 uint32_t wait_on_time:1; 241 uint32_t rq_ts_format:2; 242 uint32_t sq_ts_format:2; 243 uint32_t steering_format_version:4; 244 uint32_t qp_ts_format:2; 245 uint32_t regexp_params:1; 246 uint32_t regexp_version:3; 247 uint32_t reg_c_preserve:1; 248 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 249 uint32_t crypto:1; /* Crypto engine is supported. */ 250 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 251 uint32_t dek:1; /* General obj type DEK is supported. */ 252 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 253 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 254 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 255 uint32_t regexp_num_of_engines; 256 uint32_t log_max_ft_sampler_num:8; 257 uint32_t inner_ipv4_ihl:1; 258 uint32_t outer_ipv4_ihl:1; 259 uint32_t geneve_tlv_opt; 260 uint32_t cqe_compression:1; 261 uint32_t mini_cqe_resp_flow_tag:1; 262 uint32_t mini_cqe_resp_l3_l4_tag:1; 263 uint32_t enhanced_cqe_compression:1; 264 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 265 struct mlx5_hca_qos_attr qos; 266 struct mlx5_hca_vdpa_attr vdpa; 267 struct mlx5_hca_flow_attr flow; 268 struct mlx5_hca_flex_attr flex; 269 struct mlx5_hca_crypto_mmo_attr crypto_mmo; 270 int log_max_qp_sz; 271 int log_max_cq_sz; 272 int log_max_qp; 273 int log_max_cq; 274 uint32_t log_max_pd; 275 uint32_t log_max_mrw_sz; 276 uint32_t log_max_srq; 277 uint32_t log_max_srq_sz; 278 uint32_t rss_ind_tbl_cap; 279 uint32_t mmo_dma_sq_en:1; 280 uint32_t mmo_compress_sq_en:1; 281 uint32_t mmo_decompress_sq_en:1; 282 uint32_t mmo_dma_qp_en:1; 283 uint32_t mmo_compress_qp_en:1; 284 uint32_t decomp_deflate_v1_en:1; 285 uint32_t decomp_deflate_v2_en:1; 286 uint32_t mmo_regex_qp_en:1; 287 uint32_t mmo_regex_sq_en:1; 288 uint32_t compress_min_block_size:4; 289 uint32_t log_max_mmo_dma:5; 290 uint32_t log_max_mmo_compress:5; 291 uint32_t log_max_mmo_decompress:5; 292 uint32_t decomp_lz4_data_only_en:1; 293 uint32_t decomp_lz4_no_checksum_en:1; 294 uint32_t decomp_lz4_checksum_en:1; 295 uint32_t umr_modify_entity_size_disabled:1; 296 uint32_t umr_indirect_mkey_disabled:1; 297 uint32_t log_min_stride_wqe_sz:5; 298 uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */ 299 uint32_t crypto_wrapped_import_method:1; 300 uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */ 301 uint16_t max_wqe_sz_sq; 302 uint32_t striding_rq:1; 303 uint32_t ext_stride_num_range:1; 304 uint32_t cqe_compression_128:1; 305 uint32_t multi_pkt_send_wqe:1; 306 uint32_t enhanced_multi_pkt_send_wqe:1; 307 uint32_t set_reg_c:16; 308 uint32_t nic_flow_table:1; 309 uint32_t modify_outer_ip_ecn:1; 310 uint32_t modify_outer_ipv6_traffic_class:1; 311 union { 312 uint32_t max_flow_counter; 313 struct { 314 uint16_t max_flow_counter_15_0; 315 uint16_t max_flow_counter_31_16; 316 }; 317 }; 318 uint32_t flow_counter_bulk_log_max_alloc:5; 319 uint32_t flow_counter_bulk_log_granularity:5; 320 uint32_t alloc_flow_counter_pd:1; 321 uint32_t flow_counter_access_aso:1; 322 uint32_t query_match_sample_info:1; 323 uint32_t flow_access_aso_opc_mod:8; 324 uint32_t cross_vhca:1; 325 uint32_t lag_rx_port_affinity:1; 326 uint32_t wqe_based_flow_table_sup:1; 327 uint8_t max_header_modify_pattern_length; 328 uint64_t system_image_guid; 329 }; 330 331 /* LAG Context. */ 332 struct mlx5_devx_lag_context { 333 uint32_t fdb_selection_mode:1; 334 uint32_t port_select_mode:3; 335 uint32_t lag_state:3; 336 uint32_t tx_remap_affinity_1:4; 337 uint32_t tx_remap_affinity_2:4; 338 }; 339 340 struct mlx5_devx_wq_attr { 341 uint32_t wq_type:4; 342 uint32_t wq_signature:1; 343 uint32_t end_padding_mode:2; 344 uint32_t cd_slave:1; 345 uint32_t hds_skip_first_sge:1; 346 uint32_t log2_hds_buf_size:3; 347 uint32_t page_offset:5; 348 uint32_t lwm:16; 349 uint32_t pd:24; 350 uint32_t uar_page:24; 351 uint64_t dbr_addr; 352 uint32_t hw_counter; 353 uint32_t sw_counter; 354 uint32_t log_wq_stride:4; 355 uint32_t log_wq_pg_sz:5; 356 uint32_t log_wq_sz:5; 357 uint32_t dbr_umem_valid:1; 358 uint32_t wq_umem_valid:1; 359 uint32_t log_hairpin_num_packets:5; 360 uint32_t log_hairpin_data_sz:5; 361 uint32_t single_wqe_log_num_of_strides:4; 362 uint32_t two_byte_shift_en:1; 363 uint32_t single_stride_log_num_of_bytes:3; 364 uint32_t dbr_umem_id; 365 uint32_t wq_umem_id; 366 uint64_t wq_umem_offset; 367 }; 368 369 /* Create RQ attributes structure, used by create RQ operation. */ 370 struct mlx5_devx_create_rq_attr { 371 uint32_t rlky:1; 372 uint32_t delay_drop_en:1; 373 uint32_t scatter_fcs:1; 374 uint32_t vsd:1; 375 uint32_t mem_rq_type:4; 376 uint32_t state:4; 377 uint32_t flush_in_error_en:1; 378 uint32_t hairpin:1; 379 uint32_t hairpin_data_buffer_type:3; 380 uint32_t ts_format:2; 381 uint32_t user_index:24; 382 uint32_t cqn:24; 383 uint32_t counter_set_id:8; 384 uint32_t rmpn:24; 385 struct mlx5_devx_wq_attr wq_attr; 386 }; 387 388 /* Modify RQ attributes structure, used by modify RQ operation. */ 389 struct mlx5_devx_modify_rq_attr { 390 uint32_t rqn:24; 391 uint32_t rq_state:4; /* Current RQ state. */ 392 uint32_t state:4; /* Required RQ state. */ 393 uint32_t scatter_fcs:1; 394 uint32_t vsd:1; 395 uint32_t counter_set_id:8; 396 uint32_t hairpin_peer_sq:24; 397 uint32_t hairpin_peer_vhca:16; 398 uint64_t modify_bitmask; 399 uint32_t lwm:16; /* Contained WQ lwm. */ 400 }; 401 402 /* Create RMP attributes structure, used by create RMP operation. */ 403 struct mlx5_devx_create_rmp_attr { 404 uint32_t rsvd0:8; 405 uint32_t state:4; 406 uint32_t rsvd1:20; 407 uint32_t basic_cyclic_rcv_wqe:1; 408 uint32_t rsvd4:31; 409 uint32_t rsvd8[10]; 410 struct mlx5_devx_wq_attr wq_attr; 411 }; 412 413 struct mlx5_rx_hash_field_select { 414 uint32_t l3_prot_type:1; 415 uint32_t l4_prot_type:1; 416 uint32_t selected_fields:30; 417 }; 418 419 /* TIR attributes structure, used by TIR operations. */ 420 struct mlx5_devx_tir_attr { 421 uint32_t disp_type:4; 422 uint32_t lro_timeout_period_usecs:16; 423 uint32_t lro_enable_mask:4; 424 uint32_t lro_max_msg_sz:8; 425 uint32_t inline_rqn:24; 426 uint32_t rx_hash_symmetric:1; 427 uint32_t tunneled_offload_en:1; 428 uint32_t indirect_table:24; 429 uint32_t rx_hash_fn:4; 430 uint32_t self_lb_block:2; 431 uint32_t transport_domain:24; 432 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 433 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 434 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 435 }; 436 437 /* TIR attributes structure, used by TIR modify. */ 438 struct mlx5_devx_modify_tir_attr { 439 uint32_t tirn:24; 440 uint64_t modify_bitmask; 441 struct mlx5_devx_tir_attr tir; 442 }; 443 444 /* RQT attributes structure, used by RQT operations. */ 445 struct mlx5_devx_rqt_attr { 446 uint8_t rq_type; 447 uint32_t rqt_max_size:16; 448 uint32_t rqt_actual_size:16; 449 uint32_t rq_list[]; 450 }; 451 452 /* TIS attributes structure. */ 453 struct mlx5_devx_tis_attr { 454 uint32_t strict_lag_tx_port_affinity:1; 455 uint32_t tls_en:1; 456 uint32_t lag_tx_port_affinity:4; 457 uint32_t prio:4; 458 uint32_t transport_domain:24; 459 }; 460 461 /* SQ attributes structure, used by SQ create operation. */ 462 struct mlx5_devx_create_sq_attr { 463 uint32_t rlky:1; 464 uint32_t cd_master:1; 465 uint32_t fre:1; 466 uint32_t flush_in_error_en:1; 467 uint32_t allow_multi_pkt_send_wqe:1; 468 uint32_t min_wqe_inline_mode:3; 469 uint32_t state:4; 470 uint32_t reg_umr:1; 471 uint32_t allow_swp:1; 472 uint32_t hairpin:1; 473 uint32_t non_wire:1; 474 uint32_t static_sq_wq:1; 475 uint32_t ts_format:2; 476 uint32_t hairpin_wq_buffer_type:3; 477 uint32_t user_index:24; 478 uint32_t cqn:24; 479 uint32_t packet_pacing_rate_limit_index:16; 480 uint32_t tis_lst_sz:16; 481 uint32_t tis_num:24; 482 struct mlx5_devx_wq_attr wq_attr; 483 }; 484 485 /* SQ attributes structure, used by SQ modify operation. */ 486 struct mlx5_devx_modify_sq_attr { 487 uint32_t sq_state:4; 488 uint32_t state:4; 489 uint32_t hairpin_peer_rq:24; 490 uint32_t hairpin_peer_vhca:16; 491 }; 492 493 494 /* CQ attributes structure, used by CQ operations. */ 495 struct mlx5_devx_cq_attr { 496 uint32_t q_umem_valid:1; 497 uint32_t db_umem_valid:1; 498 uint32_t use_first_only:1; 499 uint32_t overrun_ignore:1; 500 uint32_t cqe_comp_en:1; 501 uint32_t mini_cqe_res_format:2; 502 uint32_t mini_cqe_res_format_ext:2; 503 uint32_t cqe_comp_layout:2; 504 uint32_t log_cq_size:5; 505 uint32_t log_page_size:5; 506 uint32_t uar_page_id; 507 uint32_t q_umem_id; 508 uint64_t q_umem_offset; 509 uint32_t db_umem_id; 510 uint64_t db_umem_offset; 511 uint32_t eqn; 512 uint64_t db_addr; 513 }; 514 515 /* Virtq attributes structure, used by VIRTQ operations. */ 516 struct mlx5_devx_virtq_attr { 517 uint16_t hw_available_index; 518 uint16_t hw_used_index; 519 uint16_t q_size; 520 uint32_t pd:24; 521 uint32_t virtio_version_1_0:1; 522 uint32_t tso_ipv4:1; 523 uint32_t tso_ipv6:1; 524 uint32_t tx_csum:1; 525 uint32_t rx_csum:1; 526 uint32_t event_mode:3; 527 uint32_t state:4; 528 uint32_t hw_latency_mode:2; 529 uint32_t hw_max_latency_us:12; 530 uint32_t hw_max_pending_comp:16; 531 uint32_t dirty_bitmap_dump_enable:1; 532 uint32_t dirty_bitmap_mkey; 533 uint32_t dirty_bitmap_size; 534 uint32_t mkey; 535 uint32_t qp_id; 536 uint32_t queue_index; 537 uint32_t tis_id; 538 uint32_t counters_obj_id; 539 uint64_t dirty_bitmap_addr; 540 uint64_t mod_fields_bitmap; 541 uint64_t desc_addr; 542 uint64_t used_addr; 543 uint64_t available_addr; 544 struct { 545 uint32_t id; 546 uint32_t size; 547 uint64_t offset; 548 } umems[3]; 549 uint8_t error_type; 550 uint8_t q_type; 551 }; 552 553 struct mlx5_devx_qp_attr { 554 uint32_t pd:24; 555 uint32_t uar_index:24; 556 uint32_t cqn:24; 557 uint32_t log_page_size:5; 558 uint32_t num_of_receive_wqes:17; /* Must be power of 2. */ 559 uint32_t log_rq_stride:3; 560 uint32_t num_of_send_wqbbs:17; /* Must be power of 2. */ 561 uint32_t ts_format:2; 562 uint32_t dbr_umem_valid:1; 563 uint32_t dbr_umem_id; 564 uint64_t dbr_address; 565 uint32_t wq_umem_id; 566 uint64_t wq_umem_offset; 567 uint32_t user_index:24; 568 uint32_t mmo:1; 569 uint32_t cd_master:1; 570 uint32_t cd_slave_send:1; 571 uint32_t cd_slave_recv:1; 572 }; 573 574 struct mlx5_devx_virtio_q_couners_attr { 575 uint64_t received_desc; 576 uint64_t completed_desc; 577 uint32_t error_cqes; 578 uint32_t bad_desc_errors; 579 uint32_t exceed_max_chain; 580 uint32_t invalid_buffer; 581 }; 582 583 /* 584 * Match sample info attributes structure, used by: 585 * - GENEVE TLV option query. 586 * - Graph flow match sample query. 587 */ 588 struct mlx5_devx_match_sample_info_query_attr { 589 uint32_t modify_field_id:12; 590 uint32_t sample_dw_data:8; 591 uint32_t sample_dw_ok_bit:8; 592 uint32_t sample_dw_ok_bit_offset:5; 593 }; 594 595 /* 596 * graph flow match sample attributes structure, 597 * used by flex parser operations. 598 */ 599 struct mlx5_devx_match_sample_attr { 600 uint32_t flow_match_sample_en:1; 601 uint32_t flow_match_sample_field_offset:16; 602 uint32_t flow_match_sample_offset_mode:4; 603 uint32_t flow_match_sample_field_offset_mask; 604 uint32_t flow_match_sample_field_offset_shift:4; 605 uint32_t flow_match_sample_field_base_offset:8; 606 uint32_t flow_match_sample_tunnel_mode:3; 607 uint32_t flow_match_sample_field_id; 608 }; 609 610 /* graph node arc attributes structure, used by flex parser operations. */ 611 struct mlx5_devx_graph_arc_attr { 612 uint32_t compare_condition_value:16; 613 uint32_t start_inner_tunnel:1; 614 uint32_t arc_parse_graph_node:8; 615 uint32_t parse_graph_node_handle; 616 }; 617 618 /* Maximal number of samples per graph node. */ 619 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 620 621 /* Maximal number of input/output arcs per graph node. */ 622 #define MLX5_GRAPH_NODE_ARC_NUM 8 623 624 /* parse graph node attributes structure, used by flex parser operations. */ 625 struct mlx5_devx_graph_node_attr { 626 uint32_t modify_field_select; 627 uint32_t header_length_mode:4; 628 uint32_t header_length_base_value:16; 629 uint32_t header_length_field_shift:4; 630 uint32_t header_length_field_offset:16; 631 uint32_t header_length_field_mask; 632 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 633 uint32_t next_header_field_offset:16; 634 uint32_t next_header_field_size:5; 635 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 636 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 637 }; 638 639 /* Encryption key size is up to 1024 bit, 128 bytes. */ 640 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 641 642 struct mlx5_devx_dek_attr { 643 uint32_t key_size:4; 644 uint32_t has_keytag:1; 645 uint32_t key_purpose:4; 646 uint32_t pd:24; 647 uint64_t opaque; 648 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 649 }; 650 651 struct mlx5_devx_import_kek_attr { 652 uint64_t modify_field_select; 653 uint32_t state:8; 654 uint32_t key_size:4; 655 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 656 }; 657 658 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 659 660 struct mlx5_devx_credential_attr { 661 uint64_t modify_field_select; 662 uint32_t state:8; 663 uint32_t credential_role:8; 664 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 665 }; 666 667 struct mlx5_devx_crypto_login_attr { 668 uint64_t modify_field_select; 669 uint32_t credential_pointer:24; 670 uint32_t session_import_kek_ptr:24; 671 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 672 }; 673 674 /* 675 * GENEVE TLV option attributes structure, used by GENEVE TLV option create. 676 */ 677 struct mlx5_devx_geneve_tlv_option_attr { 678 uint32_t option_class:16; 679 uint32_t option_type:8; 680 uint32_t option_data_len:5; 681 uint32_t option_class_ignore:1; 682 uint32_t offset_valid:1; 683 uint32_t sample_offset:8; 684 }; 685 686 /* mlx5_devx_cmds.c */ 687 688 __rte_internal 689 struct mlx5_devx_obj * 690 mlx5_devx_cmd_flow_counter_alloc_general(void *ctx, 691 struct mlx5_devx_counter_attr *attr); 692 693 __rte_internal 694 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 695 uint32_t bulk_sz); 696 __rte_internal 697 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 698 __rte_internal 699 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 700 int clear, uint32_t n_counters, 701 uint64_t *pkts, uint64_t *bytes, 702 uint32_t mkey, void *addr, 703 void *cmd_comp, 704 uint64_t async_id); 705 __rte_internal 706 int mlx5_devx_cmd_query_hca_attr(void *ctx, 707 struct mlx5_hca_attr *attr); 708 __rte_internal 709 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 710 struct mlx5_devx_mkey_attr *attr); 711 __rte_internal 712 int mlx5_devx_get_out_command_status(void *out); 713 __rte_internal 714 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 715 uint32_t *tis_td); 716 __rte_internal 717 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 718 struct mlx5_devx_create_rq_attr *rq_attr, 719 int socket); 720 __rte_internal 721 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 722 struct mlx5_devx_modify_rq_attr *rq_attr); 723 __rte_internal 724 struct mlx5_devx_obj *mlx5_devx_cmd_create_rmp(void *ctx, 725 struct mlx5_devx_create_rmp_attr *rq_attr, int socket); 726 __rte_internal 727 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 728 struct mlx5_devx_tir_attr *tir_attr); 729 __rte_internal 730 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 731 struct mlx5_devx_rqt_attr *rqt_attr); 732 __rte_internal 733 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 734 struct mlx5_devx_create_sq_attr *sq_attr); 735 __rte_internal 736 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 737 struct mlx5_devx_modify_sq_attr *sq_attr); 738 __rte_internal 739 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 740 struct mlx5_devx_tis_attr *tis_attr); 741 __rte_internal 742 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 743 __rte_internal 744 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 745 FILE *file); 746 __rte_internal 747 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 748 __rte_internal 749 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 750 struct mlx5_devx_cq_attr *attr); 751 __rte_internal 752 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 753 struct mlx5_devx_virtq_attr *attr); 754 __rte_internal 755 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 756 struct mlx5_devx_virtq_attr *attr); 757 __rte_internal 758 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 759 struct mlx5_devx_virtq_attr *attr); 760 __rte_internal 761 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 762 struct mlx5_devx_qp_attr *attr); 763 __rte_internal 764 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 765 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 766 __rte_internal 767 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 768 struct mlx5_devx_rqt_attr *rqt_attr); 769 __rte_internal 770 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 771 struct mlx5_devx_modify_tir_attr *tir_attr); 772 __rte_internal 773 int mlx5_devx_cmd_match_sample_info_query(void *ctx, uint32_t sample_field_id, 774 struct mlx5_devx_match_sample_info_query_attr *attr); 775 __rte_internal 776 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 777 uint32_t *ids, 778 uint32_t num, uint8_t *anchor); 779 780 __rte_internal 781 struct mlx5_devx_obj * 782 mlx5_devx_cmd_create_flex_parser(void *ctx, 783 struct mlx5_devx_graph_node_attr *data); 784 785 __rte_internal 786 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 787 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 788 789 __rte_internal 790 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 791 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 792 793 __rte_internal 794 struct mlx5_devx_obj * 795 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 796 struct mlx5_devx_geneve_tlv_option_attr *attr); 797 798 __rte_internal 799 int 800 mlx5_devx_cmd_query_geneve_tlv_option(void *ctx, 801 struct mlx5_devx_obj *geneve_tlv_opt_obj, 802 struct mlx5_devx_match_sample_info_query_attr *attr); 803 804 /** 805 * Create virtio queue counters object DevX API. 806 * 807 * @param[in] ctx 808 * Device context. 809 810 * @return 811 * The DevX object created, NULL otherwise and rte_errno is set. 812 */ 813 __rte_internal 814 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 815 816 /** 817 * Query virtio queue counters object using DevX API. 818 * 819 * @param[in] couners_obj 820 * Pointer to virtq object structure. 821 * @param [in/out] attr 822 * Pointer to virtio queue counters attributes structure. 823 * 824 * @return 825 * 0 on success, a negative errno value otherwise and rte_errno is set. 826 */ 827 __rte_internal 828 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 829 struct mlx5_devx_virtio_q_couners_attr *attr); 830 __rte_internal 831 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 832 uint32_t pd); 833 __rte_internal 834 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 835 836 __rte_internal 837 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 838 839 __rte_internal 840 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 841 __rte_internal 842 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 843 uint32_t *out_of_buffers); 844 __rte_internal 845 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 846 uint32_t pd, uint32_t log_obj_size); 847 848 /** 849 * Create general object of type FLOW_METER_ASO using DevX API.. 850 * 851 * @param[in] ctx 852 * Device context. 853 * @param [in] pd 854 * PD value to associate the FLOW_METER_ASO object with. 855 * @param [in] log_obj_size 856 * log_obj_size define to allocate number of 2 * meters 857 * in one FLOW_METER_ASO object. 858 * 859 * @return 860 * The DevX object created, NULL otherwise and rte_errno is set. 861 */ 862 __rte_internal 863 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 864 uint32_t pd, uint32_t log_obj_size); 865 __rte_internal 866 struct mlx5_devx_obj * 867 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 868 869 __rte_internal 870 struct mlx5_devx_obj * 871 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 872 struct mlx5_devx_import_kek_attr *attr); 873 874 __rte_internal 875 struct mlx5_devx_obj * 876 mlx5_devx_cmd_create_credential_obj(void *ctx, 877 struct mlx5_devx_credential_attr *attr); 878 879 __rte_internal 880 struct mlx5_devx_obj * 881 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 882 struct mlx5_devx_crypto_login_attr *attr); 883 884 __rte_internal 885 int 886 mlx5_devx_cmd_query_lag(void *ctx, 887 struct mlx5_devx_lag_context *lag_ctx); 888 889 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 890