1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 struct mlx5_klm *klm_array; 35 int klm_num; 36 }; 37 38 /* HCA qos attributes. */ 39 struct mlx5_hca_qos_attr { 40 uint32_t sup:1; /* Whether QOS is supported. */ 41 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ 42 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 43 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 44 uint32_t flow_meter_reg_share:1; 45 /* Whether reg_c share is supported. */ 46 uint8_t log_max_flow_meter; 47 /* Power of the maximum supported meters. */ 48 uint8_t flow_meter_reg_c_ids; 49 /* Bitmap of the reg_Cs available for flow meter to use. */ 50 51 }; 52 53 struct mlx5_hca_vdpa_attr { 54 uint8_t virtio_queue_type; 55 uint32_t valid:1; 56 uint32_t desc_tunnel_offload_type:1; 57 uint32_t eth_frame_offload_type:1; 58 uint32_t virtio_version_1_0:1; 59 uint32_t tso_ipv4:1; 60 uint32_t tso_ipv6:1; 61 uint32_t tx_csum:1; 62 uint32_t rx_csum:1; 63 uint32_t event_mode:3; 64 uint32_t log_doorbell_stride:5; 65 uint32_t log_doorbell_bar_size:5; 66 uint32_t queue_counters_valid:1; 67 uint32_t max_num_virtio_queues; 68 struct { 69 uint32_t a; 70 uint32_t b; 71 } umems[3]; 72 uint64_t doorbell_bar_offset; 73 }; 74 75 /* HCA supports this number of time periods for LRO. */ 76 #define MLX5_LRO_NUM_SUPP_PERIODS 4 77 78 /* HCA attributes. */ 79 struct mlx5_hca_attr { 80 uint32_t eswitch_manager:1; 81 uint32_t flow_counters_dump:1; 82 uint32_t log_max_rqt_size:5; 83 uint32_t parse_graph_flex_node:1; 84 uint8_t flow_counter_bulk_alloc_bitmap; 85 uint32_t eth_net_offloads:1; 86 uint32_t eth_virt:1; 87 uint32_t wqe_vlan_insert:1; 88 uint32_t wqe_inline_mode:2; 89 uint32_t vport_inline_mode:3; 90 uint32_t tunnel_stateless_geneve_rx:1; 91 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 92 uint32_t tunnel_stateless_gtp:1; 93 uint32_t lro_cap:1; 94 uint32_t tunnel_lro_gre:1; 95 uint32_t tunnel_lro_vxlan:1; 96 uint32_t lro_max_msg_sz_mode:2; 97 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 98 uint16_t lro_min_mss_size; 99 uint32_t flex_parser_protocols; 100 uint32_t hairpin:1; 101 uint32_t log_max_hairpin_queues:5; 102 uint32_t log_max_hairpin_wq_data_sz:5; 103 uint32_t log_max_hairpin_num_packets:5; 104 uint32_t vhca_id:16; 105 uint32_t relaxed_ordering_write:1; 106 uint32_t relaxed_ordering_read:1; 107 uint32_t access_register_user:1; 108 uint32_t wqe_index_ignore:1; 109 uint32_t cross_channel:1; 110 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 111 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 112 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 113 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 114 uint32_t scatter_fcs_w_decap_disable:1; 115 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 116 uint32_t regex:1; 117 uint32_t regexp_num_of_engines; 118 uint32_t log_max_ft_sampler_num:8; 119 struct mlx5_hca_qos_attr qos; 120 struct mlx5_hca_vdpa_attr vdpa; 121 int log_max_qp_sz; 122 int log_max_cq_sz; 123 int log_max_qp; 124 int log_max_cq; 125 uint32_t log_max_pd; 126 uint32_t log_max_mrw_sz; 127 uint32_t log_max_srq; 128 uint32_t log_max_srq_sz; 129 uint32_t rss_ind_tbl_cap; 130 }; 131 132 struct mlx5_devx_wq_attr { 133 uint32_t wq_type:4; 134 uint32_t wq_signature:1; 135 uint32_t end_padding_mode:2; 136 uint32_t cd_slave:1; 137 uint32_t hds_skip_first_sge:1; 138 uint32_t log2_hds_buf_size:3; 139 uint32_t page_offset:5; 140 uint32_t lwm:16; 141 uint32_t pd:24; 142 uint32_t uar_page:24; 143 uint64_t dbr_addr; 144 uint32_t hw_counter; 145 uint32_t sw_counter; 146 uint32_t log_wq_stride:4; 147 uint32_t log_wq_pg_sz:5; 148 uint32_t log_wq_sz:5; 149 uint32_t dbr_umem_valid:1; 150 uint32_t wq_umem_valid:1; 151 uint32_t log_hairpin_num_packets:5; 152 uint32_t log_hairpin_data_sz:5; 153 uint32_t single_wqe_log_num_of_strides:4; 154 uint32_t two_byte_shift_en:1; 155 uint32_t single_stride_log_num_of_bytes:3; 156 uint32_t dbr_umem_id; 157 uint32_t wq_umem_id; 158 uint64_t wq_umem_offset; 159 }; 160 161 /* Create RQ attributes structure, used by create RQ operation. */ 162 struct mlx5_devx_create_rq_attr { 163 uint32_t rlky:1; 164 uint32_t delay_drop_en:1; 165 uint32_t scatter_fcs:1; 166 uint32_t vsd:1; 167 uint32_t mem_rq_type:4; 168 uint32_t state:4; 169 uint32_t flush_in_error_en:1; 170 uint32_t hairpin:1; 171 uint32_t user_index:24; 172 uint32_t cqn:24; 173 uint32_t counter_set_id:8; 174 uint32_t rmpn:24; 175 struct mlx5_devx_wq_attr wq_attr; 176 }; 177 178 /* Modify RQ attributes structure, used by modify RQ operation. */ 179 struct mlx5_devx_modify_rq_attr { 180 uint32_t rqn:24; 181 uint32_t rq_state:4; /* Current RQ state. */ 182 uint32_t state:4; /* Required RQ state. */ 183 uint32_t scatter_fcs:1; 184 uint32_t vsd:1; 185 uint32_t counter_set_id:8; 186 uint32_t hairpin_peer_sq:24; 187 uint32_t hairpin_peer_vhca:16; 188 uint64_t modify_bitmask; 189 uint32_t lwm:16; /* Contained WQ lwm. */ 190 }; 191 192 struct mlx5_rx_hash_field_select { 193 uint32_t l3_prot_type:1; 194 uint32_t l4_prot_type:1; 195 uint32_t selected_fields:30; 196 }; 197 198 /* TIR attributes structure, used by TIR operations. */ 199 struct mlx5_devx_tir_attr { 200 uint32_t disp_type:4; 201 uint32_t lro_timeout_period_usecs:16; 202 uint32_t lro_enable_mask:4; 203 uint32_t lro_max_msg_sz:8; 204 uint32_t inline_rqn:24; 205 uint32_t rx_hash_symmetric:1; 206 uint32_t tunneled_offload_en:1; 207 uint32_t indirect_table:24; 208 uint32_t rx_hash_fn:4; 209 uint32_t self_lb_block:2; 210 uint32_t transport_domain:24; 211 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 212 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 213 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 214 }; 215 216 /* TIR attributes structure, used by TIR modify. */ 217 struct mlx5_devx_modify_tir_attr { 218 uint32_t tirn:24; 219 uint64_t modify_bitmask; 220 struct mlx5_devx_tir_attr tir; 221 }; 222 223 /* RQT attributes structure, used by RQT operations. */ 224 struct mlx5_devx_rqt_attr { 225 uint8_t rq_type; 226 uint32_t rqt_max_size:16; 227 uint32_t rqt_actual_size:16; 228 uint32_t rq_list[]; 229 }; 230 231 /* TIS attributes structure. */ 232 struct mlx5_devx_tis_attr { 233 uint32_t strict_lag_tx_port_affinity:1; 234 uint32_t tls_en:1; 235 uint32_t lag_tx_port_affinity:4; 236 uint32_t prio:4; 237 uint32_t transport_domain:24; 238 }; 239 240 /* SQ attributes structure, used by SQ create operation. */ 241 struct mlx5_devx_create_sq_attr { 242 uint32_t rlky:1; 243 uint32_t cd_master:1; 244 uint32_t fre:1; 245 uint32_t flush_in_error_en:1; 246 uint32_t allow_multi_pkt_send_wqe:1; 247 uint32_t min_wqe_inline_mode:3; 248 uint32_t state:4; 249 uint32_t reg_umr:1; 250 uint32_t allow_swp:1; 251 uint32_t hairpin:1; 252 uint32_t non_wire:1; 253 uint32_t static_sq_wq:1; 254 uint32_t user_index:24; 255 uint32_t cqn:24; 256 uint32_t packet_pacing_rate_limit_index:16; 257 uint32_t tis_lst_sz:16; 258 uint32_t tis_num:24; 259 struct mlx5_devx_wq_attr wq_attr; 260 }; 261 262 /* SQ attributes structure, used by SQ modify operation. */ 263 struct mlx5_devx_modify_sq_attr { 264 uint32_t sq_state:4; 265 uint32_t state:4; 266 uint32_t hairpin_peer_rq:24; 267 uint32_t hairpin_peer_vhca:16; 268 }; 269 270 271 /* CQ attributes structure, used by CQ operations. */ 272 struct mlx5_devx_cq_attr { 273 uint32_t q_umem_valid:1; 274 uint32_t db_umem_valid:1; 275 uint32_t use_first_only:1; 276 uint32_t overrun_ignore:1; 277 uint32_t cqe_comp_en:1; 278 uint32_t mini_cqe_res_format:2; 279 uint32_t mini_cqe_res_format_ext:2; 280 uint32_t cqe_size:3; 281 uint32_t log_cq_size:5; 282 uint32_t log_page_size:5; 283 uint32_t uar_page_id; 284 uint32_t q_umem_id; 285 uint64_t q_umem_offset; 286 uint32_t db_umem_id; 287 uint64_t db_umem_offset; 288 uint32_t eqn; 289 uint64_t db_addr; 290 }; 291 292 /* Virtq attributes structure, used by VIRTQ operations. */ 293 struct mlx5_devx_virtq_attr { 294 uint16_t hw_available_index; 295 uint16_t hw_used_index; 296 uint16_t q_size; 297 uint32_t pd:24; 298 uint32_t virtio_version_1_0:1; 299 uint32_t tso_ipv4:1; 300 uint32_t tso_ipv6:1; 301 uint32_t tx_csum:1; 302 uint32_t rx_csum:1; 303 uint32_t event_mode:3; 304 uint32_t state:4; 305 uint32_t hw_latency_mode:2; 306 uint32_t hw_max_latency_us:12; 307 uint32_t hw_max_pending_comp:16; 308 uint32_t dirty_bitmap_dump_enable:1; 309 uint32_t dirty_bitmap_mkey; 310 uint32_t dirty_bitmap_size; 311 uint32_t mkey; 312 uint32_t qp_id; 313 uint32_t queue_index; 314 uint32_t tis_id; 315 uint32_t counters_obj_id; 316 uint64_t dirty_bitmap_addr; 317 uint64_t type; 318 uint64_t desc_addr; 319 uint64_t used_addr; 320 uint64_t available_addr; 321 struct { 322 uint32_t id; 323 uint32_t size; 324 uint64_t offset; 325 } umems[3]; 326 uint8_t error_type; 327 }; 328 329 330 struct mlx5_devx_qp_attr { 331 uint32_t pd:24; 332 uint32_t uar_index:24; 333 uint32_t cqn:24; 334 uint32_t log_page_size:5; 335 uint32_t rq_size:17; /* Must be power of 2. */ 336 uint32_t log_rq_stride:3; 337 uint32_t sq_size:17; /* Must be power of 2. */ 338 uint32_t dbr_umem_valid:1; 339 uint32_t dbr_umem_id; 340 uint64_t dbr_address; 341 uint32_t wq_umem_id; 342 uint64_t wq_umem_offset; 343 }; 344 345 struct mlx5_devx_virtio_q_couners_attr { 346 uint64_t received_desc; 347 uint64_t completed_desc; 348 uint32_t error_cqes; 349 uint32_t bad_desc_errors; 350 uint32_t exceed_max_chain; 351 uint32_t invalid_buffer; 352 }; 353 354 /* 355 * graph flow match sample attributes structure, 356 * used by flex parser operations. 357 */ 358 struct mlx5_devx_match_sample_attr { 359 uint32_t flow_match_sample_en:1; 360 uint32_t flow_match_sample_field_offset:16; 361 uint32_t flow_match_sample_offset_mode:4; 362 uint32_t flow_match_sample_field_offset_mask; 363 uint32_t flow_match_sample_field_offset_shift:4; 364 uint32_t flow_match_sample_field_base_offset:8; 365 uint32_t flow_match_sample_tunnel_mode:3; 366 uint32_t flow_match_sample_field_id; 367 }; 368 369 /* graph node arc attributes structure, used by flex parser operations. */ 370 struct mlx5_devx_graph_arc_attr { 371 uint32_t compare_condition_value:16; 372 uint32_t start_inner_tunnel:1; 373 uint32_t arc_parse_graph_node:8; 374 uint32_t parse_graph_node_handle; 375 }; 376 377 /* Maximal number of samples per graph node. */ 378 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 379 380 /* Maximal number of input/output arcs per graph node. */ 381 #define MLX5_GRAPH_NODE_ARC_NUM 8 382 383 /* parse graph node attributes structure, used by flex parser operations. */ 384 struct mlx5_devx_graph_node_attr { 385 uint32_t modify_field_select; 386 uint32_t header_length_mode:4; 387 uint32_t header_length_base_value:16; 388 uint32_t header_length_field_shift:4; 389 uint32_t header_length_field_offset:16; 390 uint32_t header_length_field_mask; 391 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 392 uint32_t next_header_field_offset:16; 393 uint32_t next_header_field_size:5; 394 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 395 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 396 }; 397 398 /* mlx5_devx_cmds.c */ 399 400 __rte_internal 401 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 402 uint32_t bulk_sz); 403 __rte_internal 404 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 405 __rte_internal 406 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 407 int clear, uint32_t n_counters, 408 uint64_t *pkts, uint64_t *bytes, 409 uint32_t mkey, void *addr, 410 void *cmd_comp, 411 uint64_t async_id); 412 __rte_internal 413 int mlx5_devx_cmd_query_hca_attr(void *ctx, 414 struct mlx5_hca_attr *attr); 415 __rte_internal 416 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 417 struct mlx5_devx_mkey_attr *attr); 418 __rte_internal 419 int mlx5_devx_get_out_command_status(void *out); 420 __rte_internal 421 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 422 uint32_t *tis_td); 423 __rte_internal 424 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 425 struct mlx5_devx_create_rq_attr *rq_attr, 426 int socket); 427 __rte_internal 428 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 429 struct mlx5_devx_modify_rq_attr *rq_attr); 430 __rte_internal 431 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 432 struct mlx5_devx_tir_attr *tir_attr); 433 __rte_internal 434 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 435 struct mlx5_devx_rqt_attr *rqt_attr); 436 __rte_internal 437 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 438 struct mlx5_devx_create_sq_attr *sq_attr); 439 __rte_internal 440 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 441 struct mlx5_devx_modify_sq_attr *sq_attr); 442 __rte_internal 443 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 444 struct mlx5_devx_tis_attr *tis_attr); 445 __rte_internal 446 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 447 __rte_internal 448 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 449 FILE *file); 450 __rte_internal 451 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 452 struct mlx5_devx_cq_attr *attr); 453 __rte_internal 454 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 455 struct mlx5_devx_virtq_attr *attr); 456 __rte_internal 457 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 458 struct mlx5_devx_virtq_attr *attr); 459 __rte_internal 460 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 461 struct mlx5_devx_virtq_attr *attr); 462 __rte_internal 463 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 464 struct mlx5_devx_qp_attr *attr); 465 __rte_internal 466 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 467 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 468 __rte_internal 469 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 470 struct mlx5_devx_rqt_attr *rqt_attr); 471 __rte_internal 472 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 473 struct mlx5_devx_modify_tir_attr *tir_attr); 474 __rte_internal 475 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 476 uint32_t ids[], uint32_t num); 477 478 __rte_internal 479 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 480 struct mlx5_devx_graph_node_attr *data); 481 482 __rte_internal 483 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 484 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 485 /** 486 * Create virtio queue counters object DevX API. 487 * 488 * @param[in] ctx 489 * Device context. 490 491 * @return 492 * The DevX object created, NULL otherwise and rte_errno is set. 493 */ 494 __rte_internal 495 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 496 497 /** 498 * Query virtio queue counters object using DevX API. 499 * 500 * @param[in] couners_obj 501 * Pointer to virtq object structure. 502 * @param [in/out] attr 503 * Pointer to virtio queue counters attributes structure. 504 * 505 * @return 506 * 0 on success, a negative errno value otherwise and rte_errno is set. 507 */ 508 __rte_internal 509 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 510 struct mlx5_devx_virtio_q_couners_attr *attr); 511 __rte_internal 512 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 513 uint32_t pd); 514 515 __rte_internal 516 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 517 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 518