1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 11 12 /* This is limitation of libibverbs: in length variable type is u16. */ 13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 15 16 struct mlx5_devx_mkey_attr { 17 uint64_t addr; 18 uint64_t size; 19 uint32_t umem_id; 20 uint32_t pd; 21 uint32_t log_entity_size; 22 uint32_t pg_access:1; 23 uint32_t relaxed_ordering:1; 24 struct mlx5_klm *klm_array; 25 int klm_num; 26 }; 27 28 /* HCA qos attributes. */ 29 struct mlx5_hca_qos_attr { 30 uint32_t sup:1; /* Whether QOS is supported. */ 31 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ 32 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 33 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 34 uint32_t flow_meter_reg_share:1; 35 /* Whether reg_c share is supported. */ 36 uint8_t log_max_flow_meter; 37 /* Power of the maximum supported meters. */ 38 uint8_t flow_meter_reg_c_ids; 39 /* Bitmap of the reg_Cs available for flow meter to use. */ 40 41 }; 42 43 struct mlx5_hca_vdpa_attr { 44 uint8_t virtio_queue_type; 45 uint32_t valid:1; 46 uint32_t desc_tunnel_offload_type:1; 47 uint32_t eth_frame_offload_type:1; 48 uint32_t virtio_version_1_0:1; 49 uint32_t tso_ipv4:1; 50 uint32_t tso_ipv6:1; 51 uint32_t tx_csum:1; 52 uint32_t rx_csum:1; 53 uint32_t event_mode:3; 54 uint32_t log_doorbell_stride:5; 55 uint32_t log_doorbell_bar_size:5; 56 uint32_t queue_counters_valid:1; 57 uint32_t max_num_virtio_queues; 58 struct { 59 uint32_t a; 60 uint32_t b; 61 } umems[3]; 62 uint64_t doorbell_bar_offset; 63 }; 64 65 /* HCA supports this number of time periods for LRO. */ 66 #define MLX5_LRO_NUM_SUPP_PERIODS 4 67 68 /* HCA attributes. */ 69 struct mlx5_hca_attr { 70 uint32_t eswitch_manager:1; 71 uint32_t flow_counters_dump:1; 72 uint32_t log_max_rqt_size:5; 73 uint32_t parse_graph_flex_node:1; 74 uint8_t flow_counter_bulk_alloc_bitmap; 75 uint32_t eth_net_offloads:1; 76 uint32_t eth_virt:1; 77 uint32_t wqe_vlan_insert:1; 78 uint32_t wqe_inline_mode:2; 79 uint32_t vport_inline_mode:3; 80 uint32_t tunnel_stateless_geneve_rx:1; 81 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 82 uint32_t tunnel_stateless_gtp:1; 83 uint32_t lro_cap:1; 84 uint32_t tunnel_lro_gre:1; 85 uint32_t tunnel_lro_vxlan:1; 86 uint32_t lro_max_msg_sz_mode:2; 87 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 88 uint32_t flex_parser_protocols; 89 uint32_t hairpin:1; 90 uint32_t log_max_hairpin_queues:5; 91 uint32_t log_max_hairpin_wq_data_sz:5; 92 uint32_t log_max_hairpin_num_packets:5; 93 uint32_t vhca_id:16; 94 uint32_t relaxed_ordering_write:1; 95 uint32_t relaxed_ordering_read:1; 96 uint32_t access_register_user:1; 97 uint32_t wqe_index_ignore:1; 98 uint32_t cross_channel:1; 99 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 100 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 101 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 102 uint32_t scatter_fcs_w_decap_disable:1; 103 uint32_t regex:1; 104 uint32_t regexp_num_of_engines; 105 struct mlx5_hca_qos_attr qos; 106 struct mlx5_hca_vdpa_attr vdpa; 107 }; 108 109 struct mlx5_devx_wq_attr { 110 uint32_t wq_type:4; 111 uint32_t wq_signature:1; 112 uint32_t end_padding_mode:2; 113 uint32_t cd_slave:1; 114 uint32_t hds_skip_first_sge:1; 115 uint32_t log2_hds_buf_size:3; 116 uint32_t page_offset:5; 117 uint32_t lwm:16; 118 uint32_t pd:24; 119 uint32_t uar_page:24; 120 uint64_t dbr_addr; 121 uint32_t hw_counter; 122 uint32_t sw_counter; 123 uint32_t log_wq_stride:4; 124 uint32_t log_wq_pg_sz:5; 125 uint32_t log_wq_sz:5; 126 uint32_t dbr_umem_valid:1; 127 uint32_t wq_umem_valid:1; 128 uint32_t log_hairpin_num_packets:5; 129 uint32_t log_hairpin_data_sz:5; 130 uint32_t single_wqe_log_num_of_strides:4; 131 uint32_t two_byte_shift_en:1; 132 uint32_t single_stride_log_num_of_bytes:3; 133 uint32_t dbr_umem_id; 134 uint32_t wq_umem_id; 135 uint64_t wq_umem_offset; 136 }; 137 138 /* Create RQ attributes structure, used by create RQ operation. */ 139 struct mlx5_devx_create_rq_attr { 140 uint32_t rlky:1; 141 uint32_t delay_drop_en:1; 142 uint32_t scatter_fcs:1; 143 uint32_t vsd:1; 144 uint32_t mem_rq_type:4; 145 uint32_t state:4; 146 uint32_t flush_in_error_en:1; 147 uint32_t hairpin:1; 148 uint32_t user_index:24; 149 uint32_t cqn:24; 150 uint32_t counter_set_id:8; 151 uint32_t rmpn:24; 152 struct mlx5_devx_wq_attr wq_attr; 153 }; 154 155 /* Modify RQ attributes structure, used by modify RQ operation. */ 156 struct mlx5_devx_modify_rq_attr { 157 uint32_t rqn:24; 158 uint32_t rq_state:4; /* Current RQ state. */ 159 uint32_t state:4; /* Required RQ state. */ 160 uint32_t scatter_fcs:1; 161 uint32_t vsd:1; 162 uint32_t counter_set_id:8; 163 uint32_t hairpin_peer_sq:24; 164 uint32_t hairpin_peer_vhca:16; 165 uint64_t modify_bitmask; 166 uint32_t lwm:16; /* Contained WQ lwm. */ 167 }; 168 169 struct mlx5_rx_hash_field_select { 170 uint32_t l3_prot_type:1; 171 uint32_t l4_prot_type:1; 172 uint32_t selected_fields:30; 173 }; 174 175 /* TIR attributes structure, used by TIR operations. */ 176 struct mlx5_devx_tir_attr { 177 uint32_t disp_type:4; 178 uint32_t lro_timeout_period_usecs:16; 179 uint32_t lro_enable_mask:4; 180 uint32_t lro_max_msg_sz:8; 181 uint32_t inline_rqn:24; 182 uint32_t rx_hash_symmetric:1; 183 uint32_t tunneled_offload_en:1; 184 uint32_t indirect_table:24; 185 uint32_t rx_hash_fn:4; 186 uint32_t self_lb_block:2; 187 uint32_t transport_domain:24; 188 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 189 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 190 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 191 }; 192 193 /* RQT attributes structure, used by RQT operations. */ 194 struct mlx5_devx_rqt_attr { 195 uint8_t rq_type; 196 uint32_t rqt_max_size:16; 197 uint32_t rqt_actual_size:16; 198 uint32_t rq_list[]; 199 }; 200 201 /* TIS attributes structure. */ 202 struct mlx5_devx_tis_attr { 203 uint32_t strict_lag_tx_port_affinity:1; 204 uint32_t tls_en:1; 205 uint32_t lag_tx_port_affinity:4; 206 uint32_t prio:4; 207 uint32_t transport_domain:24; 208 }; 209 210 /* SQ attributes structure, used by SQ create operation. */ 211 struct mlx5_devx_create_sq_attr { 212 uint32_t rlky:1; 213 uint32_t cd_master:1; 214 uint32_t fre:1; 215 uint32_t flush_in_error_en:1; 216 uint32_t allow_multi_pkt_send_wqe:1; 217 uint32_t min_wqe_inline_mode:3; 218 uint32_t state:4; 219 uint32_t reg_umr:1; 220 uint32_t allow_swp:1; 221 uint32_t hairpin:1; 222 uint32_t non_wire:1; 223 uint32_t static_sq_wq:1; 224 uint32_t user_index:24; 225 uint32_t cqn:24; 226 uint32_t packet_pacing_rate_limit_index:16; 227 uint32_t tis_lst_sz:16; 228 uint32_t tis_num:24; 229 struct mlx5_devx_wq_attr wq_attr; 230 }; 231 232 /* SQ attributes structure, used by SQ modify operation. */ 233 struct mlx5_devx_modify_sq_attr { 234 uint32_t sq_state:4; 235 uint32_t state:4; 236 uint32_t hairpin_peer_rq:24; 237 uint32_t hairpin_peer_vhca:16; 238 }; 239 240 241 /* CQ attributes structure, used by CQ operations. */ 242 struct mlx5_devx_cq_attr { 243 uint32_t q_umem_valid:1; 244 uint32_t db_umem_valid:1; 245 uint32_t use_first_only:1; 246 uint32_t overrun_ignore:1; 247 uint32_t cqe_comp_en:1; 248 uint32_t mini_cqe_res_format:2; 249 uint32_t cqe_size:3; 250 uint32_t log_cq_size:5; 251 uint32_t log_page_size:5; 252 uint32_t uar_page_id; 253 uint32_t q_umem_id; 254 uint64_t q_umem_offset; 255 uint32_t db_umem_id; 256 uint64_t db_umem_offset; 257 uint32_t eqn; 258 uint64_t db_addr; 259 }; 260 261 /* Virtq attributes structure, used by VIRTQ operations. */ 262 struct mlx5_devx_virtq_attr { 263 uint16_t hw_available_index; 264 uint16_t hw_used_index; 265 uint16_t q_size; 266 uint32_t pd:24; 267 uint32_t virtio_version_1_0:1; 268 uint32_t tso_ipv4:1; 269 uint32_t tso_ipv6:1; 270 uint32_t tx_csum:1; 271 uint32_t rx_csum:1; 272 uint32_t event_mode:3; 273 uint32_t state:4; 274 uint32_t dirty_bitmap_dump_enable:1; 275 uint32_t dirty_bitmap_mkey; 276 uint32_t dirty_bitmap_size; 277 uint32_t mkey; 278 uint32_t qp_id; 279 uint32_t queue_index; 280 uint32_t tis_id; 281 uint32_t counters_obj_id; 282 uint64_t dirty_bitmap_addr; 283 uint64_t type; 284 uint64_t desc_addr; 285 uint64_t used_addr; 286 uint64_t available_addr; 287 struct { 288 uint32_t id; 289 uint32_t size; 290 uint64_t offset; 291 } umems[3]; 292 }; 293 294 295 struct mlx5_devx_qp_attr { 296 uint32_t pd:24; 297 uint32_t uar_index:24; 298 uint32_t cqn:24; 299 uint32_t log_page_size:5; 300 uint32_t rq_size:17; /* Must be power of 2. */ 301 uint32_t log_rq_stride:3; 302 uint32_t sq_size:17; /* Must be power of 2. */ 303 uint32_t dbr_umem_valid:1; 304 uint32_t dbr_umem_id; 305 uint64_t dbr_address; 306 uint32_t wq_umem_id; 307 uint64_t wq_umem_offset; 308 }; 309 310 struct mlx5_devx_virtio_q_couners_attr { 311 uint64_t received_desc; 312 uint64_t completed_desc; 313 uint32_t error_cqes; 314 uint32_t bad_desc_errors; 315 uint32_t exceed_max_chain; 316 uint32_t invalid_buffer; 317 }; 318 319 /* 320 * graph flow match sample attributes structure, 321 * used by flex parser operations. 322 */ 323 struct mlx5_devx_match_sample_attr { 324 uint32_t flow_match_sample_en:1; 325 uint32_t flow_match_sample_field_offset:16; 326 uint32_t flow_match_sample_offset_mode:4; 327 uint32_t flow_match_sample_field_offset_mask; 328 uint32_t flow_match_sample_field_offset_shift:4; 329 uint32_t flow_match_sample_field_base_offset:8; 330 uint32_t flow_match_sample_tunnel_mode:3; 331 uint32_t flow_match_sample_field_id; 332 }; 333 334 /* graph node arc attributes structure, used by flex parser operations. */ 335 struct mlx5_devx_graph_arc_attr { 336 uint32_t compare_condition_value:16; 337 uint32_t start_inner_tunnel:1; 338 uint32_t arc_parse_graph_node:8; 339 uint32_t parse_graph_node_handle; 340 }; 341 342 /* Maximal number of samples per graph node. */ 343 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 344 345 /* Maximal number of input/output arcs per graph node. */ 346 #define MLX5_GRAPH_NODE_ARC_NUM 8 347 348 /* parse graph node attributes structure, used by flex parser operations. */ 349 struct mlx5_devx_graph_node_attr { 350 uint32_t modify_field_select; 351 uint32_t header_length_mode:4; 352 uint32_t header_length_base_value:16; 353 uint32_t header_length_field_shift:4; 354 uint32_t header_length_field_offset:16; 355 uint32_t header_length_field_mask; 356 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 357 uint32_t next_header_field_offset:16; 358 uint32_t next_header_field_size:5; 359 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 360 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 361 }; 362 363 /* mlx5_devx_cmds.c */ 364 365 __rte_internal 366 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 367 uint32_t bulk_sz); 368 __rte_internal 369 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 370 __rte_internal 371 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 372 int clear, uint32_t n_counters, 373 uint64_t *pkts, uint64_t *bytes, 374 uint32_t mkey, void *addr, 375 void *cmd_comp, 376 uint64_t async_id); 377 __rte_internal 378 int mlx5_devx_cmd_query_hca_attr(void *ctx, 379 struct mlx5_hca_attr *attr); 380 __rte_internal 381 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 382 struct mlx5_devx_mkey_attr *attr); 383 __rte_internal 384 int mlx5_devx_get_out_command_status(void *out); 385 __rte_internal 386 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 387 uint32_t *tis_td); 388 __rte_internal 389 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 390 struct mlx5_devx_create_rq_attr *rq_attr, 391 int socket); 392 __rte_internal 393 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 394 struct mlx5_devx_modify_rq_attr *rq_attr); 395 __rte_internal 396 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 397 struct mlx5_devx_tir_attr *tir_attr); 398 __rte_internal 399 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 400 struct mlx5_devx_rqt_attr *rqt_attr); 401 __rte_internal 402 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 403 struct mlx5_devx_create_sq_attr *sq_attr); 404 __rte_internal 405 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 406 struct mlx5_devx_modify_sq_attr *sq_attr); 407 __rte_internal 408 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 409 struct mlx5_devx_tis_attr *tis_attr); 410 __rte_internal 411 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 412 __rte_internal 413 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 414 FILE *file); 415 __rte_internal 416 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 417 struct mlx5_devx_cq_attr *attr); 418 __rte_internal 419 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 420 struct mlx5_devx_virtq_attr *attr); 421 __rte_internal 422 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 423 struct mlx5_devx_virtq_attr *attr); 424 __rte_internal 425 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 426 struct mlx5_devx_virtq_attr *attr); 427 __rte_internal 428 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 429 struct mlx5_devx_qp_attr *attr); 430 __rte_internal 431 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 432 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 433 __rte_internal 434 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 435 struct mlx5_devx_rqt_attr *rqt_attr); 436 __rte_internal 437 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 438 uint32_t ids[], uint32_t num); 439 440 __rte_internal 441 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 442 struct mlx5_devx_graph_node_attr *data); 443 444 __rte_internal 445 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 446 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 447 /** 448 * Create virtio queue counters object DevX API. 449 * 450 * @param[in] ctx 451 * Device context. 452 453 * @return 454 * The DevX object created, NULL otherwise and rte_errno is set. 455 */ 456 __rte_internal 457 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 458 459 /** 460 * Query virtio queue counters object using DevX API. 461 * 462 * @param[in] couners_obj 463 * Pointer to virtq object structure. 464 * @param [in/out] attr 465 * Pointer to virtio queue counters attributes structure. 466 * 467 * @return 468 * 0 on success, a negative errno value otherwise and rte_errno is set. 469 */ 470 __rte_internal 471 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 472 struct mlx5_devx_virtio_q_couners_attr *attr); 473 474 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 475