1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include <rte_compat.h> 9 #include <rte_bitops.h> 10 11 #include "mlx5_glue.h" 12 #include "mlx5_prm.h" 13 14 /* This is limitation of libibverbs: in length variable type is u16. */ 15 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 16 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 17 18 struct mlx5_devx_mkey_attr { 19 uint64_t addr; 20 uint64_t size; 21 uint32_t umem_id; 22 uint32_t pd; 23 uint32_t log_entity_size; 24 uint32_t pg_access:1; 25 uint32_t relaxed_ordering_write:1; 26 uint32_t relaxed_ordering_read:1; 27 uint32_t umr_en:1; 28 uint32_t crypto_en:2; 29 uint32_t set_remote_rw:1; 30 struct mlx5_klm *klm_array; 31 int klm_num; 32 }; 33 34 /* HCA qos attributes. */ 35 struct mlx5_hca_qos_attr { 36 uint32_t sup:1; /* Whether QOS is supported. */ 37 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */ 38 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 39 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 40 uint32_t flow_meter:1; 41 /* 42 * Flow meter is supported, updated version. 43 * When flow_meter is 1, it indicates that REG_C sharing is supported. 44 * If flow_meter is 1, flow_meter_old is also 1. 45 * Using older driver versions, flow_meter_old can be 1 46 * while flow_meter is 0. 47 */ 48 uint32_t flow_meter_aso_sup:1; 49 /* Whether FLOW_METER_ASO Object is supported. */ 50 uint8_t log_max_flow_meter; 51 /* Power of the maximum supported meters. */ 52 uint8_t flow_meter_reg_c_ids; 53 /* Bitmap of the reg_Cs available for flow meter to use. */ 54 uint32_t log_meter_aso_granularity:5; 55 /* Power of the minimum allocation granularity Object. */ 56 uint32_t log_meter_aso_max_alloc:5; 57 /* Power of the maximum allocation granularity Object. */ 58 uint32_t log_max_num_meter_aso:5; 59 /* Power of the maximum number of supported objects. */ 60 61 }; 62 63 struct mlx5_hca_vdpa_attr { 64 uint8_t virtio_queue_type; 65 uint32_t valid:1; 66 uint32_t desc_tunnel_offload_type:1; 67 uint32_t eth_frame_offload_type:1; 68 uint32_t virtio_version_1_0:1; 69 uint32_t tso_ipv4:1; 70 uint32_t tso_ipv6:1; 71 uint32_t tx_csum:1; 72 uint32_t rx_csum:1; 73 uint32_t event_mode:3; 74 uint32_t log_doorbell_stride:5; 75 uint32_t log_doorbell_bar_size:5; 76 uint32_t queue_counters_valid:1; 77 uint32_t max_num_virtio_queues; 78 struct { 79 uint32_t a; 80 uint32_t b; 81 } umems[3]; 82 uint64_t doorbell_bar_offset; 83 }; 84 85 struct mlx5_hca_flow_attr { 86 uint32_t tunnel_header_0_1; 87 uint32_t tunnel_header_2_3; 88 }; 89 90 /** 91 * Accumulate port PARSE_GRAPH_NODE capabilities from 92 * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables 93 */ 94 __extension__ 95 struct mlx5_hca_flex_attr { 96 uint32_t node_in; 97 uint32_t node_out; 98 uint16_t header_length_mode; 99 uint16_t sample_offset_mode; 100 uint8_t max_num_arc_in; 101 uint8_t max_num_arc_out; 102 uint8_t max_num_sample; 103 uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ 104 uint8_t sample_id_in_out:1; 105 uint16_t max_base_header_length; 106 uint8_t max_sample_base_offset; 107 uint16_t max_next_header_offset; 108 uint8_t header_length_mask_width; 109 }; 110 111 /* ISO C restricts enumerator values to range of 'int' */ 112 __extension__ 113 enum { 114 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1), 115 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2), 116 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3), 117 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4), 118 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5), 119 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6), 120 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7), 121 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8), 122 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9), 123 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10), 124 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11), 125 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12), 126 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31) 127 }; 128 129 enum { 130 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0), 131 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1), 132 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2) 133 }; 134 135 /* 136 * DWORD shift is the base for calculating header_length_field_mask 137 * value in the MLX5_GRAPH_NODE_LEN_FIELD mode. 138 */ 139 #define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02 140 141 static inline uint32_t 142 mlx5_hca_parse_graph_node_base_hdr_len_mask 143 (const struct mlx5_hca_flex_attr *attr) 144 { 145 return (1 << attr->header_length_mask_width) - 1; 146 } 147 148 /* HCA supports this number of time periods for LRO. */ 149 #define MLX5_LRO_NUM_SUPP_PERIODS 4 150 151 /* HCA attributes. */ 152 struct mlx5_hca_attr { 153 uint32_t eswitch_manager:1; 154 uint32_t flow_counters_dump:1; 155 uint32_t mem_rq_rmp:1; 156 uint32_t log_max_rmp:5; 157 uint32_t log_max_rqt_size:5; 158 uint32_t parse_graph_flex_node:1; 159 uint8_t flow_counter_bulk_alloc_bitmap; 160 uint32_t eth_net_offloads:1; 161 uint32_t eth_virt:1; 162 uint32_t wqe_vlan_insert:1; 163 uint32_t csum_cap:1; 164 uint32_t vlan_cap:1; 165 uint32_t wqe_inline_mode:2; 166 uint32_t vport_inline_mode:3; 167 uint32_t tunnel_stateless_geneve_rx:1; 168 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 169 uint32_t tunnel_stateless_gtp:1; 170 uint32_t max_lso_cap; 171 uint32_t scatter_fcs:1; 172 uint32_t lro_cap:1; 173 uint32_t tunnel_lro_gre:1; 174 uint32_t tunnel_lro_vxlan:1; 175 uint32_t tunnel_stateless_gre:1; 176 uint32_t tunnel_stateless_vxlan:1; 177 uint32_t swp:1; 178 uint32_t swp_csum:1; 179 uint32_t swp_lso:1; 180 uint32_t lro_max_msg_sz_mode:2; 181 uint32_t rq_delay_drop:1; 182 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 183 uint16_t lro_min_mss_size; 184 uint32_t flex_parser_protocols; 185 uint32_t max_geneve_tlv_options; 186 uint32_t max_geneve_tlv_option_data_len; 187 uint32_t hairpin:1; 188 uint32_t log_max_hairpin_queues:5; 189 uint32_t log_max_hairpin_wq_data_sz:5; 190 uint32_t log_max_hairpin_num_packets:5; 191 uint32_t vhca_id:16; 192 uint32_t relaxed_ordering_write:1; 193 uint32_t relaxed_ordering_read:1; 194 uint32_t access_register_user:1; 195 uint32_t wqe_index_ignore:1; 196 uint32_t cross_channel:1; 197 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 198 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 199 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 200 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 201 uint32_t scatter_fcs_w_decap_disable:1; 202 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 203 uint32_t roce:1; 204 uint32_t rq_ts_format:2; 205 uint32_t sq_ts_format:2; 206 uint32_t steering_format_version:4; 207 uint32_t qp_ts_format:2; 208 uint32_t regexp_params:1; 209 uint32_t regexp_version:3; 210 uint32_t reg_c_preserve:1; 211 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ 212 uint32_t crypto:1; /* Crypto engine is supported. */ 213 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ 214 uint32_t dek:1; /* General obj type DEK is supported. */ 215 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */ 216 uint32_t credential:1; /* General obj type CREDENTIAL supported. */ 217 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ 218 uint32_t regexp_num_of_engines; 219 uint32_t log_max_ft_sampler_num:8; 220 uint32_t inner_ipv4_ihl:1; 221 uint32_t outer_ipv4_ihl:1; 222 uint32_t geneve_tlv_opt; 223 uint32_t cqe_compression:1; 224 uint32_t mini_cqe_resp_flow_tag:1; 225 uint32_t mini_cqe_resp_l3_l4_tag:1; 226 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ 227 struct mlx5_hca_qos_attr qos; 228 struct mlx5_hca_vdpa_attr vdpa; 229 struct mlx5_hca_flow_attr flow; 230 struct mlx5_hca_flex_attr flex; 231 int log_max_qp_sz; 232 int log_max_cq_sz; 233 int log_max_qp; 234 int log_max_cq; 235 uint32_t log_max_pd; 236 uint32_t log_max_mrw_sz; 237 uint32_t log_max_srq; 238 uint32_t log_max_srq_sz; 239 uint32_t rss_ind_tbl_cap; 240 uint32_t mmo_dma_sq_en:1; 241 uint32_t mmo_compress_sq_en:1; 242 uint32_t mmo_decompress_sq_en:1; 243 uint32_t mmo_dma_qp_en:1; 244 uint32_t mmo_compress_qp_en:1; 245 uint32_t mmo_decompress_qp_en:1; 246 uint32_t mmo_regex_qp_en:1; 247 uint32_t mmo_regex_sq_en:1; 248 uint32_t compress_min_block_size:4; 249 uint32_t log_max_mmo_dma:5; 250 uint32_t log_max_mmo_compress:5; 251 uint32_t log_max_mmo_decompress:5; 252 uint32_t umr_modify_entity_size_disabled:1; 253 uint32_t umr_indirect_mkey_disabled:1; 254 uint32_t log_min_stride_wqe_sz:5; 255 uint16_t max_wqe_sz_sq; 256 }; 257 258 /* LAG Context. */ 259 struct mlx5_devx_lag_context { 260 uint32_t fdb_selection_mode:1; 261 uint32_t port_select_mode:3; 262 uint32_t lag_state:3; 263 uint32_t tx_remap_affinity_1:4; 264 uint32_t tx_remap_affinity_2:4; 265 }; 266 267 struct mlx5_devx_wq_attr { 268 uint32_t wq_type:4; 269 uint32_t wq_signature:1; 270 uint32_t end_padding_mode:2; 271 uint32_t cd_slave:1; 272 uint32_t hds_skip_first_sge:1; 273 uint32_t log2_hds_buf_size:3; 274 uint32_t page_offset:5; 275 uint32_t lwm:16; 276 uint32_t pd:24; 277 uint32_t uar_page:24; 278 uint64_t dbr_addr; 279 uint32_t hw_counter; 280 uint32_t sw_counter; 281 uint32_t log_wq_stride:4; 282 uint32_t log_wq_pg_sz:5; 283 uint32_t log_wq_sz:5; 284 uint32_t dbr_umem_valid:1; 285 uint32_t wq_umem_valid:1; 286 uint32_t log_hairpin_num_packets:5; 287 uint32_t log_hairpin_data_sz:5; 288 uint32_t single_wqe_log_num_of_strides:4; 289 uint32_t two_byte_shift_en:1; 290 uint32_t single_stride_log_num_of_bytes:3; 291 uint32_t dbr_umem_id; 292 uint32_t wq_umem_id; 293 uint64_t wq_umem_offset; 294 }; 295 296 /* Create RQ attributes structure, used by create RQ operation. */ 297 struct mlx5_devx_create_rq_attr { 298 uint32_t rlky:1; 299 uint32_t delay_drop_en:1; 300 uint32_t scatter_fcs:1; 301 uint32_t vsd:1; 302 uint32_t mem_rq_type:4; 303 uint32_t state:4; 304 uint32_t flush_in_error_en:1; 305 uint32_t hairpin:1; 306 uint32_t ts_format:2; 307 uint32_t user_index:24; 308 uint32_t cqn:24; 309 uint32_t counter_set_id:8; 310 uint32_t rmpn:24; 311 struct mlx5_devx_wq_attr wq_attr; 312 }; 313 314 /* Modify RQ attributes structure, used by modify RQ operation. */ 315 struct mlx5_devx_modify_rq_attr { 316 uint32_t rqn:24; 317 uint32_t rq_state:4; /* Current RQ state. */ 318 uint32_t state:4; /* Required RQ state. */ 319 uint32_t scatter_fcs:1; 320 uint32_t vsd:1; 321 uint32_t counter_set_id:8; 322 uint32_t hairpin_peer_sq:24; 323 uint32_t hairpin_peer_vhca:16; 324 uint64_t modify_bitmask; 325 uint32_t lwm:16; /* Contained WQ lwm. */ 326 }; 327 328 /* Create RMP attributes structure, used by create RMP operation. */ 329 struct mlx5_devx_create_rmp_attr { 330 uint32_t rsvd0:8; 331 uint32_t state:4; 332 uint32_t rsvd1:20; 333 uint32_t basic_cyclic_rcv_wqe:1; 334 uint32_t rsvd4:31; 335 uint32_t rsvd8[10]; 336 struct mlx5_devx_wq_attr wq_attr; 337 }; 338 339 struct mlx5_rx_hash_field_select { 340 uint32_t l3_prot_type:1; 341 uint32_t l4_prot_type:1; 342 uint32_t selected_fields:30; 343 }; 344 345 /* TIR attributes structure, used by TIR operations. */ 346 struct mlx5_devx_tir_attr { 347 uint32_t disp_type:4; 348 uint32_t lro_timeout_period_usecs:16; 349 uint32_t lro_enable_mask:4; 350 uint32_t lro_max_msg_sz:8; 351 uint32_t inline_rqn:24; 352 uint32_t rx_hash_symmetric:1; 353 uint32_t tunneled_offload_en:1; 354 uint32_t indirect_table:24; 355 uint32_t rx_hash_fn:4; 356 uint32_t self_lb_block:2; 357 uint32_t transport_domain:24; 358 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 359 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 360 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 361 }; 362 363 /* TIR attributes structure, used by TIR modify. */ 364 struct mlx5_devx_modify_tir_attr { 365 uint32_t tirn:24; 366 uint64_t modify_bitmask; 367 struct mlx5_devx_tir_attr tir; 368 }; 369 370 /* RQT attributes structure, used by RQT operations. */ 371 struct mlx5_devx_rqt_attr { 372 uint8_t rq_type; 373 uint32_t rqt_max_size:16; 374 uint32_t rqt_actual_size:16; 375 uint32_t rq_list[]; 376 }; 377 378 /* TIS attributes structure. */ 379 struct mlx5_devx_tis_attr { 380 uint32_t strict_lag_tx_port_affinity:1; 381 uint32_t tls_en:1; 382 uint32_t lag_tx_port_affinity:4; 383 uint32_t prio:4; 384 uint32_t transport_domain:24; 385 }; 386 387 /* SQ attributes structure, used by SQ create operation. */ 388 struct mlx5_devx_create_sq_attr { 389 uint32_t rlky:1; 390 uint32_t cd_master:1; 391 uint32_t fre:1; 392 uint32_t flush_in_error_en:1; 393 uint32_t allow_multi_pkt_send_wqe:1; 394 uint32_t min_wqe_inline_mode:3; 395 uint32_t state:4; 396 uint32_t reg_umr:1; 397 uint32_t allow_swp:1; 398 uint32_t hairpin:1; 399 uint32_t non_wire:1; 400 uint32_t static_sq_wq:1; 401 uint32_t ts_format:2; 402 uint32_t user_index:24; 403 uint32_t cqn:24; 404 uint32_t packet_pacing_rate_limit_index:16; 405 uint32_t tis_lst_sz:16; 406 uint32_t tis_num:24; 407 struct mlx5_devx_wq_attr wq_attr; 408 }; 409 410 /* SQ attributes structure, used by SQ modify operation. */ 411 struct mlx5_devx_modify_sq_attr { 412 uint32_t sq_state:4; 413 uint32_t state:4; 414 uint32_t hairpin_peer_rq:24; 415 uint32_t hairpin_peer_vhca:16; 416 }; 417 418 419 /* CQ attributes structure, used by CQ operations. */ 420 struct mlx5_devx_cq_attr { 421 uint32_t q_umem_valid:1; 422 uint32_t db_umem_valid:1; 423 uint32_t use_first_only:1; 424 uint32_t overrun_ignore:1; 425 uint32_t cqe_comp_en:1; 426 uint32_t mini_cqe_res_format:2; 427 uint32_t mini_cqe_res_format_ext:2; 428 uint32_t log_cq_size:5; 429 uint32_t log_page_size:5; 430 uint32_t uar_page_id; 431 uint32_t q_umem_id; 432 uint64_t q_umem_offset; 433 uint32_t db_umem_id; 434 uint64_t db_umem_offset; 435 uint32_t eqn; 436 uint64_t db_addr; 437 }; 438 439 /* Virtq attributes structure, used by VIRTQ operations. */ 440 struct mlx5_devx_virtq_attr { 441 uint16_t hw_available_index; 442 uint16_t hw_used_index; 443 uint16_t q_size; 444 uint32_t pd:24; 445 uint32_t virtio_version_1_0:1; 446 uint32_t tso_ipv4:1; 447 uint32_t tso_ipv6:1; 448 uint32_t tx_csum:1; 449 uint32_t rx_csum:1; 450 uint32_t event_mode:3; 451 uint32_t state:4; 452 uint32_t hw_latency_mode:2; 453 uint32_t hw_max_latency_us:12; 454 uint32_t hw_max_pending_comp:16; 455 uint32_t dirty_bitmap_dump_enable:1; 456 uint32_t dirty_bitmap_mkey; 457 uint32_t dirty_bitmap_size; 458 uint32_t mkey; 459 uint32_t qp_id; 460 uint32_t queue_index; 461 uint32_t tis_id; 462 uint32_t counters_obj_id; 463 uint64_t dirty_bitmap_addr; 464 uint64_t type; 465 uint64_t desc_addr; 466 uint64_t used_addr; 467 uint64_t available_addr; 468 struct { 469 uint32_t id; 470 uint32_t size; 471 uint64_t offset; 472 } umems[3]; 473 uint8_t error_type; 474 }; 475 476 477 struct mlx5_devx_qp_attr { 478 uint32_t pd:24; 479 uint32_t uar_index:24; 480 uint32_t cqn:24; 481 uint32_t log_page_size:5; 482 uint32_t num_of_receive_wqes:17; /* Must be power of 2. */ 483 uint32_t log_rq_stride:3; 484 uint32_t num_of_send_wqbbs:17; /* Must be power of 2. */ 485 uint32_t ts_format:2; 486 uint32_t dbr_umem_valid:1; 487 uint32_t dbr_umem_id; 488 uint64_t dbr_address; 489 uint32_t wq_umem_id; 490 uint64_t wq_umem_offset; 491 uint32_t user_index:24; 492 uint32_t mmo:1; 493 }; 494 495 struct mlx5_devx_virtio_q_couners_attr { 496 uint64_t received_desc; 497 uint64_t completed_desc; 498 uint32_t error_cqes; 499 uint32_t bad_desc_errors; 500 uint32_t exceed_max_chain; 501 uint32_t invalid_buffer; 502 }; 503 504 /* 505 * graph flow match sample attributes structure, 506 * used by flex parser operations. 507 */ 508 struct mlx5_devx_match_sample_attr { 509 uint32_t flow_match_sample_en:1; 510 uint32_t flow_match_sample_field_offset:16; 511 uint32_t flow_match_sample_offset_mode:4; 512 uint32_t flow_match_sample_field_offset_mask; 513 uint32_t flow_match_sample_field_offset_shift:4; 514 uint32_t flow_match_sample_field_base_offset:8; 515 uint32_t flow_match_sample_tunnel_mode:3; 516 uint32_t flow_match_sample_field_id; 517 }; 518 519 /* graph node arc attributes structure, used by flex parser operations. */ 520 struct mlx5_devx_graph_arc_attr { 521 uint32_t compare_condition_value:16; 522 uint32_t start_inner_tunnel:1; 523 uint32_t arc_parse_graph_node:8; 524 uint32_t parse_graph_node_handle; 525 }; 526 527 /* Maximal number of samples per graph node. */ 528 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 529 530 /* Maximal number of input/output arcs per graph node. */ 531 #define MLX5_GRAPH_NODE_ARC_NUM 8 532 533 /* parse graph node attributes structure, used by flex parser operations. */ 534 struct mlx5_devx_graph_node_attr { 535 uint32_t modify_field_select; 536 uint32_t header_length_mode:4; 537 uint32_t header_length_base_value:16; 538 uint32_t header_length_field_shift:4; 539 uint32_t header_length_field_offset:16; 540 uint32_t header_length_field_mask; 541 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 542 uint32_t next_header_field_offset:16; 543 uint32_t next_header_field_size:5; 544 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 545 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 546 }; 547 548 /* Encryption key size is up to 1024 bit, 128 bytes. */ 549 #define MLX5_CRYPTO_KEY_MAX_SIZE 128 550 551 struct mlx5_devx_dek_attr { 552 uint32_t key_size:4; 553 uint32_t has_keytag:1; 554 uint32_t key_purpose:4; 555 uint32_t pd:24; 556 uint64_t opaque; 557 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 558 }; 559 560 struct mlx5_devx_import_kek_attr { 561 uint64_t modify_field_select; 562 uint32_t state:8; 563 uint32_t key_size:4; 564 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE]; 565 }; 566 567 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48 568 569 struct mlx5_devx_credential_attr { 570 uint64_t modify_field_select; 571 uint32_t state:8; 572 uint32_t credential_role:8; 573 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 574 }; 575 576 struct mlx5_devx_crypto_login_attr { 577 uint64_t modify_field_select; 578 uint32_t credential_pointer:24; 579 uint32_t session_import_kek_ptr:24; 580 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE]; 581 }; 582 583 /* mlx5_devx_cmds.c */ 584 585 __rte_internal 586 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 587 uint32_t bulk_sz); 588 __rte_internal 589 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 590 __rte_internal 591 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 592 int clear, uint32_t n_counters, 593 uint64_t *pkts, uint64_t *bytes, 594 uint32_t mkey, void *addr, 595 void *cmd_comp, 596 uint64_t async_id); 597 __rte_internal 598 int mlx5_devx_cmd_query_hca_attr(void *ctx, 599 struct mlx5_hca_attr *attr); 600 __rte_internal 601 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 602 struct mlx5_devx_mkey_attr *attr); 603 __rte_internal 604 int mlx5_devx_get_out_command_status(void *out); 605 __rte_internal 606 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 607 uint32_t *tis_td); 608 __rte_internal 609 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 610 struct mlx5_devx_create_rq_attr *rq_attr, 611 int socket); 612 __rte_internal 613 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 614 struct mlx5_devx_modify_rq_attr *rq_attr); 615 __rte_internal 616 struct mlx5_devx_obj *mlx5_devx_cmd_create_rmp(void *ctx, 617 struct mlx5_devx_create_rmp_attr *rq_attr, int socket); 618 __rte_internal 619 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 620 struct mlx5_devx_tir_attr *tir_attr); 621 __rte_internal 622 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 623 struct mlx5_devx_rqt_attr *rqt_attr); 624 __rte_internal 625 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 626 struct mlx5_devx_create_sq_attr *sq_attr); 627 __rte_internal 628 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 629 struct mlx5_devx_modify_sq_attr *sq_attr); 630 __rte_internal 631 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 632 struct mlx5_devx_tis_attr *tis_attr); 633 __rte_internal 634 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 635 __rte_internal 636 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 637 FILE *file); 638 __rte_internal 639 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file); 640 __rte_internal 641 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 642 struct mlx5_devx_cq_attr *attr); 643 __rte_internal 644 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 645 struct mlx5_devx_virtq_attr *attr); 646 __rte_internal 647 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 648 struct mlx5_devx_virtq_attr *attr); 649 __rte_internal 650 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 651 struct mlx5_devx_virtq_attr *attr); 652 __rte_internal 653 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 654 struct mlx5_devx_qp_attr *attr); 655 __rte_internal 656 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 657 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 658 __rte_internal 659 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 660 struct mlx5_devx_rqt_attr *rqt_attr); 661 __rte_internal 662 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 663 struct mlx5_devx_modify_tir_attr *tir_attr); 664 __rte_internal 665 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 666 uint32_t ids[], uint32_t num); 667 668 __rte_internal 669 struct mlx5_devx_obj * 670 mlx5_devx_cmd_create_flex_parser(void *ctx, 671 struct mlx5_devx_graph_node_attr *data); 672 673 __rte_internal 674 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 675 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 676 677 __rte_internal 678 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, 679 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 680 681 __rte_internal 682 struct mlx5_devx_obj * 683 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 684 uint16_t class, uint8_t type, uint8_t len); 685 686 /** 687 * Create virtio queue counters object DevX API. 688 * 689 * @param[in] ctx 690 * Device context. 691 692 * @return 693 * The DevX object created, NULL otherwise and rte_errno is set. 694 */ 695 __rte_internal 696 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 697 698 /** 699 * Query virtio queue counters object using DevX API. 700 * 701 * @param[in] couners_obj 702 * Pointer to virtq object structure. 703 * @param [in/out] attr 704 * Pointer to virtio queue counters attributes structure. 705 * 706 * @return 707 * 0 on success, a negative errno value otherwise and rte_errno is set. 708 */ 709 __rte_internal 710 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 711 struct mlx5_devx_virtio_q_couners_attr *attr); 712 __rte_internal 713 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 714 uint32_t pd); 715 __rte_internal 716 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 717 718 __rte_internal 719 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id); 720 721 __rte_internal 722 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); 723 __rte_internal 724 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 725 uint32_t *out_of_buffers); 726 __rte_internal 727 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, 728 uint32_t pd, uint32_t log_obj_size); 729 730 /** 731 * Create general object of type FLOW_METER_ASO using DevX API.. 732 * 733 * @param[in] ctx 734 * Device context. 735 * @param [in] pd 736 * PD value to associate the FLOW_METER_ASO object with. 737 * @param [in] log_obj_size 738 * log_obj_size define to allocate number of 2 * meters 739 * in one FLOW_METER_ASO object. 740 * 741 * @return 742 * The DevX object created, NULL otherwise and rte_errno is set. 743 */ 744 __rte_internal 745 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, 746 uint32_t pd, uint32_t log_obj_size); 747 __rte_internal 748 struct mlx5_devx_obj * 749 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr); 750 751 __rte_internal 752 struct mlx5_devx_obj * 753 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 754 struct mlx5_devx_import_kek_attr *attr); 755 756 __rte_internal 757 struct mlx5_devx_obj * 758 mlx5_devx_cmd_create_credential_obj(void *ctx, 759 struct mlx5_devx_credential_attr *attr); 760 761 __rte_internal 762 struct mlx5_devx_obj * 763 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 764 struct mlx5_devx_crypto_login_attr *attr); 765 766 __rte_internal 767 int 768 mlx5_devx_cmd_query_lag(void *ctx, 769 struct mlx5_devx_lag_context *lag_ctx); 770 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 771