1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ 6 #define RTE_PMD_MLX5_DEVX_CMDS_H_ 7 8 #include "mlx5_glue.h" 9 #include "mlx5_prm.h" 10 #include <rte_compat.h> 11 12 /* 13 * Defines the amount of retries to allocate the first UAR in the page. 14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 15 * UAR base address if UAR was not the first object in the UAR page. 16 * It caused the PMD failure and we should try to get another UAR 17 * till we get the first one with non-NULL base address returned. 18 */ 19 #define MLX5_ALLOC_UAR_RETRY 32 20 21 /* This is limitation of libibverbs: in length variable type is u16. */ 22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ 23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4)) 24 25 struct mlx5_devx_mkey_attr { 26 uint64_t addr; 27 uint64_t size; 28 uint32_t umem_id; 29 uint32_t pd; 30 uint32_t log_entity_size; 31 uint32_t pg_access:1; 32 uint32_t relaxed_ordering_write:1; 33 uint32_t relaxed_ordering_read:1; 34 struct mlx5_klm *klm_array; 35 int klm_num; 36 }; 37 38 /* HCA qos attributes. */ 39 struct mlx5_hca_qos_attr { 40 uint32_t sup:1; /* Whether QOS is supported. */ 41 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */ 42 uint32_t packet_pacing:1; /* Packet pacing is supported. */ 43 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */ 44 uint32_t flow_meter_reg_share:1; 45 /* Whether reg_c share is supported. */ 46 uint8_t log_max_flow_meter; 47 /* Power of the maximum supported meters. */ 48 uint8_t flow_meter_reg_c_ids; 49 /* Bitmap of the reg_Cs available for flow meter to use. */ 50 51 }; 52 53 struct mlx5_hca_vdpa_attr { 54 uint8_t virtio_queue_type; 55 uint32_t valid:1; 56 uint32_t desc_tunnel_offload_type:1; 57 uint32_t eth_frame_offload_type:1; 58 uint32_t virtio_version_1_0:1; 59 uint32_t tso_ipv4:1; 60 uint32_t tso_ipv6:1; 61 uint32_t tx_csum:1; 62 uint32_t rx_csum:1; 63 uint32_t event_mode:3; 64 uint32_t log_doorbell_stride:5; 65 uint32_t log_doorbell_bar_size:5; 66 uint32_t queue_counters_valid:1; 67 uint32_t max_num_virtio_queues; 68 struct { 69 uint32_t a; 70 uint32_t b; 71 } umems[3]; 72 uint64_t doorbell_bar_offset; 73 }; 74 75 /* HCA supports this number of time periods for LRO. */ 76 #define MLX5_LRO_NUM_SUPP_PERIODS 4 77 78 /* HCA attributes. */ 79 struct mlx5_hca_attr { 80 uint32_t eswitch_manager:1; 81 uint32_t flow_counters_dump:1; 82 uint32_t log_max_rqt_size:5; 83 uint32_t parse_graph_flex_node:1; 84 uint8_t flow_counter_bulk_alloc_bitmap; 85 uint32_t eth_net_offloads:1; 86 uint32_t eth_virt:1; 87 uint32_t wqe_vlan_insert:1; 88 uint32_t wqe_inline_mode:2; 89 uint32_t vport_inline_mode:3; 90 uint32_t tunnel_stateless_geneve_rx:1; 91 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ 92 uint32_t tunnel_stateless_gtp:1; 93 uint32_t lro_cap:1; 94 uint32_t tunnel_lro_gre:1; 95 uint32_t tunnel_lro_vxlan:1; 96 uint32_t lro_max_msg_sz_mode:2; 97 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; 98 uint16_t lro_min_mss_size; 99 uint32_t flex_parser_protocols; 100 uint32_t max_geneve_tlv_options; 101 uint32_t max_geneve_tlv_option_data_len; 102 uint32_t hairpin:1; 103 uint32_t log_max_hairpin_queues:5; 104 uint32_t log_max_hairpin_wq_data_sz:5; 105 uint32_t log_max_hairpin_num_packets:5; 106 uint32_t vhca_id:16; 107 uint32_t relaxed_ordering_write:1; 108 uint32_t relaxed_ordering_read:1; 109 uint32_t access_register_user:1; 110 uint32_t wqe_index_ignore:1; 111 uint32_t cross_channel:1; 112 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */ 113 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */ 114 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 115 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */ 116 uint32_t scatter_fcs_w_decap_disable:1; 117 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */ 118 uint32_t regex:1; 119 uint32_t regexp_num_of_engines; 120 uint32_t log_max_ft_sampler_num:8; 121 uint32_t geneve_tlv_opt; 122 struct mlx5_hca_qos_attr qos; 123 struct mlx5_hca_vdpa_attr vdpa; 124 int log_max_qp_sz; 125 int log_max_cq_sz; 126 int log_max_qp; 127 int log_max_cq; 128 uint32_t log_max_pd; 129 uint32_t log_max_mrw_sz; 130 uint32_t log_max_srq; 131 uint32_t log_max_srq_sz; 132 uint32_t rss_ind_tbl_cap; 133 }; 134 135 struct mlx5_devx_wq_attr { 136 uint32_t wq_type:4; 137 uint32_t wq_signature:1; 138 uint32_t end_padding_mode:2; 139 uint32_t cd_slave:1; 140 uint32_t hds_skip_first_sge:1; 141 uint32_t log2_hds_buf_size:3; 142 uint32_t page_offset:5; 143 uint32_t lwm:16; 144 uint32_t pd:24; 145 uint32_t uar_page:24; 146 uint64_t dbr_addr; 147 uint32_t hw_counter; 148 uint32_t sw_counter; 149 uint32_t log_wq_stride:4; 150 uint32_t log_wq_pg_sz:5; 151 uint32_t log_wq_sz:5; 152 uint32_t dbr_umem_valid:1; 153 uint32_t wq_umem_valid:1; 154 uint32_t log_hairpin_num_packets:5; 155 uint32_t log_hairpin_data_sz:5; 156 uint32_t single_wqe_log_num_of_strides:4; 157 uint32_t two_byte_shift_en:1; 158 uint32_t single_stride_log_num_of_bytes:3; 159 uint32_t dbr_umem_id; 160 uint32_t wq_umem_id; 161 uint64_t wq_umem_offset; 162 }; 163 164 /* Create RQ attributes structure, used by create RQ operation. */ 165 struct mlx5_devx_create_rq_attr { 166 uint32_t rlky:1; 167 uint32_t delay_drop_en:1; 168 uint32_t scatter_fcs:1; 169 uint32_t vsd:1; 170 uint32_t mem_rq_type:4; 171 uint32_t state:4; 172 uint32_t flush_in_error_en:1; 173 uint32_t hairpin:1; 174 uint32_t user_index:24; 175 uint32_t cqn:24; 176 uint32_t counter_set_id:8; 177 uint32_t rmpn:24; 178 struct mlx5_devx_wq_attr wq_attr; 179 }; 180 181 /* Modify RQ attributes structure, used by modify RQ operation. */ 182 struct mlx5_devx_modify_rq_attr { 183 uint32_t rqn:24; 184 uint32_t rq_state:4; /* Current RQ state. */ 185 uint32_t state:4; /* Required RQ state. */ 186 uint32_t scatter_fcs:1; 187 uint32_t vsd:1; 188 uint32_t counter_set_id:8; 189 uint32_t hairpin_peer_sq:24; 190 uint32_t hairpin_peer_vhca:16; 191 uint64_t modify_bitmask; 192 uint32_t lwm:16; /* Contained WQ lwm. */ 193 }; 194 195 struct mlx5_rx_hash_field_select { 196 uint32_t l3_prot_type:1; 197 uint32_t l4_prot_type:1; 198 uint32_t selected_fields:30; 199 }; 200 201 /* TIR attributes structure, used by TIR operations. */ 202 struct mlx5_devx_tir_attr { 203 uint32_t disp_type:4; 204 uint32_t lro_timeout_period_usecs:16; 205 uint32_t lro_enable_mask:4; 206 uint32_t lro_max_msg_sz:8; 207 uint32_t inline_rqn:24; 208 uint32_t rx_hash_symmetric:1; 209 uint32_t tunneled_offload_en:1; 210 uint32_t indirect_table:24; 211 uint32_t rx_hash_fn:4; 212 uint32_t self_lb_block:2; 213 uint32_t transport_domain:24; 214 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN]; 215 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer; 216 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner; 217 }; 218 219 /* TIR attributes structure, used by TIR modify. */ 220 struct mlx5_devx_modify_tir_attr { 221 uint32_t tirn:24; 222 uint64_t modify_bitmask; 223 struct mlx5_devx_tir_attr tir; 224 }; 225 226 /* RQT attributes structure, used by RQT operations. */ 227 struct mlx5_devx_rqt_attr { 228 uint8_t rq_type; 229 uint32_t rqt_max_size:16; 230 uint32_t rqt_actual_size:16; 231 uint32_t rq_list[]; 232 }; 233 234 /* TIS attributes structure. */ 235 struct mlx5_devx_tis_attr { 236 uint32_t strict_lag_tx_port_affinity:1; 237 uint32_t tls_en:1; 238 uint32_t lag_tx_port_affinity:4; 239 uint32_t prio:4; 240 uint32_t transport_domain:24; 241 }; 242 243 /* SQ attributes structure, used by SQ create operation. */ 244 struct mlx5_devx_create_sq_attr { 245 uint32_t rlky:1; 246 uint32_t cd_master:1; 247 uint32_t fre:1; 248 uint32_t flush_in_error_en:1; 249 uint32_t allow_multi_pkt_send_wqe:1; 250 uint32_t min_wqe_inline_mode:3; 251 uint32_t state:4; 252 uint32_t reg_umr:1; 253 uint32_t allow_swp:1; 254 uint32_t hairpin:1; 255 uint32_t non_wire:1; 256 uint32_t static_sq_wq:1; 257 uint32_t user_index:24; 258 uint32_t cqn:24; 259 uint32_t packet_pacing_rate_limit_index:16; 260 uint32_t tis_lst_sz:16; 261 uint32_t tis_num:24; 262 struct mlx5_devx_wq_attr wq_attr; 263 }; 264 265 /* SQ attributes structure, used by SQ modify operation. */ 266 struct mlx5_devx_modify_sq_attr { 267 uint32_t sq_state:4; 268 uint32_t state:4; 269 uint32_t hairpin_peer_rq:24; 270 uint32_t hairpin_peer_vhca:16; 271 }; 272 273 274 /* CQ attributes structure, used by CQ operations. */ 275 struct mlx5_devx_cq_attr { 276 uint32_t q_umem_valid:1; 277 uint32_t db_umem_valid:1; 278 uint32_t use_first_only:1; 279 uint32_t overrun_ignore:1; 280 uint32_t cqe_comp_en:1; 281 uint32_t mini_cqe_res_format:2; 282 uint32_t mini_cqe_res_format_ext:2; 283 uint32_t log_cq_size:5; 284 uint32_t log_page_size:5; 285 uint32_t uar_page_id; 286 uint32_t q_umem_id; 287 uint64_t q_umem_offset; 288 uint32_t db_umem_id; 289 uint64_t db_umem_offset; 290 uint32_t eqn; 291 uint64_t db_addr; 292 }; 293 294 /* Virtq attributes structure, used by VIRTQ operations. */ 295 struct mlx5_devx_virtq_attr { 296 uint16_t hw_available_index; 297 uint16_t hw_used_index; 298 uint16_t q_size; 299 uint32_t pd:24; 300 uint32_t virtio_version_1_0:1; 301 uint32_t tso_ipv4:1; 302 uint32_t tso_ipv6:1; 303 uint32_t tx_csum:1; 304 uint32_t rx_csum:1; 305 uint32_t event_mode:3; 306 uint32_t state:4; 307 uint32_t hw_latency_mode:2; 308 uint32_t hw_max_latency_us:12; 309 uint32_t hw_max_pending_comp:16; 310 uint32_t dirty_bitmap_dump_enable:1; 311 uint32_t dirty_bitmap_mkey; 312 uint32_t dirty_bitmap_size; 313 uint32_t mkey; 314 uint32_t qp_id; 315 uint32_t queue_index; 316 uint32_t tis_id; 317 uint32_t counters_obj_id; 318 uint64_t dirty_bitmap_addr; 319 uint64_t type; 320 uint64_t desc_addr; 321 uint64_t used_addr; 322 uint64_t available_addr; 323 struct { 324 uint32_t id; 325 uint32_t size; 326 uint64_t offset; 327 } umems[3]; 328 uint8_t error_type; 329 }; 330 331 332 struct mlx5_devx_qp_attr { 333 uint32_t pd:24; 334 uint32_t uar_index:24; 335 uint32_t cqn:24; 336 uint32_t log_page_size:5; 337 uint32_t rq_size:17; /* Must be power of 2. */ 338 uint32_t log_rq_stride:3; 339 uint32_t sq_size:17; /* Must be power of 2. */ 340 uint32_t dbr_umem_valid:1; 341 uint32_t dbr_umem_id; 342 uint64_t dbr_address; 343 uint32_t wq_umem_id; 344 uint64_t wq_umem_offset; 345 }; 346 347 struct mlx5_devx_virtio_q_couners_attr { 348 uint64_t received_desc; 349 uint64_t completed_desc; 350 uint32_t error_cqes; 351 uint32_t bad_desc_errors; 352 uint32_t exceed_max_chain; 353 uint32_t invalid_buffer; 354 }; 355 356 /* 357 * graph flow match sample attributes structure, 358 * used by flex parser operations. 359 */ 360 struct mlx5_devx_match_sample_attr { 361 uint32_t flow_match_sample_en:1; 362 uint32_t flow_match_sample_field_offset:16; 363 uint32_t flow_match_sample_offset_mode:4; 364 uint32_t flow_match_sample_field_offset_mask; 365 uint32_t flow_match_sample_field_offset_shift:4; 366 uint32_t flow_match_sample_field_base_offset:8; 367 uint32_t flow_match_sample_tunnel_mode:3; 368 uint32_t flow_match_sample_field_id; 369 }; 370 371 /* graph node arc attributes structure, used by flex parser operations. */ 372 struct mlx5_devx_graph_arc_attr { 373 uint32_t compare_condition_value:16; 374 uint32_t start_inner_tunnel:1; 375 uint32_t arc_parse_graph_node:8; 376 uint32_t parse_graph_node_handle; 377 }; 378 379 /* Maximal number of samples per graph node. */ 380 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8 381 382 /* Maximal number of input/output arcs per graph node. */ 383 #define MLX5_GRAPH_NODE_ARC_NUM 8 384 385 /* parse graph node attributes structure, used by flex parser operations. */ 386 struct mlx5_devx_graph_node_attr { 387 uint32_t modify_field_select; 388 uint32_t header_length_mode:4; 389 uint32_t header_length_base_value:16; 390 uint32_t header_length_field_shift:4; 391 uint32_t header_length_field_offset:16; 392 uint32_t header_length_field_mask; 393 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM]; 394 uint32_t next_header_field_offset:16; 395 uint32_t next_header_field_size:5; 396 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM]; 397 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM]; 398 }; 399 400 /* mlx5_devx_cmds.c */ 401 402 __rte_internal 403 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx, 404 uint32_t bulk_sz); 405 __rte_internal 406 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj); 407 __rte_internal 408 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 409 int clear, uint32_t n_counters, 410 uint64_t *pkts, uint64_t *bytes, 411 uint32_t mkey, void *addr, 412 void *cmd_comp, 413 uint64_t async_id); 414 __rte_internal 415 int mlx5_devx_cmd_query_hca_attr(void *ctx, 416 struct mlx5_hca_attr *attr); 417 __rte_internal 418 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx, 419 struct mlx5_devx_mkey_attr *attr); 420 __rte_internal 421 int mlx5_devx_get_out_command_status(void *out); 422 __rte_internal 423 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 424 uint32_t *tis_td); 425 __rte_internal 426 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx, 427 struct mlx5_devx_create_rq_attr *rq_attr, 428 int socket); 429 __rte_internal 430 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 431 struct mlx5_devx_modify_rq_attr *rq_attr); 432 __rte_internal 433 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx, 434 struct mlx5_devx_tir_attr *tir_attr); 435 __rte_internal 436 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx, 437 struct mlx5_devx_rqt_attr *rqt_attr); 438 __rte_internal 439 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx, 440 struct mlx5_devx_create_sq_attr *sq_attr); 441 __rte_internal 442 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 443 struct mlx5_devx_modify_sq_attr *sq_attr); 444 __rte_internal 445 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx, 446 struct mlx5_devx_tis_attr *tis_attr); 447 __rte_internal 448 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx); 449 __rte_internal 450 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain, 451 FILE *file); 452 __rte_internal 453 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx, 454 struct mlx5_devx_cq_attr *attr); 455 __rte_internal 456 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx, 457 struct mlx5_devx_virtq_attr *attr); 458 __rte_internal 459 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 460 struct mlx5_devx_virtq_attr *attr); 461 __rte_internal 462 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 463 struct mlx5_devx_virtq_attr *attr); 464 __rte_internal 465 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx, 466 struct mlx5_devx_qp_attr *attr); 467 __rte_internal 468 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, 469 uint32_t qp_st_mod_op, uint32_t remote_qp_id); 470 __rte_internal 471 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 472 struct mlx5_devx_rqt_attr *rqt_attr); 473 __rte_internal 474 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 475 struct mlx5_devx_modify_tir_attr *tir_attr); 476 __rte_internal 477 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 478 uint32_t ids[], uint32_t num); 479 480 __rte_internal 481 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, 482 struct mlx5_devx_graph_node_attr *data); 483 484 __rte_internal 485 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, 486 uint32_t arg, uint32_t *data, uint32_t dw_cnt); 487 488 __rte_internal 489 struct mlx5_devx_obj * 490 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 491 uint16_t class, uint8_t type, uint8_t len); 492 493 /** 494 * Create virtio queue counters object DevX API. 495 * 496 * @param[in] ctx 497 * Device context. 498 499 * @return 500 * The DevX object created, NULL otherwise and rte_errno is set. 501 */ 502 __rte_internal 503 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx); 504 505 /** 506 * Query virtio queue counters object using DevX API. 507 * 508 * @param[in] couners_obj 509 * Pointer to virtq object structure. 510 * @param [in/out] attr 511 * Pointer to virtio queue counters attributes structure. 512 * 513 * @return 514 * 0 on success, a negative errno value otherwise and rte_errno is set. 515 */ 516 __rte_internal 517 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 518 struct mlx5_devx_virtio_q_couners_attr *attr); 519 __rte_internal 520 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, 521 uint32_t pd); 522 523 __rte_internal 524 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx); 525 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */ 526