1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 6WIND S.A. 3 * Copyright 2018 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_COMMON_MR_H_ 7 #define RTE_PMD_MLX5_COMMON_MR_H_ 8 9 #include <stddef.h> 10 #include <stdint.h> 11 #include <sys/queue.h> 12 13 14 #include <rte_rwlock.h> 15 #include <rte_bitmap.h> 16 #include <rte_mbuf.h> 17 #include <rte_memory.h> 18 19 #include "mlx5_glue.h" 20 #include "mlx5_common_mp.h" 21 #include "mlx5_common_defs.h" 22 23 /* mlx5 PMD MR struct. */ 24 struct mlx5_pmd_mr { 25 uint32_t lkey; 26 void *addr; 27 size_t len; 28 void *obj; /* verbs mr object or devx umem object. */ 29 struct mlx5_devx_obj *mkey; /* devx mkey object. */ 30 }; 31 32 /** 33 * mr operations typedef 34 */ 35 typedef int (*mlx5_reg_mr_t)(void *pd, void *addr, size_t length, 36 struct mlx5_pmd_mr *pmd_mr); 37 typedef void (*mlx5_dereg_mr_t)(struct mlx5_pmd_mr *pmd_mr); 38 39 /* Memory Region object. */ 40 struct mlx5_mr { 41 LIST_ENTRY(mlx5_mr) mr; /**< Pointer to the prev/next entry. */ 42 struct mlx5_pmd_mr pmd_mr; /* PMD memory region. */ 43 const struct rte_memseg_list *msl; 44 int ms_base_idx; /* Start index of msl->memseg_arr[]. */ 45 int ms_n; /* Number of memsegs in use. */ 46 uint32_t ms_bmp_n; /* Number of bits in memsegs bit-mask. */ 47 struct rte_bitmap *ms_bmp; /* Bit-mask of memsegs belonged to MR. */ 48 }; 49 50 /* Cache entry for Memory Region. */ 51 struct mr_cache_entry { 52 uintptr_t start; /* Start address of MR. */ 53 uintptr_t end; /* End address of MR. */ 54 uint32_t lkey; /* rte_cpu_to_be_32(lkey). */ 55 } __rte_packed; 56 57 /* MR Cache table for Binary search. */ 58 struct mlx5_mr_btree { 59 uint16_t len; /* Number of entries. */ 60 uint16_t size; /* Total number of entries. */ 61 int overflow; /* Mark failure of table expansion. */ 62 struct mr_cache_entry (*table)[]; 63 } __rte_packed; 64 65 struct mlx5_common_device; 66 67 /* Per-queue MR control descriptor. */ 68 struct mlx5_mr_ctrl { 69 uint32_t *dev_gen_ptr; /* Generation number of device to poll. */ 70 uint32_t cur_gen; /* Generation number saved to flush caches. */ 71 uint16_t mru; /* Index of last hit entry in top-half cache. */ 72 uint16_t head; /* Index of the oldest entry in top-half cache. */ 73 struct mr_cache_entry cache[MLX5_MR_CACHE_N]; /* Cache for top-half. */ 74 struct mlx5_mr_btree cache_bh; /* Cache for bottom-half. */ 75 } __rte_packed; 76 77 LIST_HEAD(mlx5_mr_list, mlx5_mr); 78 LIST_HEAD(mlx5_mempool_reg_list, mlx5_mempool_reg); 79 80 /* Global per-device MR cache. */ 81 struct mlx5_mr_share_cache { 82 uint32_t dev_gen; /* Generation number to flush local caches. */ 83 rte_rwlock_t rwlock; /* MR cache Lock. */ 84 rte_rwlock_t mprwlock; /* Mempool Registration Lock. */ 85 uint8_t mp_cb_registered; /* Mempool are Registered. */ 86 struct mlx5_mr_btree cache; /* Global MR cache table. */ 87 struct mlx5_mr_list mr_list; /* Registered MR list. */ 88 struct mlx5_mr_list mr_free_list; /* Freed MR list. */ 89 struct mlx5_mempool_reg_list mempool_reg_list; /* Mempool database. */ 90 mlx5_reg_mr_t reg_mr_cb; /* Callback to reg_mr func */ 91 mlx5_dereg_mr_t dereg_mr_cb; /* Callback to dereg_mr func */ 92 } __rte_packed; 93 94 /* Multi-Packet RQ buffer header. */ 95 struct mlx5_mprq_buf { 96 struct rte_mempool *mp; 97 uint16_t refcnt; /* Atomically accessed refcnt. */ 98 struct rte_mbuf_ext_shared_info shinfos[]; 99 /* 100 * Shared information per stride. 101 * More memory will be allocated for the first stride head-room and for 102 * the strides data. 103 */ 104 } __rte_cache_aligned; 105 106 __rte_internal 107 void mlx5_mprq_buf_free_cb(void *addr, void *opaque); 108 109 /** 110 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the 111 * cloned mbuf is allocated is returned instead. 112 * 113 * @param buf 114 * Pointer to mbuf. 115 * 116 * @return 117 * Memory pool where data is located for given mbuf. 118 */ 119 static inline struct rte_mempool * 120 mlx5_mb2mp(struct rte_mbuf *buf) 121 { 122 if (unlikely(RTE_MBUF_CLONED(buf))) 123 return rte_mbuf_from_indirect(buf)->pool; 124 return buf->pool; 125 } 126 127 /** 128 * Look up LKey from given lookup table by linear search. Firstly look up the 129 * last-hit entry. If miss, the entire array is searched. If found, update the 130 * last-hit index and return LKey. 131 * 132 * @param lkp_tbl 133 * Pointer to lookup table. 134 * @param[in,out] cached_idx 135 * Pointer to last-hit index. 136 * @param n 137 * Size of lookup table. 138 * @param addr 139 * Search key. 140 * 141 * @return 142 * Searched LKey on success, UINT32_MAX on no match. 143 */ 144 static __rte_always_inline uint32_t 145 mlx5_mr_lookup_lkey(struct mr_cache_entry *lkp_tbl, uint16_t *cached_idx, 146 uint16_t n, uintptr_t addr) 147 { 148 uint16_t idx; 149 150 if (likely(addr >= lkp_tbl[*cached_idx].start && 151 addr < lkp_tbl[*cached_idx].end)) 152 return lkp_tbl[*cached_idx].lkey; 153 for (idx = 0; idx < n && lkp_tbl[idx].start != 0; ++idx) { 154 if (addr >= lkp_tbl[idx].start && 155 addr < lkp_tbl[idx].end) { 156 /* Found. */ 157 *cached_idx = idx; 158 return lkp_tbl[idx].lkey; 159 } 160 } 161 return UINT32_MAX; 162 } 163 164 __rte_internal 165 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl); 166 167 /** 168 * Bottom-half of LKey search on. If supported, lookup for the address from 169 * the mempool. Otherwise, search in old mechanism caches. 170 * 171 * @param mr_ctrl 172 * Pointer to per-queue MR control structure. 173 * @param mb 174 * Pointer to mbuf. 175 * 176 * @return 177 * Searched LKey on success, UINT32_MAX on no match. 178 */ 179 __rte_internal 180 uint32_t mlx5_mr_mb2mr_bh(struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf); 181 182 /** 183 * Query LKey from a packet buffer. 184 * 185 * @param mr_ctrl 186 * Pointer to per-queue MR control structure. 187 * @param mbuf 188 * Pointer to mbuf. 189 * 190 * @return 191 * Searched LKey on success, UINT32_MAX on no match. 192 */ 193 static __rte_always_inline uint32_t 194 mlx5_mr_mb2mr(struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf) 195 { 196 uint32_t lkey; 197 198 /* Check generation bit to see if there's any change on existing MRs. */ 199 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) 200 mlx5_mr_flush_local_cache(mr_ctrl); 201 /* Linear search on MR cache array. */ 202 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, 203 MLX5_MR_CACHE_N, (uintptr_t)mbuf->buf_addr); 204 if (likely(lkey != UINT32_MAX)) 205 return lkey; 206 /* Take slower bottom-half on miss. */ 207 return mlx5_mr_mb2mr_bh(mr_ctrl, mbuf); 208 } 209 210 /* mlx5_common_mr.c */ 211 212 __rte_internal 213 int mlx5_mr_ctrl_init(struct mlx5_mr_ctrl *mr_ctrl, uint32_t *dev_gen_ptr, 214 int socket); 215 __rte_internal 216 void mlx5_mr_btree_free(struct mlx5_mr_btree *bt); 217 void mlx5_mr_btree_dump(struct mlx5_mr_btree *bt __rte_unused); 218 __rte_internal 219 uint32_t mlx5_mr_mempool2mr_bh(struct mlx5_mr_ctrl *mr_ctrl, 220 struct rte_mempool *mp, uintptr_t addr); 221 void mlx5_mr_release_cache(struct mlx5_mr_share_cache *mr_cache); 222 int mlx5_mr_create_cache(struct mlx5_mr_share_cache *share_cache, int socket); 223 void mlx5_mr_dump_cache(struct mlx5_mr_share_cache *share_cache __rte_unused); 224 void mlx5_mr_rebuild_cache(struct mlx5_mr_share_cache *share_cache); 225 void mlx5_free_mr_by_addr(struct mlx5_mr_share_cache *share_cache, 226 const char *ibdev_name, const void *addr, size_t len); 227 int mlx5_mr_insert_cache(struct mlx5_mr_share_cache *share_cache, 228 struct mlx5_mr *mr); 229 struct mlx5_mr * 230 mlx5_mr_lookup_list(struct mlx5_mr_share_cache *share_cache, 231 struct mr_cache_entry *entry, uintptr_t addr); 232 struct mlx5_mr * 233 mlx5_create_mr_ext(void *pd, uintptr_t addr, size_t len, int socket_id, 234 mlx5_reg_mr_t reg_mr_cb); 235 void mlx5_mr_free(struct mlx5_mr *mr, mlx5_dereg_mr_t dereg_mr_cb); 236 __rte_internal 237 uint32_t 238 mlx5_mr_create(struct mlx5_common_device *cdev, 239 struct mlx5_mr_share_cache *share_cache, 240 struct mr_cache_entry *entry, uintptr_t addr); 241 242 /* mlx5_common_verbs.c */ 243 244 __rte_internal 245 int 246 mlx5_common_verbs_reg_mr(void *pd, void *addr, size_t length, 247 struct mlx5_pmd_mr *pmd_mr); 248 __rte_internal 249 void 250 mlx5_common_verbs_dereg_mr(struct mlx5_pmd_mr *pmd_mr); 251 252 void 253 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, mlx5_dereg_mr_t *dereg_mr_cb); 254 255 __rte_internal 256 int 257 mlx5_mr_mempool_register(struct mlx5_common_device *cdev, 258 struct rte_mempool *mp, bool is_extmem); 259 __rte_internal 260 int 261 mlx5_mr_mempool_unregister(struct mlx5_common_device *cdev, 262 struct rte_mempool *mp); 263 264 __rte_internal 265 int 266 mlx5_mr_mempool_populate_cache(struct mlx5_mr_ctrl *mr_ctrl, 267 struct rte_mempool *mp); 268 269 #endif /* RTE_PMD_MLX5_COMMON_MR_H_ */ 270