1a77bedf2SMichael Baum /* SPDX-License-Identifier: BSD-3-Clause 2a77bedf2SMichael Baum * Copyright 2021 6WIND S.A. 3a77bedf2SMichael Baum * Copyright 2021 Mellanox Technologies, Ltd 4a77bedf2SMichael Baum */ 5a77bedf2SMichael Baum 6a77bedf2SMichael Baum #ifndef RTE_PMD_MLX5_COMMON_DEFS_H_ 7a77bedf2SMichael Baum #define RTE_PMD_MLX5_COMMON_DEFS_H_ 8a77bedf2SMichael Baum 9a77bedf2SMichael Baum #include "mlx5_autoconf.h" 10a77bedf2SMichael Baum 11a77bedf2SMichael Baum /* Size of per-queue MR cache array for linear search. */ 12a77bedf2SMichael Baum #define MLX5_MR_CACHE_N 8 13a77bedf2SMichael Baum 14a77bedf2SMichael Baum /* Size of MR cache table for binary search. */ 15a77bedf2SMichael Baum #define MLX5_MR_BTREE_CACHE_N 256 16a77bedf2SMichael Baum 17a77bedf2SMichael Baum /* 18a77bedf2SMichael Baum * Defines the amount of retries to allocate the first UAR in the page. 19a77bedf2SMichael Baum * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 20a77bedf2SMichael Baum * UAR base address if UAR was not the first object in the UAR page. 21a77bedf2SMichael Baum * It caused the PMD failure and we should try to get another UAR 22a77bedf2SMichael Baum * till we get the first one with non-NULL base address returned. 23a77bedf2SMichael Baum */ 24a77bedf2SMichael Baum #define MLX5_ALLOC_UAR_RETRY 32 25a77bedf2SMichael Baum 26a77bedf2SMichael Baum /* Environment variable to control the doorbell register mapping. */ 27a77bedf2SMichael Baum #define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF" 28a77bedf2SMichael Baum #if defined(RTE_ARCH_ARM64) 29a77bedf2SMichael Baum #define MLX5_SHUT_UP_BF_DEFAULT "0" 30a77bedf2SMichael Baum #else 31a77bedf2SMichael Baum #define MLX5_SHUT_UP_BF_DEFAULT "1" 32a77bedf2SMichael Baum #endif 33a77bedf2SMichael Baum 34a77bedf2SMichael Baum /* Default PMD specific parameter value. */ 35a77bedf2SMichael Baum #define MLX5_ARG_UNSET (-1) 36a77bedf2SMichael Baum 37*a6b9d5a5SMichael Baum /* MLX5_SQ_DB_NC supported values. */ 38*a6b9d5a5SMichael Baum #define MLX5_SQ_DB_CACHED 0 39*a6b9d5a5SMichael Baum #define MLX5_SQ_DB_NCACHED 1 40*a6b9d5a5SMichael Baum #define MLX5_SQ_DB_HEURISTIC 2 41a77bedf2SMichael Baum 425dfa003dSMichael Baum /* Fields of memory mapping type in offset parameter of mmap() */ 435dfa003dSMichael Baum #define MLX5_UAR_MMAP_CMD_SHIFT 8 445dfa003dSMichael Baum #define MLX5_UAR_MMAP_CMD_MASK 0xff 455dfa003dSMichael Baum 465dfa003dSMichael Baum #ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD 475dfa003dSMichael Baum #define MLX5_MMAP_GET_NC_PAGES_CMD 3 485dfa003dSMichael Baum #endif 495dfa003dSMichael Baum 50662d0dc6SMichael Baum #define MLX5_VDPA_MAX_RETRIES 20 51662d0dc6SMichael Baum #define MLX5_VDPA_USEC 1000 52662d0dc6SMichael Baum 53a77bedf2SMichael Baum #endif /* RTE_PMD_MLX5_COMMON_DEFS_H_ */ 54