1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 #include <string.h> 7 #include <stdio.h> 8 9 #include <rte_errno.h> 10 #include <rte_mempool.h> 11 #include <rte_malloc.h> 12 13 #include "mlx5_common.h" 14 #include "mlx5_common_os.h" 15 #include "mlx5_common_utils.h" 16 #include "mlx5_malloc.h" 17 #include "mlx5_common_pci.h" 18 19 int mlx5_common_logtype; 20 21 uint8_t haswell_broadwell_cpu; 22 23 static int 24 mlx5_class_check_handler(__rte_unused const char *key, const char *value, 25 void *opaque) 26 { 27 enum mlx5_class *ret = opaque; 28 29 if (strcmp(value, "vdpa") == 0) { 30 *ret = MLX5_CLASS_VDPA; 31 } else if (strcmp(value, "net") == 0) { 32 *ret = MLX5_CLASS_NET; 33 } else { 34 DRV_LOG(ERR, "Invalid mlx5 class %s. Maybe typo in device" 35 " class argument setting?", value); 36 *ret = MLX5_CLASS_INVALID; 37 } 38 return 0; 39 } 40 41 enum mlx5_class 42 mlx5_class_get(struct rte_devargs *devargs) 43 { 44 struct rte_kvargs *kvlist; 45 const char *key = MLX5_CLASS_ARG_NAME; 46 enum mlx5_class ret = MLX5_CLASS_NET; 47 48 if (devargs == NULL) 49 return ret; 50 kvlist = rte_kvargs_parse(devargs->args, NULL); 51 if (kvlist == NULL) 52 return ret; 53 if (rte_kvargs_count(kvlist, key)) 54 rte_kvargs_process(kvlist, key, mlx5_class_check_handler, &ret); 55 rte_kvargs_free(kvlist); 56 return ret; 57 } 58 59 60 /* In case this is an x86_64 intel processor to check if 61 * we should use relaxed ordering. 62 */ 63 #ifdef RTE_ARCH_X86_64 64 /** 65 * This function returns processor identification and feature information 66 * into the registers. 67 * 68 * @param eax, ebx, ecx, edx 69 * Pointers to the registers that will hold cpu information. 70 * @param level 71 * The main category of information returned. 72 */ 73 static inline void mlx5_cpu_id(unsigned int level, 74 unsigned int *eax, unsigned int *ebx, 75 unsigned int *ecx, unsigned int *edx) 76 { 77 __asm__("cpuid\n\t" 78 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) 79 : "0" (level)); 80 } 81 #endif 82 83 RTE_INIT_PRIO(mlx5_log_init, LOG) 84 { 85 mlx5_common_logtype = rte_log_register("pmd.common.mlx5"); 86 if (mlx5_common_logtype >= 0) 87 rte_log_set_level(mlx5_common_logtype, RTE_LOG_NOTICE); 88 } 89 90 static bool mlx5_common_initialized; 91 92 /** 93 * One time innitialization routine for run-time dependency on glue library 94 * for multiple PMDs. Each mlx5 PMD that depends on mlx5_common module, 95 * must invoke in its constructor. 96 */ 97 void 98 mlx5_common_init(void) 99 { 100 if (mlx5_common_initialized) 101 return; 102 103 mlx5_glue_constructor(); 104 mlx5_common_pci_init(); 105 mlx5_common_initialized = true; 106 } 107 108 /** 109 * This function is responsible of initializing the variable 110 * haswell_broadwell_cpu by checking if the cpu is intel 111 * and reading the data returned from mlx5_cpu_id(). 112 * since haswell and broadwell cpus don't have improved performance 113 * when using relaxed ordering we want to check the cpu type before 114 * before deciding whether to enable RO or not. 115 * if the cpu is haswell or broadwell the variable will be set to 1 116 * otherwise it will be 0. 117 */ 118 RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG) 119 { 120 #ifdef RTE_ARCH_X86_64 121 unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56}; 122 unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46}; 123 unsigned int i, model, family, brand_id, vendor; 124 unsigned int signature_intel_ebx = 0x756e6547; 125 unsigned int extended_model; 126 unsigned int eax = 0; 127 unsigned int ebx = 0; 128 unsigned int ecx = 0; 129 unsigned int edx = 0; 130 int max_level; 131 132 mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx); 133 vendor = ebx; 134 max_level = eax; 135 if (max_level < 1) { 136 haswell_broadwell_cpu = 0; 137 return; 138 } 139 mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx); 140 model = (eax >> 4) & 0x0f; 141 family = (eax >> 8) & 0x0f; 142 brand_id = ebx & 0xff; 143 extended_model = (eax >> 12) & 0xf0; 144 /* Check if the processor is Haswell or Broadwell */ 145 if (vendor == signature_intel_ebx) { 146 if (family == 0x06) 147 model += extended_model; 148 if (brand_id == 0 && family == 0x6) { 149 for (i = 0; i < RTE_DIM(broadwell_models); i++) 150 if (model == broadwell_models[i]) { 151 haswell_broadwell_cpu = 1; 152 return; 153 } 154 for (i = 0; i < RTE_DIM(haswell_models); i++) 155 if (model == haswell_models[i]) { 156 haswell_broadwell_cpu = 1; 157 return; 158 } 159 } 160 } 161 #endif 162 haswell_broadwell_cpu = 0; 163 } 164 165 /** 166 * Allocate page of door-bells and register it using DevX API. 167 * 168 * @param [in] ctx 169 * Pointer to the device context. 170 * 171 * @return 172 * Pointer to new page on success, NULL otherwise. 173 */ 174 static struct mlx5_devx_dbr_page * 175 mlx5_alloc_dbr_page(void *ctx) 176 { 177 struct mlx5_devx_dbr_page *page; 178 179 /* Allocate space for door-bell page and management data. */ 180 page = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, 181 sizeof(struct mlx5_devx_dbr_page), 182 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 183 if (!page) { 184 DRV_LOG(ERR, "cannot allocate dbr page"); 185 return NULL; 186 } 187 /* Register allocated memory. */ 188 page->umem = mlx5_glue->devx_umem_reg(ctx, page->dbrs, 189 MLX5_DBR_PAGE_SIZE, 0); 190 if (!page->umem) { 191 DRV_LOG(ERR, "cannot umem reg dbr page"); 192 mlx5_free(page); 193 return NULL; 194 } 195 return page; 196 } 197 198 /** 199 * Find the next available door-bell, allocate new page if needed. 200 * 201 * @param [in] ctx 202 * Pointer to device context. 203 * @param [in] head 204 * Pointer to the head of dbr pages list. 205 * @param [out] dbr_page 206 * Door-bell page containing the page data. 207 * 208 * @return 209 * Door-bell address offset on success, a negative error value otherwise. 210 */ 211 int64_t 212 mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head, 213 struct mlx5_devx_dbr_page **dbr_page) 214 { 215 struct mlx5_devx_dbr_page *page = NULL; 216 uint32_t i, j; 217 218 LIST_FOREACH(page, head, next) 219 if (page->dbr_count < MLX5_DBR_PER_PAGE) 220 break; 221 if (!page) { /* No page with free door-bell exists. */ 222 page = mlx5_alloc_dbr_page(ctx); 223 if (!page) /* Failed to allocate new page. */ 224 return (-1); 225 LIST_INSERT_HEAD(head, page, next); 226 } 227 /* Loop to find bitmap part with clear bit. */ 228 for (i = 0; 229 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX; 230 i++) 231 ; /* Empty. */ 232 /* Find the first clear bit. */ 233 MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE); 234 j = rte_bsf64(~page->dbr_bitmap[i]); 235 page->dbr_bitmap[i] |= (UINT64_C(1) << j); 236 page->dbr_count++; 237 *dbr_page = page; 238 return (((i * 64) + j) * sizeof(uint64_t)); 239 } 240 241 /** 242 * Release a door-bell record. 243 * 244 * @param [in] head 245 * Pointer to the head of dbr pages list. 246 * @param [in] umem_id 247 * UMEM ID of page containing the door-bell record to release. 248 * @param [in] offset 249 * Offset of door-bell record in page. 250 * 251 * @return 252 * 0 on success, a negative error value otherwise. 253 */ 254 int32_t 255 mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id, 256 uint64_t offset) 257 { 258 struct mlx5_devx_dbr_page *page = NULL; 259 int ret = 0; 260 261 LIST_FOREACH(page, head, next) 262 /* Find the page this address belongs to. */ 263 if (mlx5_os_get_umem_id(page->umem) == umem_id) 264 break; 265 if (!page) 266 return -EINVAL; 267 page->dbr_count--; 268 if (!page->dbr_count) { 269 /* Page not used, free it and remove from list. */ 270 LIST_REMOVE(page, next); 271 if (page->umem) 272 ret = -mlx5_glue->devx_umem_dereg(page->umem); 273 mlx5_free(page); 274 } else { 275 /* Mark in bitmap that this door-bell is not in use. */ 276 offset /= MLX5_DBR_SIZE; 277 int i = offset / 64; 278 int j = offset % 64; 279 280 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j); 281 } 282 return ret; 283 } 284