1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2019 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 #include <string.h> 7 #include <stdio.h> 8 9 #include <rte_errno.h> 10 #include <rte_mempool.h> 11 #include <rte_malloc.h> 12 13 #include "mlx5_common.h" 14 #include "mlx5_common_os.h" 15 #include "mlx5_common_utils.h" 16 #include "mlx5_malloc.h" 17 18 int mlx5_common_logtype; 19 20 uint8_t haswell_broadwell_cpu; 21 22 static int 23 mlx5_class_check_handler(__rte_unused const char *key, const char *value, 24 void *opaque) 25 { 26 enum mlx5_class *ret = opaque; 27 28 if (strcmp(value, "vdpa") == 0) { 29 *ret = MLX5_CLASS_VDPA; 30 } else if (strcmp(value, "net") == 0) { 31 *ret = MLX5_CLASS_NET; 32 } else { 33 DRV_LOG(ERR, "Invalid mlx5 class %s. Maybe typo in device" 34 " class argument setting?", value); 35 *ret = MLX5_CLASS_INVALID; 36 } 37 return 0; 38 } 39 40 enum mlx5_class 41 mlx5_class_get(struct rte_devargs *devargs) 42 { 43 struct rte_kvargs *kvlist; 44 const char *key = MLX5_CLASS_ARG_NAME; 45 enum mlx5_class ret = MLX5_CLASS_NET; 46 47 if (devargs == NULL) 48 return ret; 49 kvlist = rte_kvargs_parse(devargs->args, NULL); 50 if (kvlist == NULL) 51 return ret; 52 if (rte_kvargs_count(kvlist, key)) 53 rte_kvargs_process(kvlist, key, mlx5_class_check_handler, &ret); 54 rte_kvargs_free(kvlist); 55 return ret; 56 } 57 58 59 /* In case this is an x86_64 intel processor to check if 60 * we should use relaxed ordering. 61 */ 62 #ifdef RTE_ARCH_X86_64 63 /** 64 * This function returns processor identification and feature information 65 * into the registers. 66 * 67 * @param eax, ebx, ecx, edx 68 * Pointers to the registers that will hold cpu information. 69 * @param level 70 * The main category of information returned. 71 */ 72 static inline void mlx5_cpu_id(unsigned int level, 73 unsigned int *eax, unsigned int *ebx, 74 unsigned int *ecx, unsigned int *edx) 75 { 76 __asm__("cpuid\n\t" 77 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) 78 : "0" (level)); 79 } 80 #endif 81 82 RTE_INIT_PRIO(mlx5_log_init, LOG) 83 { 84 mlx5_common_logtype = rte_log_register("pmd.common.mlx5"); 85 if (mlx5_common_logtype >= 0) 86 rte_log_set_level(mlx5_common_logtype, RTE_LOG_NOTICE); 87 } 88 89 /** 90 * Initialization routine for run-time dependency on glue library. 91 */ 92 RTE_INIT_PRIO(mlx5_glue_init, CLASS) 93 { 94 mlx5_glue_constructor(); 95 } 96 97 /** 98 * This function is responsible of initializing the variable 99 * haswell_broadwell_cpu by checking if the cpu is intel 100 * and reading the data returned from mlx5_cpu_id(). 101 * since haswell and broadwell cpus don't have improved performance 102 * when using relaxed ordering we want to check the cpu type before 103 * before deciding whether to enable RO or not. 104 * if the cpu is haswell or broadwell the variable will be set to 1 105 * otherwise it will be 0. 106 */ 107 RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG) 108 { 109 #ifdef RTE_ARCH_X86_64 110 unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56}; 111 unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46}; 112 unsigned int i, model, family, brand_id, vendor; 113 unsigned int signature_intel_ebx = 0x756e6547; 114 unsigned int extended_model; 115 unsigned int eax = 0; 116 unsigned int ebx = 0; 117 unsigned int ecx = 0; 118 unsigned int edx = 0; 119 int max_level; 120 121 mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx); 122 vendor = ebx; 123 max_level = eax; 124 if (max_level < 1) { 125 haswell_broadwell_cpu = 0; 126 return; 127 } 128 mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx); 129 model = (eax >> 4) & 0x0f; 130 family = (eax >> 8) & 0x0f; 131 brand_id = ebx & 0xff; 132 extended_model = (eax >> 12) & 0xf0; 133 /* Check if the processor is Haswell or Broadwell */ 134 if (vendor == signature_intel_ebx) { 135 if (family == 0x06) 136 model += extended_model; 137 if (brand_id == 0 && family == 0x6) { 138 for (i = 0; i < RTE_DIM(broadwell_models); i++) 139 if (model == broadwell_models[i]) { 140 haswell_broadwell_cpu = 1; 141 return; 142 } 143 for (i = 0; i < RTE_DIM(haswell_models); i++) 144 if (model == haswell_models[i]) { 145 haswell_broadwell_cpu = 1; 146 return; 147 } 148 } 149 } 150 #endif 151 haswell_broadwell_cpu = 0; 152 } 153 154 /** 155 * Allocate page of door-bells and register it using DevX API. 156 * 157 * @param [in] ctx 158 * Pointer to the device context. 159 * 160 * @return 161 * Pointer to new page on success, NULL otherwise. 162 */ 163 static struct mlx5_devx_dbr_page * 164 mlx5_alloc_dbr_page(void *ctx) 165 { 166 struct mlx5_devx_dbr_page *page; 167 168 /* Allocate space for door-bell page and management data. */ 169 page = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, 170 sizeof(struct mlx5_devx_dbr_page), 171 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 172 if (!page) { 173 DRV_LOG(ERR, "cannot allocate dbr page"); 174 return NULL; 175 } 176 /* Register allocated memory. */ 177 page->umem = mlx5_glue->devx_umem_reg(ctx, page->dbrs, 178 MLX5_DBR_PAGE_SIZE, 0); 179 if (!page->umem) { 180 DRV_LOG(ERR, "cannot umem reg dbr page"); 181 mlx5_free(page); 182 return NULL; 183 } 184 return page; 185 } 186 187 /** 188 * Find the next available door-bell, allocate new page if needed. 189 * 190 * @param [in] ctx 191 * Pointer to device context. 192 * @param [in] head 193 * Pointer to the head of dbr pages list. 194 * @param [out] dbr_page 195 * Door-bell page containing the page data. 196 * 197 * @return 198 * Door-bell address offset on success, a negative error value otherwise. 199 */ 200 int64_t 201 mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head, 202 struct mlx5_devx_dbr_page **dbr_page) 203 { 204 struct mlx5_devx_dbr_page *page = NULL; 205 uint32_t i, j; 206 207 LIST_FOREACH(page, head, next) 208 if (page->dbr_count < MLX5_DBR_PER_PAGE) 209 break; 210 if (!page) { /* No page with free door-bell exists. */ 211 page = mlx5_alloc_dbr_page(ctx); 212 if (!page) /* Failed to allocate new page. */ 213 return (-1); 214 LIST_INSERT_HEAD(head, page, next); 215 } 216 /* Loop to find bitmap part with clear bit. */ 217 for (i = 0; 218 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX; 219 i++) 220 ; /* Empty. */ 221 /* Find the first clear bit. */ 222 MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE); 223 j = rte_bsf64(~page->dbr_bitmap[i]); 224 page->dbr_bitmap[i] |= (UINT64_C(1) << j); 225 page->dbr_count++; 226 *dbr_page = page; 227 return (((i * 64) + j) * sizeof(uint64_t)); 228 } 229 230 /** 231 * Release a door-bell record. 232 * 233 * @param [in] head 234 * Pointer to the head of dbr pages list. 235 * @param [in] umem_id 236 * UMEM ID of page containing the door-bell record to release. 237 * @param [in] offset 238 * Offset of door-bell record in page. 239 * 240 * @return 241 * 0 on success, a negative error value otherwise. 242 */ 243 int32_t 244 mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id, 245 uint64_t offset) 246 { 247 struct mlx5_devx_dbr_page *page = NULL; 248 int ret = 0; 249 250 LIST_FOREACH(page, head, next) 251 /* Find the page this address belongs to. */ 252 if (mlx5_os_get_umem_id(page->umem) == umem_id) 253 break; 254 if (!page) 255 return -EINVAL; 256 page->dbr_count--; 257 if (!page->dbr_count) { 258 /* Page not used, free it and remove from list. */ 259 LIST_REMOVE(page, next); 260 if (page->umem) 261 ret = -mlx5_glue->devx_umem_dereg(page->umem); 262 mlx5_free(page); 263 } else { 264 /* Mark in bitmap that this door-bell is not in use. */ 265 offset /= MLX5_DBR_SIZE; 266 int i = offset / 64; 267 int j = offset % 64; 268 269 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j); 270 } 271 return ret; 272 } 273