xref: /dpdk/drivers/common/idpf/base/idpf_osdep.h (revision e77506397fc8005c5129e22e9e2d15d5876790fd)
1fb4ac04eSJunfeng Guo /* SPDX-License-Identifier: BSD-3-Clause
29510c5f8SSoumyadeep Hore  * Copyright(c) 2001-2024 Intel Corporation
3fb4ac04eSJunfeng Guo  */
4fb4ac04eSJunfeng Guo 
5fb4ac04eSJunfeng Guo #ifndef _IDPF_OSDEP_H_
6fb4ac04eSJunfeng Guo #define _IDPF_OSDEP_H_
7fb4ac04eSJunfeng Guo 
8fb4ac04eSJunfeng Guo #include <string.h>
9fb4ac04eSJunfeng Guo #include <stdint.h>
10fb4ac04eSJunfeng Guo #include <stdio.h>
11fb4ac04eSJunfeng Guo #include <stdarg.h>
12fb4ac04eSJunfeng Guo #include <inttypes.h>
13fb4ac04eSJunfeng Guo #include <sys/queue.h>
14fb4ac04eSJunfeng Guo #include <stdbool.h>
15fb4ac04eSJunfeng Guo 
16fb4ac04eSJunfeng Guo #include <rte_common.h>
17fb4ac04eSJunfeng Guo #include <rte_memcpy.h>
18fb4ac04eSJunfeng Guo #include <rte_malloc.h>
19fb4ac04eSJunfeng Guo #include <rte_memzone.h>
20fb4ac04eSJunfeng Guo #include <rte_byteorder.h>
21fb4ac04eSJunfeng Guo #include <rte_cycles.h>
22fb4ac04eSJunfeng Guo #include <rte_spinlock.h>
23fb4ac04eSJunfeng Guo #include <rte_log.h>
24fb4ac04eSJunfeng Guo #include <rte_random.h>
25fb4ac04eSJunfeng Guo #include <rte_io.h>
2667c82e9aSQi Zhang #include <rte_compat.h>
27fb4ac04eSJunfeng Guo 
283cd9f24dSDavid Marchand #include "../idpf_common_logs.h"
293cd9f24dSDavid Marchand 
30fb4ac04eSJunfeng Guo #define INLINE inline
31fb4ac04eSJunfeng Guo #define STATIC static
32fb4ac04eSJunfeng Guo 
33fb4ac04eSJunfeng Guo typedef uint8_t		u8;
34fb4ac04eSJunfeng Guo typedef int8_t		s8;
35fb4ac04eSJunfeng Guo typedef uint16_t	u16;
36fb4ac04eSJunfeng Guo typedef int16_t		s16;
37fb4ac04eSJunfeng Guo typedef uint32_t	u32;
38fb4ac04eSJunfeng Guo typedef int32_t		s32;
39fb4ac04eSJunfeng Guo typedef uint64_t	u64;
40fb4ac04eSJunfeng Guo typedef uint64_t	s64;
41fb4ac04eSJunfeng Guo 
42fb4ac04eSJunfeng Guo typedef struct idpf_lock idpf_lock;
43fb4ac04eSJunfeng Guo 
44fb4ac04eSJunfeng Guo #define __iomem
45fd51012dSAndre Muezerie #define hw_dbg(hw, S, ...)	do {} while (0)
46fb4ac04eSJunfeng Guo #define upper_32_bits(n)	((u32)(((n) >> 16) >> 16))
47fb4ac04eSJunfeng Guo #define lower_32_bits(n)	((u32)(n))
48fb4ac04eSJunfeng Guo #define low_16_bits(x)		((x) & 0xFFFF)
49fb4ac04eSJunfeng Guo #define high_16_bits(x)		(((x) & 0xFFFF0000) >> 16)
50fb4ac04eSJunfeng Guo 
51743d7442SWenjing Qiao #define IDPF_M(m, s)		((m) << (s))
52743d7442SWenjing Qiao 
538b8eab71SSimei Su #define BITS_PER_LONG (8 * sizeof(long))
548b8eab71SSimei Su #define BITS_PER_LONG_LONG (8 * sizeof(long long))
558b8eab71SSimei Su #define GENMASK(h, l) \
568b8eab71SSimei Su 	(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
578b8eab71SSimei Su #define GENMASK_ULL(h, l) \
588b8eab71SSimei Su 	(((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
598b8eab71SSimei Su 
60fb4ac04eSJunfeng Guo #ifndef ETH_ADDR_LEN
61fb4ac04eSJunfeng Guo #define ETH_ADDR_LEN		6
62fb4ac04eSJunfeng Guo #endif
63fb4ac04eSJunfeng Guo 
64fb4ac04eSJunfeng Guo #ifndef __le16
65fb4ac04eSJunfeng Guo #define __le16	uint16_t
66fb4ac04eSJunfeng Guo #endif
67fb4ac04eSJunfeng Guo #ifndef __le32
68fb4ac04eSJunfeng Guo #define __le32	uint32_t
69fb4ac04eSJunfeng Guo #endif
70fb4ac04eSJunfeng Guo #ifndef __le64
71fb4ac04eSJunfeng Guo #define __le64	uint64_t
72fb4ac04eSJunfeng Guo #endif
73fb4ac04eSJunfeng Guo #ifndef __be16
74fb4ac04eSJunfeng Guo #define __be16	uint16_t
75fb4ac04eSJunfeng Guo #endif
76fb4ac04eSJunfeng Guo #ifndef __be32
77fb4ac04eSJunfeng Guo #define __be32	uint32_t
78fb4ac04eSJunfeng Guo #endif
79fb4ac04eSJunfeng Guo #ifndef __be64
80fb4ac04eSJunfeng Guo #define __be64	uint64_t
81fb4ac04eSJunfeng Guo #endif
82fb4ac04eSJunfeng Guo 
83fb4ac04eSJunfeng Guo #ifndef BIT_ULL
84fb4ac04eSJunfeng Guo #define BIT_ULL(a) RTE_BIT64(a)
85fb4ac04eSJunfeng Guo #endif
86fb4ac04eSJunfeng Guo 
87fb4ac04eSJunfeng Guo #ifndef BIT
88fb4ac04eSJunfeng Guo #define BIT(a) RTE_BIT32(a)
89fb4ac04eSJunfeng Guo #endif
90fb4ac04eSJunfeng Guo 
91fb4ac04eSJunfeng Guo #define FALSE	0
92fb4ac04eSJunfeng Guo #define TRUE	1
93fb4ac04eSJunfeng Guo #define false	0
94fb4ac04eSJunfeng Guo #define true	1
95fb4ac04eSJunfeng Guo 
96fb4ac04eSJunfeng Guo /* Avoid macro redefinition warning on Windows */
97fb4ac04eSJunfeng Guo #ifdef RTE_EXEC_ENV_WINDOWS
98fb4ac04eSJunfeng Guo #ifdef min
99fb4ac04eSJunfeng Guo #undef min
100fb4ac04eSJunfeng Guo #endif
101fb4ac04eSJunfeng Guo #ifdef max
102fb4ac04eSJunfeng Guo #undef max
103fb4ac04eSJunfeng Guo #endif
104fb4ac04eSJunfeng Guo #endif
105fb4ac04eSJunfeng Guo 
106fb4ac04eSJunfeng Guo #define min(a, b) RTE_MIN(a, b)
107fb4ac04eSJunfeng Guo #define max(a, b) RTE_MAX(a, b)
108fb4ac04eSJunfeng Guo 
109fb4ac04eSJunfeng Guo #define ARRAY_SIZE(arr)  RTE_DIM(arr)
110fb4ac04eSJunfeng Guo #define FIELD_SIZEOF(t, f) (sizeof(((t *)0)->(f)))
111fb4ac04eSJunfeng Guo #define MAKEMASK(m, s) ((m) << (s))
112fb4ac04eSJunfeng Guo 
1133cd9f24dSDavid Marchand #define DEBUGOUT(S, ...)	RTE_LOG(DEBUG, IDPF_COMMON, S, ## __VA_ARGS__)
1143cd9f24dSDavid Marchand #define DEBUGOUT2(S, ...)	DEBUGOUT(S, ## __VA_ARGS__)
115fb4ac04eSJunfeng Guo #define DEBUGFUNC(F)		DEBUGOUT(F "\n")
116fb4ac04eSJunfeng Guo 
117fb4ac04eSJunfeng Guo #define idpf_debug(h, m, s, ...)					\
118fb4ac04eSJunfeng Guo 	do {								\
119fb4ac04eSJunfeng Guo 		if (((m) & (h)->debug_mask))				\
1203cd9f24dSDavid Marchand 			DEBUGOUT("idpf %02x.%x " s "\n",		\
121fb4ac04eSJunfeng Guo 					(h)->bus.device, (h)->bus.func,	\
122fb4ac04eSJunfeng Guo 					##__VA_ARGS__);			\
123fb4ac04eSJunfeng Guo 	} while (0)
124fb4ac04eSJunfeng Guo 
125fd51012dSAndre Muezerie #define idpf_info(hw, fmt, ...) \
126fd51012dSAndre Muezerie 	idpf_debug(hw, IDPF_DBG_ALL, fmt, ##__VA_ARGS__)
127fd51012dSAndre Muezerie #define idpf_warn(hw, fmt, ...) \
128fd51012dSAndre Muezerie 	idpf_debug(hw, IDPF_DBG_ALL, fmt, ##__VA_ARGS__)
129fb4ac04eSJunfeng Guo #define idpf_debug_array(hw, type, rowsize, groupsize, buf, len)	\
130fb4ac04eSJunfeng Guo 	do {								\
131fb4ac04eSJunfeng Guo 		struct idpf_hw *hw_l = hw;				\
132fb4ac04eSJunfeng Guo 		u16 len_l = len;					\
133fb4ac04eSJunfeng Guo 		u8 *buf_l = buf;					\
134fb4ac04eSJunfeng Guo 		int i;							\
135fb4ac04eSJunfeng Guo 		for (i = 0; i < len_l; i += 8)				\
136fb4ac04eSJunfeng Guo 			idpf_debug(hw_l, type,				\
137fb4ac04eSJunfeng Guo 				   "0x%04X  0x%016"PRIx64"\n",		\
138fb4ac04eSJunfeng Guo 				   i, *((u64 *)((buf_l) + i)));		\
139fb4ac04eSJunfeng Guo 	} while (0)
140fb4ac04eSJunfeng Guo #define idpf_snprintf snprintf
141fb4ac04eSJunfeng Guo #ifndef SNPRINTF
142fb4ac04eSJunfeng Guo #define SNPRINTF idpf_snprintf
143fb4ac04eSJunfeng Guo #endif
144fb4ac04eSJunfeng Guo 
145fb4ac04eSJunfeng Guo #define IDPF_PCI_REG(reg)     rte_read32(reg)
146fb4ac04eSJunfeng Guo #define IDPF_PCI_REG_ADDR(a, reg)				\
147fb4ac04eSJunfeng Guo 	((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))
148fb4ac04eSJunfeng Guo #define IDPF_PCI_REG64(reg)     rte_read64(reg)
149fb4ac04eSJunfeng Guo #define IDPF_PCI_REG_ADDR64(a, reg)				\
150fb4ac04eSJunfeng Guo 	((volatile uint64_t *)((char *)(a)->hw_addr + (reg)))
151fb4ac04eSJunfeng Guo 
152fb4ac04eSJunfeng Guo #define idpf_wmb() rte_io_wmb()
153fb4ac04eSJunfeng Guo #define idpf_rmb() rte_io_rmb()
154fb4ac04eSJunfeng Guo #define idpf_mb() rte_io_mb()
155fb4ac04eSJunfeng Guo 
156fb4ac04eSJunfeng Guo static inline uint32_t idpf_read_addr(volatile void *addr)
157fb4ac04eSJunfeng Guo {
158fb4ac04eSJunfeng Guo 	return rte_le_to_cpu_32(IDPF_PCI_REG(addr));
159fb4ac04eSJunfeng Guo }
160fb4ac04eSJunfeng Guo 
161fb4ac04eSJunfeng Guo static inline uint64_t idpf_read_addr64(volatile void *addr)
162fb4ac04eSJunfeng Guo {
163fb4ac04eSJunfeng Guo 	return rte_le_to_cpu_64(IDPF_PCI_REG64(addr));
164fb4ac04eSJunfeng Guo }
165fb4ac04eSJunfeng Guo 
166fb4ac04eSJunfeng Guo #define IDPF_PCI_REG_WRITE(reg, value)			\
167fb4ac04eSJunfeng Guo 	rte_write32((rte_cpu_to_le_32(value)), reg)
168fb4ac04eSJunfeng Guo 
169fb4ac04eSJunfeng Guo #define IDPF_PCI_REG_WRITE64(reg, value)		\
170fb4ac04eSJunfeng Guo 	rte_write64((rte_cpu_to_le_64(value)), reg)
171fb4ac04eSJunfeng Guo 
172fb4ac04eSJunfeng Guo #define IDPF_READ_REG(hw, reg) idpf_read_addr(IDPF_PCI_REG_ADDR((hw), (reg)))
173fb4ac04eSJunfeng Guo #define IDPF_WRITE_REG(hw, reg, value)					\
174fb4ac04eSJunfeng Guo 	IDPF_PCI_REG_WRITE(IDPF_PCI_REG_ADDR((hw), (reg)), (value))
175fb4ac04eSJunfeng Guo 
176fb4ac04eSJunfeng Guo #define rd32(a, reg) idpf_read_addr(IDPF_PCI_REG_ADDR((a), (reg)))
177fb4ac04eSJunfeng Guo #define wr32(a, reg, value)						\
178fb4ac04eSJunfeng Guo 	IDPF_PCI_REG_WRITE(IDPF_PCI_REG_ADDR((a), (reg)), (value))
179fb4ac04eSJunfeng Guo #define div64_long(n, d) ((n) / (d))
180fb4ac04eSJunfeng Guo #define rd64(a, reg) idpf_read_addr64(IDPF_PCI_REG_ADDR64((a), (reg)))
181fb4ac04eSJunfeng Guo 
182fb4ac04eSJunfeng Guo #define BITS_PER_BYTE       8
183fb4ac04eSJunfeng Guo 
184fb4ac04eSJunfeng Guo /* memory allocation tracking */
185*e7750639SAndre Muezerie struct __rte_packed_begin idpf_dma_mem {
186fb4ac04eSJunfeng Guo 	void *va;
187fb4ac04eSJunfeng Guo 	u64 pa;
188fb4ac04eSJunfeng Guo 	u32 size;
189fb4ac04eSJunfeng Guo 	const void *zone;
190*e7750639SAndre Muezerie } __rte_packed_end;
191fb4ac04eSJunfeng Guo 
192*e7750639SAndre Muezerie struct __rte_packed_begin idpf_virt_mem {
193fb4ac04eSJunfeng Guo 	void *va;
194fb4ac04eSJunfeng Guo 	u32 size;
195*e7750639SAndre Muezerie } __rte_packed_end;
196fb4ac04eSJunfeng Guo 
197fb4ac04eSJunfeng Guo #define idpf_malloc(h, s)	rte_zmalloc(NULL, s, 0)
198fb4ac04eSJunfeng Guo #define idpf_calloc(h, c, s)	rte_zmalloc(NULL, (c) * (s), 0)
199fb4ac04eSJunfeng Guo #define idpf_free(h, m)		rte_free(m)
200fb4ac04eSJunfeng Guo 
201fb4ac04eSJunfeng Guo #define idpf_memset(a, b, c, d)	memset((a), (b), (c))
202fb4ac04eSJunfeng Guo #define idpf_memcpy(a, b, c, d)	rte_memcpy((a), (b), (c))
203fb4ac04eSJunfeng Guo #define idpf_memdup(a, b, c, d)	rte_memcpy(idpf_malloc(a, c), b, c)
204fb4ac04eSJunfeng Guo 
205fb4ac04eSJunfeng Guo #define CPU_TO_BE16(o) rte_cpu_to_be_16(o)
206fb4ac04eSJunfeng Guo #define CPU_TO_BE32(o) rte_cpu_to_be_32(o)
207fb4ac04eSJunfeng Guo #define CPU_TO_BE64(o) rte_cpu_to_be_64(o)
208fb4ac04eSJunfeng Guo #define CPU_TO_LE16(o) rte_cpu_to_le_16(o)
209fb4ac04eSJunfeng Guo #define CPU_TO_LE32(s) rte_cpu_to_le_32(s)
210fb4ac04eSJunfeng Guo #define CPU_TO_LE64(h) rte_cpu_to_le_64(h)
211fb4ac04eSJunfeng Guo #define LE16_TO_CPU(a) rte_le_to_cpu_16(a)
212fb4ac04eSJunfeng Guo #define LE32_TO_CPU(c) rte_le_to_cpu_32(c)
213fb4ac04eSJunfeng Guo #define LE64_TO_CPU(k) rte_le_to_cpu_64(k)
214fb4ac04eSJunfeng Guo 
215fb4ac04eSJunfeng Guo #define NTOHS(a) rte_be_to_cpu_16(a)
216fb4ac04eSJunfeng Guo #define NTOHL(a) rte_be_to_cpu_32(a)
217fb4ac04eSJunfeng Guo #define HTONS(a) rte_cpu_to_be_16(a)
218fb4ac04eSJunfeng Guo #define HTONL(a) rte_cpu_to_be_32(a)
219fb4ac04eSJunfeng Guo 
220fb4ac04eSJunfeng Guo /* SW spinlock */
221fb4ac04eSJunfeng Guo struct idpf_lock {
222fb4ac04eSJunfeng Guo 	rte_spinlock_t spinlock;
223fb4ac04eSJunfeng Guo };
224fb4ac04eSJunfeng Guo 
225d9ebf5ddSDavid Marchand #define idpf_init_lock(sp) rte_spinlock_init(&(sp)->spinlock)
226d9ebf5ddSDavid Marchand #define idpf_acquire_lock(sp) rte_spinlock_lock(&(sp)->spinlock)
227d9ebf5ddSDavid Marchand #define idpf_release_lock(sp) rte_spinlock_unlock(&(sp)->spinlock)
228d9ebf5ddSDavid Marchand #define idpf_destroy_lock(sp) RTE_SET_USED(sp)
229fb4ac04eSJunfeng Guo 
230fb4ac04eSJunfeng Guo struct idpf_hw;
231fb4ac04eSJunfeng Guo 
232fb4ac04eSJunfeng Guo static inline void *
233fb4ac04eSJunfeng Guo idpf_alloc_dma_mem(__rte_unused struct idpf_hw *hw,
234fb4ac04eSJunfeng Guo 		   struct idpf_dma_mem *mem, u64 size)
235fb4ac04eSJunfeng Guo {
236fb4ac04eSJunfeng Guo 	const struct rte_memzone *mz = NULL;
237fb4ac04eSJunfeng Guo 	char z_name[RTE_MEMZONE_NAMESIZE];
238fb4ac04eSJunfeng Guo 
239fb4ac04eSJunfeng Guo 	if (!mem)
240fb4ac04eSJunfeng Guo 		return NULL;
241fb4ac04eSJunfeng Guo 
242fb4ac04eSJunfeng Guo 	snprintf(z_name, sizeof(z_name), "idpf_dma_%"PRIu64, rte_rand());
243fb4ac04eSJunfeng Guo 	mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY,
244fb4ac04eSJunfeng Guo 					 RTE_MEMZONE_IOVA_CONTIG, RTE_PGSIZE_4K);
245fb4ac04eSJunfeng Guo 	if (!mz)
246fb4ac04eSJunfeng Guo 		return NULL;
247fb4ac04eSJunfeng Guo 
248fb4ac04eSJunfeng Guo 	mem->size = size;
249fb4ac04eSJunfeng Guo 	mem->va = mz->addr;
250fb4ac04eSJunfeng Guo 	mem->pa = mz->iova;
251fb4ac04eSJunfeng Guo 	mem->zone = (const void *)mz;
252fb4ac04eSJunfeng Guo 	memset(mem->va, 0, size);
253fb4ac04eSJunfeng Guo 
254fb4ac04eSJunfeng Guo 	return mem->va;
255fb4ac04eSJunfeng Guo }
256fb4ac04eSJunfeng Guo 
257fb4ac04eSJunfeng Guo static inline void
258fb4ac04eSJunfeng Guo idpf_free_dma_mem(__rte_unused struct idpf_hw *hw,
259fb4ac04eSJunfeng Guo 		  struct idpf_dma_mem *mem)
260fb4ac04eSJunfeng Guo {
261fb4ac04eSJunfeng Guo 	rte_memzone_free((const struct rte_memzone *)mem->zone);
262fb4ac04eSJunfeng Guo 	mem->size = 0;
263fb4ac04eSJunfeng Guo 	mem->va = NULL;
264fb4ac04eSJunfeng Guo 	mem->pa = 0;
265fb4ac04eSJunfeng Guo }
266fb4ac04eSJunfeng Guo 
267fb4ac04eSJunfeng Guo static inline u8
268fb4ac04eSJunfeng Guo idpf_hweight8(u32 num)
269fb4ac04eSJunfeng Guo {
270fb4ac04eSJunfeng Guo 	u8 bits = 0;
271fb4ac04eSJunfeng Guo 	u32 i;
272fb4ac04eSJunfeng Guo 
273fb4ac04eSJunfeng Guo 	for (i = 0; i < 8; i++) {
274fb4ac04eSJunfeng Guo 		bits += (u8)(num & 0x1);
275fb4ac04eSJunfeng Guo 		num >>= 1;
276fb4ac04eSJunfeng Guo 	}
277fb4ac04eSJunfeng Guo 
278fb4ac04eSJunfeng Guo 	return bits;
279fb4ac04eSJunfeng Guo }
280fb4ac04eSJunfeng Guo 
281fb4ac04eSJunfeng Guo static inline u8
282fb4ac04eSJunfeng Guo idpf_hweight32(u32 num)
283fb4ac04eSJunfeng Guo {
284fb4ac04eSJunfeng Guo 	u8 bits = 0;
285fb4ac04eSJunfeng Guo 	u32 i;
286fb4ac04eSJunfeng Guo 
287fb4ac04eSJunfeng Guo 	for (i = 0; i < 32; i++) {
288fb4ac04eSJunfeng Guo 		bits += (u8)(num & 0x1);
289fb4ac04eSJunfeng Guo 		num >>= 1;
290fb4ac04eSJunfeng Guo 	}
291fb4ac04eSJunfeng Guo 
292fb4ac04eSJunfeng Guo 	return bits;
293fb4ac04eSJunfeng Guo }
294fb4ac04eSJunfeng Guo 
295fb4ac04eSJunfeng Guo #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
296fb4ac04eSJunfeng Guo #define DELAY(x) rte_delay_us(x)
297fb4ac04eSJunfeng Guo #define idpf_usec_delay(x) rte_delay_us(x)
298fb4ac04eSJunfeng Guo #define idpf_msec_delay(x, y) rte_delay_us(1000 * (x))
299fb4ac04eSJunfeng Guo #define udelay(x) DELAY(x)
300fb4ac04eSJunfeng Guo #define msleep(x) DELAY(1000 * (x))
301fb4ac04eSJunfeng Guo #define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))
302fb4ac04eSJunfeng Guo 
303fb4ac04eSJunfeng Guo #ifndef IDPF_DBG_TRACE
304fb4ac04eSJunfeng Guo #define IDPF_DBG_TRACE	  BIT_ULL(0)
305fb4ac04eSJunfeng Guo #endif
306fb4ac04eSJunfeng Guo 
307fb4ac04eSJunfeng Guo #ifndef DIVIDE_AND_ROUND_UP
308fb4ac04eSJunfeng Guo #define DIVIDE_AND_ROUND_UP(a, b) (((a) + (b) - 1) / (b))
309fb4ac04eSJunfeng Guo #endif
310fb4ac04eSJunfeng Guo 
311fb4ac04eSJunfeng Guo #ifndef IDPF_INTEL_VENDOR_ID
312fb4ac04eSJunfeng Guo #define IDPF_INTEL_VENDOR_ID	    0x8086
313fb4ac04eSJunfeng Guo #endif
314fb4ac04eSJunfeng Guo 
315fb4ac04eSJunfeng Guo #ifndef IS_UNICAST_ETHER_ADDR
316fb4ac04eSJunfeng Guo #define IS_UNICAST_ETHER_ADDR(addr)			\
317fb4ac04eSJunfeng Guo 	((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0))
318fb4ac04eSJunfeng Guo #endif
319fb4ac04eSJunfeng Guo 
320fb4ac04eSJunfeng Guo #ifndef IS_MULTICAST_ETHER_ADDR
321fb4ac04eSJunfeng Guo #define IS_MULTICAST_ETHER_ADDR(addr)			\
322fb4ac04eSJunfeng Guo 	((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1))
323fb4ac04eSJunfeng Guo #endif
324fb4ac04eSJunfeng Guo 
325fb4ac04eSJunfeng Guo #ifndef IS_BROADCAST_ETHER_ADDR
326fb4ac04eSJunfeng Guo /* Check whether an address is broadcast. */
327fb4ac04eSJunfeng Guo #define IS_BROADCAST_ETHER_ADDR(addr)			\
328fb4ac04eSJunfeng Guo 	((bool)((((u16 *)(addr))[0] == ((u16)0xffff))))
329fb4ac04eSJunfeng Guo #endif
330fb4ac04eSJunfeng Guo 
331fb4ac04eSJunfeng Guo #ifndef IS_ZERO_ETHER_ADDR
332fb4ac04eSJunfeng Guo #define IS_ZERO_ETHER_ADDR(addr)				\
333fb4ac04eSJunfeng Guo 	(((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) &&	\
334fb4ac04eSJunfeng Guo 	 ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) &&	\
335fb4ac04eSJunfeng Guo 	 ((bool)((((u16 *)(addr))[2] == ((u16)0x0)))))
336fb4ac04eSJunfeng Guo #endif
337fb4ac04eSJunfeng Guo 
338fb4ac04eSJunfeng Guo #ifndef LIST_HEAD_TYPE
339fb4ac04eSJunfeng Guo #define LIST_HEAD_TYPE(list_name, type) LIST_HEAD(list_name, type)
340fb4ac04eSJunfeng Guo #endif
341fb4ac04eSJunfeng Guo 
342fb4ac04eSJunfeng Guo #ifndef LIST_ENTRY_TYPE
343fb4ac04eSJunfeng Guo #define LIST_ENTRY_TYPE(type)	   LIST_ENTRY(type)
344fb4ac04eSJunfeng Guo #endif
345fb4ac04eSJunfeng Guo 
3464baf54edSStephen Hemminger #ifndef LIST_FOREACH_SAFE
3474baf54edSStephen Hemminger #define LIST_FOREACH_SAFE(var, head, field, tvar)			\
3484baf54edSStephen Hemminger 	for ((var) = LIST_FIRST((head));				\
3494baf54edSStephen Hemminger 	    (var) && ((tvar) = LIST_NEXT((var), field), 1);		\
3504baf54edSStephen Hemminger 	    (var) = (tvar))
3514baf54edSStephen Hemminger #endif
3524baf54edSStephen Hemminger 
353fb4ac04eSJunfeng Guo #ifndef LIST_FOR_EACH_ENTRY_SAFE
354fb4ac04eSJunfeng Guo #define LIST_FOR_EACH_ENTRY_SAFE(pos, temp, head, entry_type, list)	\
3554baf54edSStephen Hemminger 	LIST_FOREACH_SAFE(pos, head, list, temp)
356fb4ac04eSJunfeng Guo #endif
357fb4ac04eSJunfeng Guo 
358fb4ac04eSJunfeng Guo #ifndef LIST_FOR_EACH_ENTRY
359fb4ac04eSJunfeng Guo #define LIST_FOR_EACH_ENTRY(pos, head, entry_type, list)		\
360fb4ac04eSJunfeng Guo 	LIST_FOREACH(pos, head, list)
361fb4ac04eSJunfeng Guo 
362fb4ac04eSJunfeng Guo #endif
363fb4ac04eSJunfeng Guo 
3649510c5f8SSoumyadeep Hore enum idpf_mac_type {
3659510c5f8SSoumyadeep Hore 	IDPF_MAC_UNKNOWN = 0,
3669510c5f8SSoumyadeep Hore 	IDPF_MAC_PF,
3679510c5f8SSoumyadeep Hore 	IDPF_MAC_VF,
3689510c5f8SSoumyadeep Hore 	IDPF_MAC_GENERIC
3699510c5f8SSoumyadeep Hore };
3709510c5f8SSoumyadeep Hore 
3719510c5f8SSoumyadeep Hore #define ETH_ALEN 6
3729510c5f8SSoumyadeep Hore 
3739510c5f8SSoumyadeep Hore struct idpf_mac_info {
3749510c5f8SSoumyadeep Hore 	enum idpf_mac_type type;
3759510c5f8SSoumyadeep Hore 	u8 addr[ETH_ALEN];
3769510c5f8SSoumyadeep Hore 	u8 perm_addr[ETH_ALEN];
3779510c5f8SSoumyadeep Hore };
3789510c5f8SSoumyadeep Hore 
3799510c5f8SSoumyadeep Hore #define IDPF_AQ_LINK_UP 0x1
3809510c5f8SSoumyadeep Hore 
3819510c5f8SSoumyadeep Hore /* PCI bus types */
3829510c5f8SSoumyadeep Hore enum idpf_bus_type {
3839510c5f8SSoumyadeep Hore 	idpf_bus_type_unknown = 0,
3849510c5f8SSoumyadeep Hore 	idpf_bus_type_pci,
3859510c5f8SSoumyadeep Hore 	idpf_bus_type_pcix,
3869510c5f8SSoumyadeep Hore 	idpf_bus_type_pci_express,
3879510c5f8SSoumyadeep Hore 	idpf_bus_type_reserved
3889510c5f8SSoumyadeep Hore };
3899510c5f8SSoumyadeep Hore 
3909510c5f8SSoumyadeep Hore /* PCI bus speeds */
3919510c5f8SSoumyadeep Hore enum idpf_bus_speed {
3929510c5f8SSoumyadeep Hore 	idpf_bus_speed_unknown	= 0,
3939510c5f8SSoumyadeep Hore 	idpf_bus_speed_33	= 33,
3949510c5f8SSoumyadeep Hore 	idpf_bus_speed_66	= 66,
3959510c5f8SSoumyadeep Hore 	idpf_bus_speed_100	= 100,
3969510c5f8SSoumyadeep Hore 	idpf_bus_speed_120	= 120,
3979510c5f8SSoumyadeep Hore 	idpf_bus_speed_133	= 133,
3989510c5f8SSoumyadeep Hore 	idpf_bus_speed_2500	= 2500,
3999510c5f8SSoumyadeep Hore 	idpf_bus_speed_5000	= 5000,
4009510c5f8SSoumyadeep Hore 	idpf_bus_speed_8000	= 8000,
4019510c5f8SSoumyadeep Hore 	idpf_bus_speed_reserved
4029510c5f8SSoumyadeep Hore };
4039510c5f8SSoumyadeep Hore 
4049510c5f8SSoumyadeep Hore /* PCI bus widths */
4059510c5f8SSoumyadeep Hore enum idpf_bus_width {
4069510c5f8SSoumyadeep Hore 	idpf_bus_width_unknown	= 0,
4079510c5f8SSoumyadeep Hore 	idpf_bus_width_pcie_x1	= 1,
4089510c5f8SSoumyadeep Hore 	idpf_bus_width_pcie_x2	= 2,
4099510c5f8SSoumyadeep Hore 	idpf_bus_width_pcie_x4	= 4,
4109510c5f8SSoumyadeep Hore 	idpf_bus_width_pcie_x8	= 8,
4119510c5f8SSoumyadeep Hore 	idpf_bus_width_32	= 32,
4129510c5f8SSoumyadeep Hore 	idpf_bus_width_64	= 64,
4139510c5f8SSoumyadeep Hore 	idpf_bus_width_reserved
4149510c5f8SSoumyadeep Hore };
4159510c5f8SSoumyadeep Hore 
4169510c5f8SSoumyadeep Hore /* Bus parameters */
4179510c5f8SSoumyadeep Hore struct idpf_bus_info {
4189510c5f8SSoumyadeep Hore 	enum idpf_bus_speed speed;
4199510c5f8SSoumyadeep Hore 	enum idpf_bus_width width;
4209510c5f8SSoumyadeep Hore 	enum idpf_bus_type type;
4219510c5f8SSoumyadeep Hore 
4229510c5f8SSoumyadeep Hore 	u16 func;
4239510c5f8SSoumyadeep Hore 	u16 device;
4249510c5f8SSoumyadeep Hore 	u16 lan_id;
4259510c5f8SSoumyadeep Hore 	u16 bus_id;
4269510c5f8SSoumyadeep Hore };
4279510c5f8SSoumyadeep Hore 
4289510c5f8SSoumyadeep Hore /* Function specific capabilities */
4299510c5f8SSoumyadeep Hore struct idpf_hw_func_caps {
4309510c5f8SSoumyadeep Hore 	u32 num_alloc_vfs;
4319510c5f8SSoumyadeep Hore 	u32 vf_base_id;
4329510c5f8SSoumyadeep Hore };
4339510c5f8SSoumyadeep Hore 
434fb4ac04eSJunfeng Guo #endif /* _IDPF_OSDEP_H_ */
435