xref: /dpdk/drivers/common/idpf/base/idpf_controlq_api.h (revision fb4ac04e9bfa115da9cc425b892ebad23e811b10)
1*fb4ac04eSJunfeng Guo /* SPDX-License-Identifier: BSD-3-Clause
2*fb4ac04eSJunfeng Guo  * Copyright(c) 2001-2022 Intel Corporation
3*fb4ac04eSJunfeng Guo  */
4*fb4ac04eSJunfeng Guo 
5*fb4ac04eSJunfeng Guo #ifndef _IDPF_CONTROLQ_API_H_
6*fb4ac04eSJunfeng Guo #define _IDPF_CONTROLQ_API_H_
7*fb4ac04eSJunfeng Guo 
8*fb4ac04eSJunfeng Guo #ifdef __KERNEL__
9*fb4ac04eSJunfeng Guo #include "idpf_mem.h"
10*fb4ac04eSJunfeng Guo #else /* !__KERNEL__ */
11*fb4ac04eSJunfeng Guo #include "idpf_osdep.h"
12*fb4ac04eSJunfeng Guo #endif /* !__KERNEL__ */
13*fb4ac04eSJunfeng Guo 
14*fb4ac04eSJunfeng Guo struct idpf_hw;
15*fb4ac04eSJunfeng Guo 
16*fb4ac04eSJunfeng Guo /* Used for queue init, response and events */
17*fb4ac04eSJunfeng Guo enum idpf_ctlq_type {
18*fb4ac04eSJunfeng Guo 	IDPF_CTLQ_TYPE_MAILBOX_TX	= 0,
19*fb4ac04eSJunfeng Guo 	IDPF_CTLQ_TYPE_MAILBOX_RX	= 1,
20*fb4ac04eSJunfeng Guo 	IDPF_CTLQ_TYPE_CONFIG_TX	= 2,
21*fb4ac04eSJunfeng Guo 	IDPF_CTLQ_TYPE_CONFIG_RX	= 3,
22*fb4ac04eSJunfeng Guo 	IDPF_CTLQ_TYPE_EVENT_RX		= 4,
23*fb4ac04eSJunfeng Guo 	IDPF_CTLQ_TYPE_RDMA_TX		= 5,
24*fb4ac04eSJunfeng Guo 	IDPF_CTLQ_TYPE_RDMA_RX		= 6,
25*fb4ac04eSJunfeng Guo 	IDPF_CTLQ_TYPE_RDMA_COMPL	= 7
26*fb4ac04eSJunfeng Guo };
27*fb4ac04eSJunfeng Guo 
28*fb4ac04eSJunfeng Guo /*
29*fb4ac04eSJunfeng Guo  * Generic Control Queue Structures
30*fb4ac04eSJunfeng Guo  */
31*fb4ac04eSJunfeng Guo 
32*fb4ac04eSJunfeng Guo struct idpf_ctlq_reg {
33*fb4ac04eSJunfeng Guo 	/* used for queue tracking */
34*fb4ac04eSJunfeng Guo 	u32 head;
35*fb4ac04eSJunfeng Guo 	u32 tail;
36*fb4ac04eSJunfeng Guo 	/* Below applies only to default mb (if present) */
37*fb4ac04eSJunfeng Guo 	u32 len;
38*fb4ac04eSJunfeng Guo 	u32 bah;
39*fb4ac04eSJunfeng Guo 	u32 bal;
40*fb4ac04eSJunfeng Guo 	u32 len_mask;
41*fb4ac04eSJunfeng Guo 	u32 len_ena_mask;
42*fb4ac04eSJunfeng Guo 	u32 head_mask;
43*fb4ac04eSJunfeng Guo };
44*fb4ac04eSJunfeng Guo 
45*fb4ac04eSJunfeng Guo /* Generic queue msg structure */
46*fb4ac04eSJunfeng Guo struct idpf_ctlq_msg {
47*fb4ac04eSJunfeng Guo 	u8 vmvf_type; /* represents the source of the message on recv */
48*fb4ac04eSJunfeng Guo #define IDPF_VMVF_TYPE_VF 0
49*fb4ac04eSJunfeng Guo #define IDPF_VMVF_TYPE_VM 1
50*fb4ac04eSJunfeng Guo #define IDPF_VMVF_TYPE_PF 2
51*fb4ac04eSJunfeng Guo 	u8 host_id;
52*fb4ac04eSJunfeng Guo 	/* 3b field used only when sending a message to peer - to be used in
53*fb4ac04eSJunfeng Guo 	 * combination with target func_id to route the message
54*fb4ac04eSJunfeng Guo 	 */
55*fb4ac04eSJunfeng Guo #define IDPF_HOST_ID_MASK 0x7
56*fb4ac04eSJunfeng Guo 
57*fb4ac04eSJunfeng Guo 	u16 opcode;
58*fb4ac04eSJunfeng Guo 	u16 data_len;	/* data_len = 0 when no payload is attached */
59*fb4ac04eSJunfeng Guo 	union {
60*fb4ac04eSJunfeng Guo 		u16 func_id;	/* when sending a message */
61*fb4ac04eSJunfeng Guo 		u16 status;	/* when receiving a message */
62*fb4ac04eSJunfeng Guo 	};
63*fb4ac04eSJunfeng Guo 	union {
64*fb4ac04eSJunfeng Guo 		struct {
65*fb4ac04eSJunfeng Guo 			u32 chnl_retval;
66*fb4ac04eSJunfeng Guo 			u32 chnl_opcode;
67*fb4ac04eSJunfeng Guo 		} mbx;
68*fb4ac04eSJunfeng Guo 	} cookie;
69*fb4ac04eSJunfeng Guo 	union {
70*fb4ac04eSJunfeng Guo #define IDPF_DIRECT_CTX_SIZE	16
71*fb4ac04eSJunfeng Guo #define IDPF_INDIRECT_CTX_SIZE	8
72*fb4ac04eSJunfeng Guo 		/* 16 bytes of context can be provided or 8 bytes of context
73*fb4ac04eSJunfeng Guo 		 * plus the address of a DMA buffer
74*fb4ac04eSJunfeng Guo 		 */
75*fb4ac04eSJunfeng Guo 		u8 direct[IDPF_DIRECT_CTX_SIZE];
76*fb4ac04eSJunfeng Guo 		struct {
77*fb4ac04eSJunfeng Guo 			u8 context[IDPF_INDIRECT_CTX_SIZE];
78*fb4ac04eSJunfeng Guo 			struct idpf_dma_mem *payload;
79*fb4ac04eSJunfeng Guo 		} indirect;
80*fb4ac04eSJunfeng Guo 	} ctx;
81*fb4ac04eSJunfeng Guo };
82*fb4ac04eSJunfeng Guo 
83*fb4ac04eSJunfeng Guo /* Generic queue info structures */
84*fb4ac04eSJunfeng Guo /* MB, CONFIG and EVENT q do not have extended info */
85*fb4ac04eSJunfeng Guo struct idpf_ctlq_create_info {
86*fb4ac04eSJunfeng Guo 	enum idpf_ctlq_type type;
87*fb4ac04eSJunfeng Guo 	int id; /* absolute queue offset passed as input
88*fb4ac04eSJunfeng Guo 		 * -1 for default mailbox if present
89*fb4ac04eSJunfeng Guo 		 */
90*fb4ac04eSJunfeng Guo 	u16 len; /* Queue length passed as input */
91*fb4ac04eSJunfeng Guo 	u16 buf_size; /* buffer size passed as input */
92*fb4ac04eSJunfeng Guo 	u64 base_address; /* output, HPA of the Queue start  */
93*fb4ac04eSJunfeng Guo 	struct idpf_ctlq_reg reg; /* registers accessed by ctlqs */
94*fb4ac04eSJunfeng Guo 
95*fb4ac04eSJunfeng Guo 	int ext_info_size;
96*fb4ac04eSJunfeng Guo 	void *ext_info; /* Specific to q type */
97*fb4ac04eSJunfeng Guo };
98*fb4ac04eSJunfeng Guo 
99*fb4ac04eSJunfeng Guo /* Control Queue information */
100*fb4ac04eSJunfeng Guo struct idpf_ctlq_info {
101*fb4ac04eSJunfeng Guo 	LIST_ENTRY_TYPE(idpf_ctlq_info) cq_list;
102*fb4ac04eSJunfeng Guo 
103*fb4ac04eSJunfeng Guo 	enum idpf_ctlq_type cq_type;
104*fb4ac04eSJunfeng Guo 	int q_id;
105*fb4ac04eSJunfeng Guo 	idpf_lock cq_lock;		/* queue lock
106*fb4ac04eSJunfeng Guo 					 * idpf_lock is defined in OSdep.h
107*fb4ac04eSJunfeng Guo 					 */
108*fb4ac04eSJunfeng Guo 	/* used for interrupt processing */
109*fb4ac04eSJunfeng Guo 	u16 next_to_use;
110*fb4ac04eSJunfeng Guo 	u16 next_to_clean;
111*fb4ac04eSJunfeng Guo 	u16 next_to_post;		/* starting descriptor to post buffers
112*fb4ac04eSJunfeng Guo 					 * to after recev
113*fb4ac04eSJunfeng Guo 					 */
114*fb4ac04eSJunfeng Guo 
115*fb4ac04eSJunfeng Guo 	struct idpf_dma_mem desc_ring;	/* descriptor ring memory
116*fb4ac04eSJunfeng Guo 					 * idpf_dma_mem is defined in OSdep.h
117*fb4ac04eSJunfeng Guo 					 */
118*fb4ac04eSJunfeng Guo 	union {
119*fb4ac04eSJunfeng Guo 		struct idpf_dma_mem **rx_buff;
120*fb4ac04eSJunfeng Guo 		struct idpf_ctlq_msg **tx_msg;
121*fb4ac04eSJunfeng Guo 	} bi;
122*fb4ac04eSJunfeng Guo 
123*fb4ac04eSJunfeng Guo 	u16 buf_size;			/* queue buffer size */
124*fb4ac04eSJunfeng Guo 	u16 ring_size;			/* Number of descriptors */
125*fb4ac04eSJunfeng Guo 	struct idpf_ctlq_reg reg;	/* registers accessed by ctlqs */
126*fb4ac04eSJunfeng Guo };
127*fb4ac04eSJunfeng Guo 
128*fb4ac04eSJunfeng Guo /* PF/VF mailbox commands */
129*fb4ac04eSJunfeng Guo enum idpf_mbx_opc {
130*fb4ac04eSJunfeng Guo 	/* idpf_mbq_opc_send_msg_to_pf:
131*fb4ac04eSJunfeng Guo 	 *	usage: used by PF or VF to send a message to its CPF
132*fb4ac04eSJunfeng Guo 	 *	target: RX queue and function ID of parent PF taken from HW
133*fb4ac04eSJunfeng Guo 	 */
134*fb4ac04eSJunfeng Guo 	idpf_mbq_opc_send_msg_to_pf		= 0x0801,
135*fb4ac04eSJunfeng Guo 
136*fb4ac04eSJunfeng Guo 	/* idpf_mbq_opc_send_msg_to_vf:
137*fb4ac04eSJunfeng Guo 	 *	usage: used by PF to send message to a VF
138*fb4ac04eSJunfeng Guo 	 *	target: VF control queue ID must be specified in descriptor
139*fb4ac04eSJunfeng Guo 	 */
140*fb4ac04eSJunfeng Guo 	idpf_mbq_opc_send_msg_to_vf		= 0x0802,
141*fb4ac04eSJunfeng Guo 
142*fb4ac04eSJunfeng Guo 	/* idpf_mbq_opc_send_msg_to_peer_pf:
143*fb4ac04eSJunfeng Guo 	 *	usage: used by any function to send message to any peer PF
144*fb4ac04eSJunfeng Guo 	 *	target: RX queue and host of parent PF taken from HW
145*fb4ac04eSJunfeng Guo 	 */
146*fb4ac04eSJunfeng Guo 	idpf_mbq_opc_send_msg_to_peer_pf	= 0x0803,
147*fb4ac04eSJunfeng Guo 
148*fb4ac04eSJunfeng Guo 	/* idpf_mbq_opc_send_msg_to_peer_drv:
149*fb4ac04eSJunfeng Guo 	 *	usage: used by any function to send message to any peer driver
150*fb4ac04eSJunfeng Guo 	 *	target: RX queue and target host must be specific in descriptor
151*fb4ac04eSJunfeng Guo 	 */
152*fb4ac04eSJunfeng Guo 	idpf_mbq_opc_send_msg_to_peer_drv	= 0x0804,
153*fb4ac04eSJunfeng Guo };
154*fb4ac04eSJunfeng Guo 
155*fb4ac04eSJunfeng Guo /*
156*fb4ac04eSJunfeng Guo  * API supported for control queue management
157*fb4ac04eSJunfeng Guo  */
158*fb4ac04eSJunfeng Guo 
159*fb4ac04eSJunfeng Guo /* Will init all required q including default mb.  "q_info" is an array of
160*fb4ac04eSJunfeng Guo  * create_info structs equal to the number of control queues to be created.
161*fb4ac04eSJunfeng Guo  */
162*fb4ac04eSJunfeng Guo __rte_internal
163*fb4ac04eSJunfeng Guo int idpf_ctlq_init(struct idpf_hw *hw, u8 num_q,
164*fb4ac04eSJunfeng Guo 		   struct idpf_ctlq_create_info *q_info);
165*fb4ac04eSJunfeng Guo 
166*fb4ac04eSJunfeng Guo /* Allocate and initialize a single control queue, which will be added to the
167*fb4ac04eSJunfeng Guo  * control queue list; returns a handle to the created control queue
168*fb4ac04eSJunfeng Guo  */
169*fb4ac04eSJunfeng Guo int idpf_ctlq_add(struct idpf_hw *hw,
170*fb4ac04eSJunfeng Guo 		  struct idpf_ctlq_create_info *qinfo,
171*fb4ac04eSJunfeng Guo 		  struct idpf_ctlq_info **cq);
172*fb4ac04eSJunfeng Guo 
173*fb4ac04eSJunfeng Guo /* Deinitialize and deallocate a single control queue */
174*fb4ac04eSJunfeng Guo void idpf_ctlq_remove(struct idpf_hw *hw,
175*fb4ac04eSJunfeng Guo 		      struct idpf_ctlq_info *cq);
176*fb4ac04eSJunfeng Guo 
177*fb4ac04eSJunfeng Guo /* Sends messages to HW and will also free the buffer*/
178*fb4ac04eSJunfeng Guo __rte_internal
179*fb4ac04eSJunfeng Guo int idpf_ctlq_send(struct idpf_hw *hw,
180*fb4ac04eSJunfeng Guo 		   struct idpf_ctlq_info *cq,
181*fb4ac04eSJunfeng Guo 		   u16 num_q_msg,
182*fb4ac04eSJunfeng Guo 		   struct idpf_ctlq_msg q_msg[]);
183*fb4ac04eSJunfeng Guo 
184*fb4ac04eSJunfeng Guo /* Receives messages and called by interrupt handler/polling
185*fb4ac04eSJunfeng Guo  * initiated by app/process. Also caller is supposed to free the buffers
186*fb4ac04eSJunfeng Guo  */
187*fb4ac04eSJunfeng Guo __rte_internal
188*fb4ac04eSJunfeng Guo int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg,
189*fb4ac04eSJunfeng Guo 		   struct idpf_ctlq_msg *q_msg);
190*fb4ac04eSJunfeng Guo 
191*fb4ac04eSJunfeng Guo /* Reclaims send descriptors on HW write back */
192*fb4ac04eSJunfeng Guo __rte_internal
193*fb4ac04eSJunfeng Guo int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count,
194*fb4ac04eSJunfeng Guo 		       struct idpf_ctlq_msg *msg_status[]);
195*fb4ac04eSJunfeng Guo 
196*fb4ac04eSJunfeng Guo /* Indicate RX buffers are done being processed */
197*fb4ac04eSJunfeng Guo __rte_internal
198*fb4ac04eSJunfeng Guo int idpf_ctlq_post_rx_buffs(struct idpf_hw *hw,
199*fb4ac04eSJunfeng Guo 			    struct idpf_ctlq_info *cq,
200*fb4ac04eSJunfeng Guo 			    u16 *buff_count,
201*fb4ac04eSJunfeng Guo 			    struct idpf_dma_mem **buffs);
202*fb4ac04eSJunfeng Guo 
203*fb4ac04eSJunfeng Guo /* Will destroy all q including the default mb */
204*fb4ac04eSJunfeng Guo __rte_internal
205*fb4ac04eSJunfeng Guo int idpf_ctlq_deinit(struct idpf_hw *hw);
206*fb4ac04eSJunfeng Guo 
207*fb4ac04eSJunfeng Guo #endif /* _IDPF_CONTROLQ_API_H_ */
208