xref: /dpdk/drivers/common/cpt/cpt_mcode_defines.h (revision 99a2dd955fba6e4cc23b77d590a033650ced9c45)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2018 Cavium, Inc
3  */
4 
5 #ifndef _CPT_MCODE_DEFINES_H_
6 #define _CPT_MCODE_DEFINES_H_
7 
8 #include <rte_byteorder.h>
9 #include <rte_crypto_asym.h>
10 #include <rte_memory.h>
11 
12 /*
13  * This file defines macros and structures according to microcode spec
14  *
15  */
16 /* SE opcodes */
17 #define CPT_MAJOR_OP_FC		0x33
18 #define CPT_MAJOR_OP_HASH	0x34
19 #define CPT_MAJOR_OP_HMAC	0x35
20 #define CPT_MAJOR_OP_ZUC_SNOW3G	0x37
21 #define CPT_MAJOR_OP_KASUMI	0x38
22 #define CPT_MAJOR_OP_MISC	0x01
23 #define CPT_HMAC_FIRST_BIT_POS	0x4
24 #define CPT_FC_MINOR_OP_ENCRYPT	0x0
25 #define CPT_FC_MINOR_OP_DECRYPT	0x1
26 
27 /* AE opcodes */
28 #define CPT_MAJOR_OP_MODEX	0x03
29 #define CPT_MAJOR_OP_ECDSA	0x04
30 #define CPT_MAJOR_OP_ECC	0x05
31 #define CPT_MINOR_OP_MODEX	0x01
32 #define CPT_MINOR_OP_PKCS_ENC	0x02
33 #define CPT_MINOR_OP_PKCS_ENC_CRT	0x03
34 #define CPT_MINOR_OP_PKCS_DEC	0x04
35 #define CPT_MINOR_OP_PKCS_DEC_CRT	0x05
36 #define CPT_MINOR_OP_MODEX_CRT	0x06
37 #define CPT_MINOR_OP_ECDSA_SIGN	0x01
38 #define CPT_MINOR_OP_ECDSA_VERIFY	0x02
39 #define CPT_MINOR_OP_ECC_UMP	0x03
40 
41 #define CPT_BLOCK_TYPE1 0
42 #define CPT_BLOCK_TYPE2 1
43 
44 #define CPT_MAX_SG_IN_OUT_CNT	32
45 #define CPT_MAX_SG_CNT		(CPT_MAX_SG_IN_OUT_CNT/2)
46 
47 #define COMPLETION_CODE_SIZE	8
48 #define COMPLETION_CODE_INIT	0
49 
50 #define SG_LIST_HDR_SIZE	(8u)
51 #define SG_ENTRY_SIZE		sizeof(sg_comp_t)
52 
53 #define CPT_DMA_MODE		(1 << 7)
54 
55 #define CPT_FROM_CTX		0
56 #define CPT_FROM_DPTR		1
57 
58 #define FC_GEN			0x1
59 #define ZUC_SNOW3G		0x2
60 #define KASUMI			0x3
61 #define HASH_HMAC		0x4
62 
63 #define ZS_EA			0x1
64 #define ZS_IA			0x2
65 #define K_F8			0x4
66 #define K_F9			0x8
67 
68 #define CPT_OP_CIPHER_ENCRYPT	0x1
69 #define CPT_OP_CIPHER_DECRYPT	0x2
70 #define CPT_OP_CIPHER_MASK	0x3
71 
72 #define CPT_OP_AUTH_VERIFY	0x4
73 #define CPT_OP_AUTH_GENERATE	0x8
74 #define CPT_OP_AUTH_MASK	0xC
75 
76 #define CPT_OP_ENCODE	(CPT_OP_CIPHER_ENCRYPT | CPT_OP_AUTH_GENERATE)
77 #define CPT_OP_DECODE	(CPT_OP_CIPHER_DECRYPT | CPT_OP_AUTH_VERIFY)
78 
79 /* #define CPT_ALWAYS_USE_SG_MODE */
80 #define CPT_ALWAYS_USE_SEPARATE_BUF
81 
82 /*
83  * Parameters for Flexi Crypto
84  * requests
85  */
86 #define VALID_AAD_BUF 0x01
87 #define VALID_MAC_BUF 0x02
88 #define VALID_IV_BUF 0x04
89 #define SINGLE_BUF_INPLACE 0x08
90 #define SINGLE_BUF_HEADTAILROOM 0x10
91 
92 #define ENCR_IV_OFFSET(__d_offs) ((__d_offs >> 32) & 0xffff)
93 #define ENCR_OFFSET(__d_offs) ((__d_offs >> 16) & 0xffff)
94 #define AUTH_OFFSET(__d_offs) (__d_offs & 0xffff)
95 #define ENCR_DLEN(__d_lens) (__d_lens >> 32)
96 #define AUTH_DLEN(__d_lens) (__d_lens & 0xffffffff)
97 
98 /* FC offset_control at start of DPTR in bytes */
99 #define OFF_CTRL_LEN  8 /**< bytes */
100 
101 typedef enum {
102 	MD5_TYPE        = 1,
103 	SHA1_TYPE       = 2,
104 	SHA2_SHA224     = 3,
105 	SHA2_SHA256     = 4,
106 	SHA2_SHA384     = 5,
107 	SHA2_SHA512     = 6,
108 	GMAC_TYPE       = 7,
109 	POLY1305        = 8,
110 	SHA3_SHA224     = 10,
111 	SHA3_SHA256     = 11,
112 	SHA3_SHA384     = 12,
113 	SHA3_SHA512     = 13,
114 	SHA3_SHAKE256   = 14,
115 	SHA3_SHAKE512   = 15,
116 
117 	/* These are only for software use */
118 	ZUC_EIA3        = 0x90,
119 	SNOW3G_UIA2     = 0x91,
120 	KASUMI_F9_CBC   = 0x92,
121 	KASUMI_F9_ECB   = 0x93,
122 } mc_hash_type_t;
123 
124 typedef enum {
125 	/* To support passthrough */
126 	PASSTHROUGH  = 0x0,
127 	/*
128 	 * These are defined by MC for Flexi crypto
129 	 * for field of 4 bits
130 	 */
131 	DES3_CBC    = 0x1,
132 	DES3_ECB    = 0x2,
133 	AES_CBC     = 0x3,
134 	AES_ECB     = 0x4,
135 	AES_CFB     = 0x5,
136 	AES_CTR     = 0x6,
137 	AES_GCM     = 0x7,
138 	AES_XTS     = 0x8,
139 	CHACHA20    = 0x9,
140 
141 	/* These are only for software use */
142 	ZUC_EEA3        = 0x90,
143 	SNOW3G_UEA2     = 0x91,
144 	KASUMI_F8_CBC   = 0x92,
145 	KASUMI_F8_ECB   = 0x93,
146 } mc_cipher_type_t;
147 
148 typedef enum {
149 	AES_128_BIT = 0x1,
150 	AES_192_BIT = 0x2,
151 	AES_256_BIT = 0x3
152 } mc_aes_type_t;
153 
154 typedef enum {
155 	/* Microcode errors */
156 	NO_ERR = 0x00,
157 	ERR_OPCODE_UNSUPPORTED = 0x01,
158 
159 	/* SCATTER GATHER */
160 	ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,
161 	ERR_SCATTER_GATHER_LIST = 0x03,
162 	ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,
163 
164 	/* SE GC */
165 	ERR_GC_LENGTH_INVALID = 0x41,
166 	ERR_GC_RANDOM_LEN_INVALID = 0x42,
167 	ERR_GC_DATA_LEN_INVALID = 0x43,
168 	ERR_GC_DRBG_TYPE_INVALID = 0x44,
169 	ERR_GC_CTX_LEN_INVALID = 0x45,
170 	ERR_GC_CIPHER_UNSUPPORTED = 0x46,
171 	ERR_GC_AUTH_UNSUPPORTED = 0x47,
172 	ERR_GC_OFFSET_INVALID = 0x48,
173 	ERR_GC_HASH_MODE_UNSUPPORTED = 0x49,
174 	ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a,
175 	ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b,
176 	ERR_GC_ICV_MISCOMPARE = 0x4c,
177 	ERR_GC_DATA_UNALIGNED = 0x4d,
178 
179 	/* API Layer */
180 	ERR_BAD_ALT_CCODE = 0xfd,
181 	ERR_REQ_PENDING = 0xfe,
182 	ERR_REQ_TIMEOUT = 0xff,
183 
184 	ERR_BAD_INPUT_LENGTH = (0x40000000 | 384),    /* 0x40000180 */
185 	ERR_BAD_KEY_LENGTH,
186 	ERR_BAD_KEY_HANDLE,
187 	ERR_BAD_CONTEXT_HANDLE,
188 	ERR_BAD_SCALAR_LENGTH,
189 	ERR_BAD_DIGEST_LENGTH,
190 	ERR_BAD_INPUT_ARG,
191 	ERR_BAD_RECORD_PADDING,
192 	ERR_NB_REQUEST_PENDING,
193 	ERR_EIO,
194 	ERR_ENODEV,
195 } mc_error_code_t;
196 
197 /**
198  * Enumeration cpt_comp_e
199  *
200  * CPT Completion Enumeration
201  * Enumerates the values of CPT_RES_S[COMPCODE].
202  */
203 typedef enum {
204 	CPT_8X_COMP_E_NOTDONE    = (0x00),
205 	CPT_8X_COMP_E_GOOD       = (0x01),
206 	CPT_8X_COMP_E_FAULT      = (0x02),
207 	CPT_8X_COMP_E_SWERR      = (0x03),
208 	CPT_8X_COMP_E_HWERR      = (0x04),
209 	CPT_8X_COMP_E_LAST_ENTRY = (0xFF)
210 } cpt_comp_e_t;
211 
212 /**
213  * Enumeration cpt_ec_id
214  *
215  * Enumerates supported elliptic curves
216  */
217 typedef enum {
218 	CPT_EC_ID_P192 = 0,
219 	CPT_EC_ID_P224 = 1,
220 	CPT_EC_ID_P256 = 2,
221 	CPT_EC_ID_P384 = 3,
222 	CPT_EC_ID_P521 = 4,
223 	CPT_EC_ID_PMAX = 5
224 } cpt_ec_id_t;
225 
226 typedef struct sglist_comp {
227 	union {
228 		uint64_t len;
229 		struct {
230 			uint16_t len[4];
231 		} s;
232 	} u;
233 	uint64_t ptr[4];
234 } sg_comp_t;
235 
236 struct cpt_sess_misc {
237 	/** CPT opcode */
238 	uint16_t cpt_op:4;
239 	/** ZUC, SNOW3G &  KASUMI flags */
240 	uint16_t zsk_flag:4;
241 	/** Flag for AES GCM */
242 	uint16_t aes_gcm:1;
243 	/** Flag for AES CTR */
244 	uint16_t aes_ctr:1;
245 	/** Flag for CHACHA POLY */
246 	uint16_t chacha_poly:1;
247 	/** Flag for NULL cipher/auth */
248 	uint16_t is_null:1;
249 	/** Flag for GMAC */
250 	uint16_t is_gmac:1;
251 	/** Unused field */
252 	uint16_t rsvd1:3;
253 	/** AAD length */
254 	uint16_t aad_length;
255 	/** MAC len in bytes */
256 	uint8_t mac_len;
257 	/** IV length in bytes */
258 	uint8_t iv_length;
259 	/** Auth IV length in bytes */
260 	uint8_t auth_iv_length;
261 	/** Unused field */
262 	uint8_t rsvd2;
263 	/** IV offset in bytes */
264 	uint16_t iv_offset;
265 	/** Auth IV offset in bytes */
266 	uint16_t auth_iv_offset;
267 	/** Salt */
268 	uint32_t salt;
269 	/** CPT inst word 7 */
270 	uint64_t cpt_inst_w7;
271 	/** Context DMA address */
272 	phys_addr_t ctx_dma_addr;
273 };
274 
275 typedef struct {
276 	uint64_t iv_source      : 1;
277 	uint64_t aes_key        : 2;
278 	uint64_t rsvd_60        : 1;
279 	uint64_t enc_cipher     : 4;
280 	uint64_t auth_input_type : 1;
281 	uint64_t rsvd_52_54     : 3;
282 	uint64_t hash_type      : 4;
283 	uint64_t mac_len        : 8;
284 	uint64_t rsvd_39_0      : 40;
285 	uint8_t  encr_key[32];
286 	uint8_t  encr_iv[16];
287 } mc_enc_context_t;
288 
289 typedef struct {
290 	uint8_t  ipad[64];
291 	uint8_t  opad[64];
292 } mc_fc_hmac_context_t;
293 
294 typedef struct {
295 	mc_enc_context_t     enc;
296 	mc_fc_hmac_context_t hmac;
297 } mc_fc_context_t;
298 
299 typedef struct {
300 	uint8_t encr_auth_iv[16];
301 	uint8_t ci_key[16];
302 	uint8_t zuc_const[32];
303 } mc_zuc_snow3g_ctx_t;
304 
305 typedef struct {
306 	uint8_t reg_A[8];
307 	uint8_t ci_key[16];
308 } mc_kasumi_ctx_t;
309 
310 struct cpt_ctx {
311 	/* Below fields are accessed by sw */
312 	uint64_t enc_cipher	:8;
313 	uint64_t hash_type	:8;
314 	uint64_t mac_len	:8;
315 	uint64_t auth_key_len	:8;
316 	uint64_t fc_type	:4;
317 	uint64_t hmac		:1;
318 	uint64_t zsk_flags	:3;
319 	uint64_t k_ecb		:1;
320 	uint64_t auth_enc	:1;
321 	uint64_t dec_auth	:1;
322 	uint64_t snow3g		:2;
323 	uint64_t rsvd		:19;
324 	/* Below fields are accessed by hardware */
325 	union {
326 		mc_fc_context_t fctx;
327 		mc_zuc_snow3g_ctx_t zs_ctx;
328 		mc_kasumi_ctx_t k_ctx;
329 	} mc_ctx;
330 	uint8_t  auth_key[1024];
331 };
332 
333 /* Prime and order fields of built-in elliptic curves */
334 struct cpt_ec_group {
335 	struct {
336 		/* P521 maximum length */
337 		uint8_t data[66];
338 		unsigned int length;
339 	} prime;
340 
341 	struct {
342 		/* P521 maximum length */
343 		uint8_t data[66];
344 		unsigned int length;
345 	} order;
346 };
347 
348 struct cpt_asym_ec_ctx {
349 	/* Prime length defined by microcode for EC operations */
350 	uint8_t curveid;
351 };
352 
353 struct cpt_asym_sess_misc {
354 	enum rte_crypto_asym_xform_type xfrm_type;
355 	union {
356 		struct rte_crypto_rsa_xform rsa_ctx;
357 		struct rte_crypto_modex_xform mod_ctx;
358 		struct cpt_asym_ec_ctx ec_ctx;
359 	};
360 	uint64_t cpt_inst_w7;
361 };
362 
363 /* Buffer pointer */
364 typedef struct buf_ptr {
365 	void *vaddr;
366 	phys_addr_t dma_addr;
367 	uint32_t size;
368 	uint32_t resv;
369 } buf_ptr_t;
370 
371 /* IOV Pointer */
372 typedef struct{
373 	int buf_cnt;
374 	buf_ptr_t bufs[0];
375 } iov_ptr_t;
376 
377 typedef struct fc_params {
378 	/* 0th cache line */
379 	union {
380 		buf_ptr_t bufs[1];
381 		struct {
382 			iov_ptr_t *src_iov;
383 			iov_ptr_t *dst_iov;
384 		};
385 	};
386 	void *iv_buf;
387 	void *auth_iv_buf;
388 	buf_ptr_t meta_buf;
389 	buf_ptr_t ctx_buf;
390 	uint64_t rsvd2;
391 
392 	/* 1st cache line */
393 	buf_ptr_t aad_buf;
394 	buf_ptr_t mac_buf;
395 
396 } fc_params_t;
397 
398 /*
399  * Parameters for asymmetric operations
400  */
401 struct asym_op_params {
402 	struct cpt_request_info *req;
403 	phys_addr_t meta_buf;
404 };
405 
406 /*
407  * Parameters for digest
408  * generate requests
409  * Only src_iov, op, ctx_buf, mac_buf, prep_req
410  * meta_buf, auth_data_len are used for digest gen.
411  */
412 typedef struct fc_params digest_params_t;
413 
414 /* Cipher Algorithms */
415 typedef mc_cipher_type_t cipher_type_t;
416 
417 /* Auth Algorithms */
418 typedef mc_hash_type_t auth_type_t;
419 
420 /* Helper macros */
421 
422 #define SRC_IOV_SIZE \
423 	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
424 #define DST_IOV_SIZE \
425 	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
426 
427 #define SESS_PRIV(__sess) \
428 	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
429 
430 #define GET_SESS_FC_TYPE(__sess) \
431 	(((struct cpt_ctx *)(SESS_PRIV(__sess)))->fc_type)
432 
433 /*
434  * Get the session size
435  *
436  * @return
437  *   - session size
438  */
439 static __rte_always_inline unsigned int
440 cpt_get_session_size(void)
441 {
442 	unsigned int ctx_len = sizeof(struct cpt_ctx);
443 	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
444 }
445 #endif /* _CPT_MCODE_DEFINES_H_ */
446