xref: /dpdk/drivers/common/cpt/cpt_mcode_defines.h (revision 33bcaae5f85ad805ee287bee42013e61a1cff6fa)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2018 Cavium, Inc
3  */
4 
5 #ifndef _CPT_MCODE_DEFINES_H_
6 #define _CPT_MCODE_DEFINES_H_
7 
8 #include <rte_byteorder.h>
9 #include <rte_crypto_asym.h>
10 #include <rte_memory.h>
11 
12 /*
13  * This file defines macros and structures according to microcode spec
14  *
15  */
16 /* SE opcodes */
17 #define CPT_MAJOR_OP_FC		0x33
18 #define CPT_MAJOR_OP_HASH	0x34
19 #define CPT_MAJOR_OP_HMAC	0x35
20 #define CPT_MAJOR_OP_ZUC_SNOW3G	0x37
21 #define CPT_MAJOR_OP_KASUMI	0x38
22 #define CPT_MAJOR_OP_MISC	0x01
23 
24 #define CPT_BYTE_16		16
25 #define CPT_BYTE_24		24
26 #define CPT_BYTE_32		32
27 #define CPT_MAX_SG_IN_OUT_CNT	32
28 #define CPT_MAX_SG_CNT		(CPT_MAX_SG_IN_OUT_CNT/2)
29 
30 #define COMPLETION_CODE_SIZE	8
31 #define COMPLETION_CODE_INIT	0
32 
33 #define SG_LIST_HDR_SIZE	(8u)
34 #define SG_ENTRY_SIZE		sizeof(sg_comp_t)
35 
36 #define CPT_DMA_MODE		(1 << 7)
37 
38 #define CPT_FROM_CTX		0
39 #define CPT_FROM_DPTR		1
40 
41 #define FC_GEN			0x1
42 #define ZUC_SNOW3G		0x2
43 #define KASUMI			0x3
44 #define HASH_HMAC		0x4
45 
46 #define ZS_EA			0x1
47 #define ZS_IA			0x2
48 #define K_F8			0x4
49 #define K_F9			0x8
50 
51 #define CPT_OP_CIPHER_ENCRYPT	0x1
52 #define CPT_OP_CIPHER_DECRYPT	0x2
53 #define CPT_OP_CIPHER_MASK	0x3
54 
55 #define CPT_OP_AUTH_VERIFY	0x4
56 #define CPT_OP_AUTH_GENERATE	0x8
57 #define CPT_OP_AUTH_MASK	0xC
58 
59 #define CPT_OP_ENCODE	(CPT_OP_CIPHER_ENCRYPT | CPT_OP_AUTH_GENERATE)
60 #define CPT_OP_DECODE	(CPT_OP_CIPHER_DECRYPT | CPT_OP_AUTH_VERIFY)
61 
62 /* #define CPT_ALWAYS_USE_SG_MODE */
63 #define CPT_ALWAYS_USE_SEPARATE_BUF
64 
65 /*
66  * Parameters for Flexi Crypto
67  * requests
68  */
69 #define VALID_AAD_BUF 0x01
70 #define VALID_MAC_BUF 0x02
71 #define VALID_IV_BUF 0x04
72 #define SINGLE_BUF_INPLACE 0x08
73 #define SINGLE_BUF_HEADTAILROOM 0x10
74 
75 #define ENCR_IV_OFFSET(__d_offs) ((__d_offs >> 32) & 0xffff)
76 #define ENCR_OFFSET(__d_offs) ((__d_offs >> 16) & 0xffff)
77 #define AUTH_OFFSET(__d_offs) (__d_offs & 0xffff)
78 #define ENCR_DLEN(__d_lens) (__d_lens >> 32)
79 #define AUTH_DLEN(__d_lens) (__d_lens & 0xffffffff)
80 
81 /* FC offset_control at start of DPTR in bytes */
82 #define OFF_CTRL_LEN  8 /**< bytes */
83 
84 typedef enum {
85 	MD5_TYPE        = 1,
86 	SHA1_TYPE       = 2,
87 	SHA2_SHA224     = 3,
88 	SHA2_SHA256     = 4,
89 	SHA2_SHA384     = 5,
90 	SHA2_SHA512     = 6,
91 	GMAC_TYPE       = 7,
92 	XCBC_TYPE       = 8,
93 	SHA3_SHA224     = 10,
94 	SHA3_SHA256     = 11,
95 	SHA3_SHA384     = 12,
96 	SHA3_SHA512     = 13,
97 	SHA3_SHAKE256   = 14,
98 	SHA3_SHAKE512   = 15,
99 
100 	/* These are only for software use */
101 	ZUC_EIA3        = 0x90,
102 	SNOW3G_UIA2     = 0x91,
103 	KASUMI_F9_CBC   = 0x92,
104 	KASUMI_F9_ECB   = 0x93,
105 } mc_hash_type_t;
106 
107 typedef enum {
108 	/* To support passthrough */
109 	PASSTHROUGH  = 0x0,
110 	/*
111 	 * These are defined by MC for Flexi crypto
112 	 * for field of 4 bits
113 	 */
114 	DES3_CBC    = 0x1,
115 	DES3_ECB    = 0x2,
116 	AES_CBC     = 0x3,
117 	AES_ECB     = 0x4,
118 	AES_CFB     = 0x5,
119 	AES_CTR     = 0x6,
120 	AES_GCM     = 0x7,
121 	AES_XTS     = 0x8,
122 
123 	/* These are only for software use */
124 	ZUC_EEA3        = 0x90,
125 	SNOW3G_UEA2     = 0x91,
126 	KASUMI_F8_CBC   = 0x92,
127 	KASUMI_F8_ECB   = 0x93,
128 } mc_cipher_type_t;
129 
130 typedef enum {
131 	AES_128_BIT = 0x1,
132 	AES_192_BIT = 0x2,
133 	AES_256_BIT = 0x3
134 } mc_aes_type_t;
135 
136 typedef enum {
137 	/* Microcode errors */
138 	NO_ERR = 0x00,
139 	ERR_OPCODE_UNSUPPORTED = 0x01,
140 
141 	/* SCATTER GATHER */
142 	ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,
143 	ERR_SCATTER_GATHER_LIST = 0x03,
144 	ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,
145 
146 	/* SE GC */
147 	ERR_GC_LENGTH_INVALID = 0x41,
148 	ERR_GC_RANDOM_LEN_INVALID = 0x42,
149 	ERR_GC_DATA_LEN_INVALID = 0x43,
150 	ERR_GC_DRBG_TYPE_INVALID = 0x44,
151 	ERR_GC_CTX_LEN_INVALID = 0x45,
152 	ERR_GC_CIPHER_UNSUPPORTED = 0x46,
153 	ERR_GC_AUTH_UNSUPPORTED = 0x47,
154 	ERR_GC_OFFSET_INVALID = 0x48,
155 	ERR_GC_HASH_MODE_UNSUPPORTED = 0x49,
156 	ERR_GC_DRBG_ENTROPY_LEN_INVALID = 0x4a,
157 	ERR_GC_DRBG_ADDNL_LEN_INVALID = 0x4b,
158 	ERR_GC_ICV_MISCOMPARE = 0x4c,
159 	ERR_GC_DATA_UNALIGNED = 0x4d,
160 
161 	/* API Layer */
162 	ERR_BAD_ALT_CCODE = 0xfd,
163 	ERR_REQ_PENDING = 0xfe,
164 	ERR_REQ_TIMEOUT = 0xff,
165 
166 	ERR_BAD_INPUT_LENGTH = (0x40000000 | 384),    /* 0x40000180 */
167 	ERR_BAD_KEY_LENGTH,
168 	ERR_BAD_KEY_HANDLE,
169 	ERR_BAD_CONTEXT_HANDLE,
170 	ERR_BAD_SCALAR_LENGTH,
171 	ERR_BAD_DIGEST_LENGTH,
172 	ERR_BAD_INPUT_ARG,
173 	ERR_BAD_RECORD_PADDING,
174 	ERR_NB_REQUEST_PENDING,
175 	ERR_EIO,
176 	ERR_ENODEV,
177 } mc_error_code_t;
178 
179 /**
180  * Enumeration cpt_comp_e
181  *
182  * CPT Completion Enumeration
183  * Enumerates the values of CPT_RES_S[COMPCODE].
184  */
185 typedef enum {
186 	CPT_8X_COMP_E_NOTDONE    = (0x00),
187 	CPT_8X_COMP_E_GOOD       = (0x01),
188 	CPT_8X_COMP_E_FAULT      = (0x02),
189 	CPT_8X_COMP_E_SWERR      = (0x03),
190 	CPT_8X_COMP_E_HWERR      = (0x04),
191 	CPT_8X_COMP_E_LAST_ENTRY = (0xFF)
192 } cpt_comp_e_t;
193 
194 typedef struct sglist_comp {
195 	union {
196 		uint64_t len;
197 		struct {
198 			uint16_t len[4];
199 		} s;
200 	} u;
201 	uint64_t ptr[4];
202 } sg_comp_t;
203 
204 struct cpt_sess_misc {
205 	/** CPT opcode */
206 	uint16_t cpt_op:4;
207 	/** ZUC, SNOW3G &  KASUMI flags */
208 	uint16_t zsk_flag:4;
209 	/** Flag for AES GCM */
210 	uint16_t aes_gcm:1;
211 	/** Flag for AES CTR */
212 	uint16_t aes_ctr:1;
213 	/** Flag for NULL cipher/auth */
214 	uint16_t is_null:1;
215 	/** Flag for GMAC */
216 	uint16_t is_gmac:1;
217 	/** AAD length */
218 	uint16_t aad_length;
219 	/** MAC len in bytes */
220 	uint8_t mac_len;
221 	/** IV length in bytes */
222 	uint8_t iv_length;
223 	/** Auth IV length in bytes */
224 	uint8_t auth_iv_length;
225 	/** Reserved field */
226 	uint8_t rsvd1;
227 	/** IV offset in bytes */
228 	uint16_t iv_offset;
229 	/** Auth IV offset in bytes */
230 	uint16_t auth_iv_offset;
231 	/** Salt */
232 	uint32_t salt;
233 	/** Context DMA address */
234 	phys_addr_t ctx_dma_addr;
235 };
236 
237 typedef union {
238 	uint64_t flags;
239 	struct {
240 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
241 		uint64_t enc_cipher   : 4;
242 		uint64_t reserved1    : 1;
243 		uint64_t aes_key      : 2;
244 		uint64_t iv_source    : 1;
245 		uint64_t hash_type    : 4;
246 		uint64_t reserved2    : 3;
247 		uint64_t auth_input_type : 1;
248 		uint64_t mac_len      : 8;
249 		uint64_t reserved3    : 8;
250 		uint64_t encr_offset  : 16;
251 		uint64_t iv_offset    : 8;
252 		uint64_t auth_offset  : 8;
253 #else
254 		uint64_t auth_offset  : 8;
255 		uint64_t iv_offset    : 8;
256 		uint64_t encr_offset  : 16;
257 		uint64_t reserved3    : 8;
258 		uint64_t mac_len      : 8;
259 		uint64_t auth_input_type : 1;
260 		uint64_t reserved2    : 3;
261 		uint64_t hash_type    : 4;
262 		uint64_t iv_source    : 1;
263 		uint64_t aes_key      : 2;
264 		uint64_t reserved1    : 1;
265 		uint64_t enc_cipher   : 4;
266 #endif
267 	} e;
268 } encr_ctrl_t;
269 
270 typedef struct {
271 	encr_ctrl_t enc_ctrl;
272 	uint8_t  encr_key[32];
273 	uint8_t  encr_iv[16];
274 } mc_enc_context_t;
275 
276 typedef struct {
277 	uint8_t  ipad[64];
278 	uint8_t  opad[64];
279 } mc_fc_hmac_context_t;
280 
281 typedef struct {
282 	mc_enc_context_t     enc;
283 	mc_fc_hmac_context_t hmac;
284 } mc_fc_context_t;
285 
286 typedef struct {
287 	uint8_t encr_auth_iv[16];
288 	uint8_t ci_key[16];
289 	uint8_t zuc_const[32];
290 } mc_zuc_snow3g_ctx_t;
291 
292 typedef struct {
293 	uint8_t reg_A[8];
294 	uint8_t ci_key[16];
295 } mc_kasumi_ctx_t;
296 
297 struct cpt_ctx {
298 	/* Below fields are accessed by sw */
299 	uint64_t enc_cipher	:8;
300 	uint64_t hash_type	:8;
301 	uint64_t mac_len	:8;
302 	uint64_t auth_key_len	:8;
303 	uint64_t fc_type	:4;
304 	uint64_t hmac		:1;
305 	uint64_t zsk_flags	:3;
306 	uint64_t k_ecb		:1;
307 	uint64_t snow3g		:2;
308 	uint64_t rsvd		:21;
309 	/* Below fields are accessed by hardware */
310 	union {
311 		mc_fc_context_t fctx;
312 		mc_zuc_snow3g_ctx_t zs_ctx;
313 		mc_kasumi_ctx_t k_ctx;
314 	};
315 	uint8_t  auth_key[64];
316 };
317 
318 struct cpt_asym_sess_misc {
319 	enum rte_crypto_asym_xform_type xfrm_type;
320 	union {
321 		struct rte_crypto_rsa_xform rsa_ctx;
322 		struct rte_crypto_modex_xform mod_ctx;
323 	};
324 };
325 
326 /* Buffer pointer */
327 typedef struct buf_ptr {
328 	void *vaddr;
329 	phys_addr_t dma_addr;
330 	uint32_t size;
331 	uint32_t resv;
332 } buf_ptr_t;
333 
334 /* IOV Pointer */
335 typedef struct{
336 	int buf_cnt;
337 	buf_ptr_t bufs[0];
338 } iov_ptr_t;
339 
340 typedef union opcode_info {
341 	uint16_t flags;
342 	struct {
343 		uint8_t major;
344 		uint8_t minor;
345 	} s;
346 } opcode_info_t;
347 
348 typedef struct fc_params {
349 	/* 0th cache line */
350 	union {
351 		buf_ptr_t bufs[1];
352 		struct {
353 			iov_ptr_t *src_iov;
354 			iov_ptr_t *dst_iov;
355 		};
356 	};
357 	void *iv_buf;
358 	void *auth_iv_buf;
359 	buf_ptr_t meta_buf;
360 	buf_ptr_t ctx_buf;
361 	uint64_t rsvd2;
362 
363 	/* 1st cache line */
364 	buf_ptr_t aad_buf;
365 	buf_ptr_t mac_buf;
366 
367 } fc_params_t;
368 
369 /*
370  * Parameters for digest
371  * generate requests
372  * Only src_iov, op, ctx_buf, mac_buf, prep_req
373  * meta_buf, auth_data_len are used for digest gen.
374  */
375 typedef struct fc_params digest_params_t;
376 
377 /* Cipher Algorithms */
378 typedef mc_cipher_type_t cipher_type_t;
379 
380 /* Auth Algorithms */
381 typedef mc_hash_type_t auth_type_t;
382 
383 /* Helper macros */
384 
385 #define CPT_P_ENC_CTRL(fctx)  fctx->enc.enc_ctrl.e
386 
387 #define SRC_IOV_SIZE \
388 	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
389 #define DST_IOV_SIZE \
390 	(sizeof(iov_ptr_t) + (sizeof(buf_ptr_t) * CPT_MAX_SG_CNT))
391 
392 #define SESS_PRIV(__sess) \
393 	(void *)((uint8_t *)__sess + sizeof(struct cpt_sess_misc))
394 
395 /*
396  * Get the session size
397  *
398  * @return
399  *   - session size
400  */
401 static __rte_always_inline unsigned int
402 cpt_get_session_size(void)
403 {
404 	unsigned int ctx_len = sizeof(struct cpt_ctx);
405 	return (sizeof(struct cpt_sess_misc) + RTE_ALIGN_CEIL(ctx_len, 8));
406 }
407 #endif /* _CPT_MCODE_DEFINES_H_ */
408