xref: /dpdk/drivers/common/cnxk/roc_tim.h (revision f3c7b60769f997be0c49788d7bfc515c59910f83)
1796e3668SPavan Nikhilesh /* SPDX-License-Identifier: BSD-3-Clause
2796e3668SPavan Nikhilesh  * Copyright(C) 2021 Marvell.
3796e3668SPavan Nikhilesh  */
4796e3668SPavan Nikhilesh 
5796e3668SPavan Nikhilesh #ifndef _ROC_TIM_H_
6796e3668SPavan Nikhilesh #define _ROC_TIM_H_
7796e3668SPavan Nikhilesh 
8fdbec406SAnoob Joseph #include "roc_platform.h"
9fdbec406SAnoob Joseph 
10796e3668SPavan Nikhilesh enum roc_tim_clk_src {
11796e3668SPavan Nikhilesh 	ROC_TIM_CLK_SRC_10NS = 0,
12796e3668SPavan Nikhilesh 	ROC_TIM_CLK_SRC_GPIO,
13796e3668SPavan Nikhilesh 	ROC_TIM_CLK_SRC_GTI,
14796e3668SPavan Nikhilesh 	ROC_TIM_CLK_SRC_PTP,
15dcc97999SPavan Nikhilesh 	ROC_TIM_CLK_SRC_SYNCE,
16dcc97999SPavan Nikhilesh 	ROC_TIM_CLK_SRC_BTS,
1737a94462SPavan Nikhilesh 	ROC_TIM_CLK_SRC_EXT_MIO,
1837a94462SPavan Nikhilesh 	ROC_TIM_CLK_SRC_EXT_GTI,
19796e3668SPavan Nikhilesh 	ROC_TIM_CLK_SRC_INVALID,
20796e3668SPavan Nikhilesh };
21796e3668SPavan Nikhilesh 
22*f3c7b607SPavan Nikhilesh struct roc_tim_hwwqe_cfg {
23*f3c7b607SPavan Nikhilesh 	uint8_t grp_ena;
24*f3c7b607SPavan Nikhilesh 	uint8_t hwwqe_ena;
25*f3c7b607SPavan Nikhilesh 	uint8_t flw_ctrl_ena;
26*f3c7b607SPavan Nikhilesh 	uint16_t grp_tmo_cyc;
27*f3c7b607SPavan Nikhilesh 	uint16_t result_offset;
28*f3c7b607SPavan Nikhilesh 	uint16_t event_count_offset;
29*f3c7b607SPavan Nikhilesh };
30*f3c7b607SPavan Nikhilesh 
31796e3668SPavan Nikhilesh struct roc_tim {
32796e3668SPavan Nikhilesh 	struct roc_sso *roc_sso;
33796e3668SPavan Nikhilesh 	/* Public data. */
34796e3668SPavan Nikhilesh 	uint16_t nb_lfs;
35*f3c7b607SPavan Nikhilesh 	struct tim_feat_info feat;
36796e3668SPavan Nikhilesh 	/* Private data. */
37796e3668SPavan Nikhilesh #define TIM_MEM_SZ (1 * 1024)
38796e3668SPavan Nikhilesh 	uint8_t reserved[TIM_MEM_SZ] __plt_cache_aligned;
39796e3668SPavan Nikhilesh } __plt_cache_aligned;
40796e3668SPavan Nikhilesh 
41796e3668SPavan Nikhilesh int __roc_api roc_tim_init(struct roc_tim *roc_tim);
42796e3668SPavan Nikhilesh void __roc_api roc_tim_fini(struct roc_tim *roc_tim);
43796e3668SPavan Nikhilesh 
44796e3668SPavan Nikhilesh /* TIM config */
45796e3668SPavan Nikhilesh int __roc_api roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id,
46796e3668SPavan Nikhilesh 				uint64_t *start_tsc, uint32_t *cur_bkt);
47796e3668SPavan Nikhilesh int __roc_api roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id);
48796e3668SPavan Nikhilesh int __roc_api roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,
49*f3c7b607SPavan Nikhilesh 				enum roc_tim_clk_src clk_src, uint8_t ena_periodic, uint8_t ena_dfb,
50*f3c7b607SPavan Nikhilesh 				uint32_t bucket_sz, uint32_t chunk_sz, uint64_t interval,
51*f3c7b607SPavan Nikhilesh 				uint64_t intervalns, uint64_t clockfreq);
52*f3c7b607SPavan Nikhilesh int __roc_api roc_tim_lf_config_hwwqe(struct roc_tim *roc_tim, uint8_t ring_id,
53*f3c7b607SPavan Nikhilesh 				      struct roc_tim_hwwqe_cfg *cfg);
54dcc97999SPavan Nikhilesh int __roc_api roc_tim_lf_interval(struct roc_tim *roc_tim,
55dcc97999SPavan Nikhilesh 				  enum roc_tim_clk_src clk_src,
56dcc97999SPavan Nikhilesh 				  uint64_t clockfreq, uint64_t *intervalns,
57dcc97999SPavan Nikhilesh 				  uint64_t *interval);
58796e3668SPavan Nikhilesh int __roc_api roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id,
59796e3668SPavan Nikhilesh 			       uint64_t *clk);
60796e3668SPavan Nikhilesh int __roc_api roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id);
61796e3668SPavan Nikhilesh uintptr_t __roc_api roc_tim_lf_base_get(struct roc_tim *roc_tim,
62796e3668SPavan Nikhilesh 					uint8_t ring_id);
6337a94462SPavan Nikhilesh int roc_tim_capture_counters(struct roc_tim *roc_tim, uint64_t *counters, uint8_t nb_cntrs);
64796e3668SPavan Nikhilesh 
65796e3668SPavan Nikhilesh #endif
66