1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #include "roc_api.h" 6 #include "roc_priv.h" 7 8 #define nix_dump plt_dump 9 #define NIX_REG_INFO(reg) \ 10 { \ 11 reg, #reg \ 12 } 13 #define NIX_REG_NAME_SZ 48 14 15 #define nix_dump_no_nl plt_dump_no_nl 16 17 struct nix_lf_reg_info { 18 uint32_t offset; 19 const char *name; 20 }; 21 22 static const struct nix_lf_reg_info nix_lf_reg[] = { 23 NIX_REG_INFO(NIX_LF_RX_SECRETX(0)), 24 NIX_REG_INFO(NIX_LF_RX_SECRETX(1)), 25 NIX_REG_INFO(NIX_LF_RX_SECRETX(2)), 26 NIX_REG_INFO(NIX_LF_RX_SECRETX(3)), 27 NIX_REG_INFO(NIX_LF_RX_SECRETX(4)), 28 NIX_REG_INFO(NIX_LF_RX_SECRETX(5)), 29 NIX_REG_INFO(NIX_LF_CFG), 30 NIX_REG_INFO(NIX_LF_GINT), 31 NIX_REG_INFO(NIX_LF_GINT_W1S), 32 NIX_REG_INFO(NIX_LF_GINT_ENA_W1C), 33 NIX_REG_INFO(NIX_LF_GINT_ENA_W1S), 34 NIX_REG_INFO(NIX_LF_ERR_INT), 35 NIX_REG_INFO(NIX_LF_ERR_INT_W1S), 36 NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1C), 37 NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1S), 38 NIX_REG_INFO(NIX_LF_RAS), 39 NIX_REG_INFO(NIX_LF_RAS_W1S), 40 NIX_REG_INFO(NIX_LF_RAS_ENA_W1C), 41 NIX_REG_INFO(NIX_LF_RAS_ENA_W1S), 42 NIX_REG_INFO(NIX_LF_SQ_OP_ERR_DBG), 43 NIX_REG_INFO(NIX_LF_MNQ_ERR_DBG), 44 NIX_REG_INFO(NIX_LF_SEND_ERR_DBG), 45 }; 46 47 static void 48 nix_bitmap_dump(struct plt_bitmap *bmp) 49 { 50 uint32_t pos = 0, start_pos; 51 uint64_t slab = 0; 52 int i; 53 54 plt_bitmap_scan_init(bmp); 55 plt_bitmap_scan(bmp, &pos, &slab); 56 start_pos = pos; 57 58 nix_dump_no_nl(" \t\t["); 59 do { 60 if (!slab) 61 break; 62 i = 0; 63 64 for (i = 0; i < 64; i++) 65 if (slab & (1ULL << i)) 66 nix_dump_no_nl("%d, ", i); 67 68 if (!plt_bitmap_scan(bmp, &pos, &slab)) 69 break; 70 } while (start_pos != pos); 71 nix_dump_no_nl(" ]"); 72 } 73 74 int 75 roc_nix_lf_get_reg_count(struct roc_nix *roc_nix) 76 { 77 struct nix *nix = roc_nix_to_nix_priv(roc_nix); 78 int reg_count; 79 80 if (roc_nix == NULL) 81 return NIX_ERR_PARAM; 82 83 reg_count = PLT_DIM(nix_lf_reg); 84 /* NIX_LF_TX_STATX */ 85 reg_count += nix->lf_tx_stats; 86 /* NIX_LF_RX_STATX */ 87 reg_count += nix->lf_rx_stats; 88 /* NIX_LF_QINTX_CNT*/ 89 reg_count += nix->qints; 90 /* NIX_LF_QINTX_INT */ 91 reg_count += nix->qints; 92 /* NIX_LF_QINTX_ENA_W1S */ 93 reg_count += nix->qints; 94 /* NIX_LF_QINTX_ENA_W1C */ 95 reg_count += nix->qints; 96 /* NIX_LF_CINTX_CNT */ 97 reg_count += nix->cints; 98 /* NIX_LF_CINTX_WAIT */ 99 reg_count += nix->cints; 100 /* NIX_LF_CINTX_INT */ 101 reg_count += nix->cints; 102 /* NIX_LF_CINTX_INT_W1S */ 103 reg_count += nix->cints; 104 /* NIX_LF_CINTX_ENA_W1S */ 105 reg_count += nix->cints; 106 /* NIX_LF_CINTX_ENA_W1C */ 107 reg_count += nix->cints; 108 109 return reg_count; 110 } 111 112 int 113 nix_lf_gen_reg_dump(uintptr_t nix_lf_base, uint64_t *data) 114 { 115 bool dump_stdout; 116 uint64_t reg; 117 uint32_t i; 118 119 dump_stdout = data ? 0 : 1; 120 121 for (i = 0; i < PLT_DIM(nix_lf_reg); i++) { 122 reg = plt_read64(nix_lf_base + nix_lf_reg[i].offset); 123 if (dump_stdout && reg) 124 nix_dump("%32s = 0x%" PRIx64, nix_lf_reg[i].name, reg); 125 if (data) 126 *data++ = reg; 127 } 128 129 return i; 130 } 131 132 int 133 nix_lf_stat_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint8_t lf_tx_stats, 134 uint8_t lf_rx_stats) 135 { 136 uint32_t i, count = 0; 137 bool dump_stdout; 138 uint64_t reg; 139 140 dump_stdout = data ? 0 : 1; 141 142 /* NIX_LF_TX_STATX */ 143 for (i = 0; i < lf_tx_stats; i++) { 144 reg = plt_read64(nix_lf_base + NIX_LF_TX_STATX(i)); 145 if (dump_stdout && reg) 146 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_TX_STATX", i, 147 reg); 148 if (data) 149 *data++ = reg; 150 } 151 count += i; 152 153 /* NIX_LF_RX_STATX */ 154 for (i = 0; i < lf_rx_stats; i++) { 155 reg = plt_read64(nix_lf_base + NIX_LF_RX_STATX(i)); 156 if (dump_stdout && reg) 157 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_RX_STATX", i, 158 reg); 159 if (data) 160 *data++ = reg; 161 } 162 163 return count + i; 164 } 165 166 int 167 nix_lf_int_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint16_t qints, 168 uint16_t cints) 169 { 170 uint32_t i, count = 0; 171 bool dump_stdout; 172 uint64_t reg; 173 174 dump_stdout = data ? 0 : 1; 175 176 /* NIX_LF_QINTX_CNT*/ 177 for (i = 0; i < qints; i++) { 178 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_CNT(i)); 179 if (dump_stdout && reg) 180 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_CNT", i, 181 reg); 182 if (data) 183 *data++ = reg; 184 } 185 count += i; 186 187 /* NIX_LF_QINTX_INT */ 188 for (i = 0; i < qints; i++) { 189 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_INT(i)); 190 if (dump_stdout && reg) 191 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_INT", i, 192 reg); 193 if (data) 194 *data++ = reg; 195 } 196 count += i; 197 198 /* NIX_LF_QINTX_ENA_W1S */ 199 for (i = 0; i < qints; i++) { 200 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1S(i)); 201 if (dump_stdout && reg) 202 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_ENA_W1S", 203 i, reg); 204 if (data) 205 *data++ = reg; 206 } 207 count += i; 208 209 /* NIX_LF_QINTX_ENA_W1C */ 210 for (i = 0; i < qints; i++) { 211 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1C(i)); 212 if (dump_stdout && reg) 213 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_ENA_W1C", 214 i, reg); 215 if (data) 216 *data++ = reg; 217 } 218 count += i; 219 220 /* NIX_LF_CINTX_CNT */ 221 for (i = 0; i < cints; i++) { 222 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_CNT(i)); 223 if (dump_stdout && reg) 224 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_CNT", i, 225 reg); 226 if (data) 227 *data++ = reg; 228 } 229 count += i; 230 231 /* NIX_LF_CINTX_WAIT */ 232 for (i = 0; i < cints; i++) { 233 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_WAIT(i)); 234 if (dump_stdout && reg) 235 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_WAIT", i, 236 reg); 237 if (data) 238 *data++ = reg; 239 } 240 count += i; 241 242 /* NIX_LF_CINTX_INT */ 243 for (i = 0; i < cints; i++) { 244 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT(i)); 245 if (dump_stdout && reg) 246 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_INT", i, 247 reg); 248 if (data) 249 *data++ = reg; 250 } 251 count += i; 252 253 /* NIX_LF_CINTX_INT_W1S */ 254 for (i = 0; i < cints; i++) { 255 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT_W1S(i)); 256 if (dump_stdout && reg) 257 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_INT_W1S", 258 i, reg); 259 if (data) 260 *data++ = reg; 261 } 262 count += i; 263 264 /* NIX_LF_CINTX_ENA_W1S */ 265 for (i = 0; i < cints; i++) { 266 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1S(i)); 267 if (dump_stdout && reg) 268 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_ENA_W1S", 269 i, reg); 270 if (data) 271 *data++ = reg; 272 } 273 count += i; 274 275 /* NIX_LF_CINTX_ENA_W1C */ 276 for (i = 0; i < cints; i++) { 277 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1C(i)); 278 if (dump_stdout && reg) 279 nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_ENA_W1C", 280 i, reg); 281 if (data) 282 *data++ = reg; 283 } 284 285 return count + i; 286 } 287 288 int 289 roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data) 290 { 291 struct nix *nix = roc_nix_to_nix_priv(roc_nix); 292 bool dump_stdout = data ? 0 : 1; 293 uintptr_t nix_base; 294 uint32_t i; 295 296 if (roc_nix == NULL) 297 return NIX_ERR_PARAM; 298 299 nix_base = nix->base; 300 /* General registers */ 301 i = nix_lf_gen_reg_dump(nix_base, data); 302 303 /* Rx, Tx stat registers */ 304 i += nix_lf_stat_reg_dump(nix_base, dump_stdout ? NULL : &data[i], 305 nix->lf_tx_stats, nix->lf_rx_stats); 306 307 /* Intr registers */ 308 i += nix_lf_int_reg_dump(nix_base, dump_stdout ? NULL : &data[i], 309 nix->qints, nix->cints); 310 311 return 0; 312 } 313 314 int 315 nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p) 316 { 317 struct mbox *mbox = dev->mbox; 318 int rc; 319 320 if (roc_model_is_cn9k()) { 321 struct nix_aq_enq_rsp *rsp; 322 struct nix_aq_enq_req *aq; 323 int rc; 324 325 aq = mbox_alloc_msg_nix_aq_enq(mbox); 326 if (!aq) 327 return -ENOSPC; 328 329 aq->qidx = qid; 330 aq->ctype = ctype; 331 aq->op = NIX_AQ_INSTOP_READ; 332 333 rc = mbox_process_msg(mbox, (void *)&rsp); 334 if (rc) 335 return rc; 336 if (ctype == NIX_AQ_CTYPE_RQ) 337 *ctx_p = &rsp->rq; 338 else if (ctype == NIX_AQ_CTYPE_SQ) 339 *ctx_p = &rsp->sq; 340 else 341 *ctx_p = &rsp->cq; 342 } else { 343 struct nix_cn10k_aq_enq_rsp *rsp; 344 struct nix_cn10k_aq_enq_req *aq; 345 346 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox); 347 if (!aq) 348 return -ENOSPC; 349 350 aq->qidx = qid; 351 aq->ctype = ctype; 352 aq->op = NIX_AQ_INSTOP_READ; 353 354 rc = mbox_process_msg(mbox, (void *)&rsp); 355 if (rc) 356 return rc; 357 358 if (ctype == NIX_AQ_CTYPE_RQ) 359 *ctx_p = &rsp->rq; 360 else if (ctype == NIX_AQ_CTYPE_SQ) 361 *ctx_p = &rsp->sq; 362 else 363 *ctx_p = &rsp->cq; 364 } 365 return 0; 366 } 367 368 static inline void 369 nix_cn9k_lf_sq_dump(__io struct nix_sq_ctx_s *ctx, uint32_t *sqb_aura_p) 370 { 371 nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d", 372 ctx->sqe_way_mask, ctx->cq); 373 nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x", 374 ctx->sdp_mcast, ctx->substream); 375 nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n", ctx->qint_idx, 376 ctx->ena); 377 378 nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d", 379 ctx->sqb_count, ctx->default_chan); 380 nix_dump("W1: smq_rr_quantum \t\t%d\nW1: sso_ena \t\t\t%d", 381 ctx->smq_rr_quantum, ctx->sso_ena); 382 nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n", 383 ctx->xoff, ctx->cq_ena, ctx->smq); 384 385 nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d", 386 ctx->sqe_stype, ctx->sq_int_ena); 387 nix_dump("W2: sq_int \t\t\t%d\nW2: sqb_aura \t\t\t%d", ctx->sq_int, 388 ctx->sqb_aura); 389 nix_dump("W2: smq_rr_count \t\t%d\n", ctx->smq_rr_count); 390 391 nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d", 392 ctx->smq_next_sq_vld, ctx->smq_pend); 393 nix_dump("W3: smenq_next_sqb_vld \t%d\nW3: head_offset\t\t\t%d", 394 ctx->smenq_next_sqb_vld, ctx->head_offset); 395 nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d", 396 ctx->smenq_offset, ctx->tail_offset); 397 nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d", 398 ctx->smq_lso_segnum, ctx->smq_next_sq); 399 nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d", ctx->mnq_dis, 400 ctx->lmt_dis); 401 nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n", 402 ctx->cq_limit, ctx->max_sqe_size); 403 404 nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb); 405 nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb); 406 nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb); 407 nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb); 408 nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb); 409 410 nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d", 411 ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena); 412 nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d", 413 ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps); 414 nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d", 415 ctx->vfi_lso_sb, ctx->vfi_lso_sizem1); 416 nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total); 417 418 nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "", 419 (uint64_t)ctx->scm_lso_rem); 420 nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs); 421 nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts); 422 nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "", 423 (uint64_t)ctx->drop_octs); 424 nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "", 425 (uint64_t)ctx->drop_pkts); 426 427 *sqb_aura_p = ctx->sqb_aura; 428 } 429 430 static inline void 431 nix_lf_sq_dump(__io struct nix_cn10k_sq_ctx_s *ctx, uint32_t *sqb_aura_p) 432 { 433 nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d", 434 ctx->sqe_way_mask, ctx->cq); 435 nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x", 436 ctx->sdp_mcast, ctx->substream); 437 nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n", ctx->qint_idx, 438 ctx->ena); 439 440 nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d", 441 ctx->sqb_count, ctx->default_chan); 442 nix_dump("W1: smq_rr_weight \t\t%d\nW1: sso_ena \t\t\t%d", 443 ctx->smq_rr_weight, ctx->sso_ena); 444 nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n", 445 ctx->xoff, ctx->cq_ena, ctx->smq); 446 447 nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d", 448 ctx->sqe_stype, ctx->sq_int_ena); 449 nix_dump("W2: sq_int \t\t\t%d\nW2: sqb_aura \t\t\t%d", ctx->sq_int, 450 ctx->sqb_aura); 451 nix_dump("W2: smq_rr_count[ub:lb] \t\t%x:%x\n", ctx->smq_rr_count_ub, 452 ctx->smq_rr_count_lb); 453 454 nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d", 455 ctx->smq_next_sq_vld, ctx->smq_pend); 456 nix_dump("W3: smenq_next_sqb_vld \t%d\nW3: head_offset\t\t\t%d", 457 ctx->smenq_next_sqb_vld, ctx->head_offset); 458 nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d", 459 ctx->smenq_offset, ctx->tail_offset); 460 nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d", 461 ctx->smq_lso_segnum, ctx->smq_next_sq); 462 nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d", ctx->mnq_dis, 463 ctx->lmt_dis); 464 nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n", 465 ctx->cq_limit, ctx->max_sqe_size); 466 467 nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb); 468 nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb); 469 nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb); 470 nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb); 471 nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb); 472 473 nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d", 474 ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena); 475 nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d", 476 ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps); 477 nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d", 478 ctx->vfi_lso_sb, ctx->vfi_lso_sizem1); 479 nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total); 480 481 nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "", 482 (uint64_t)ctx->scm_lso_rem); 483 nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs); 484 nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts); 485 nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "", 486 (uint64_t)ctx->drop_octs); 487 nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "", 488 (uint64_t)ctx->drop_pkts); 489 490 *sqb_aura_p = ctx->sqb_aura; 491 } 492 493 static inline void 494 nix_cn9k_lf_rq_dump(__io struct nix_rq_ctx_s *ctx) 495 { 496 nix_dump("W0: wqe_aura \t\t\t%d\nW0: substream \t\t\t0x%03x", 497 ctx->wqe_aura, ctx->substream); 498 nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d", ctx->cq, 499 ctx->ena_wqwd); 500 nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d", 501 ctx->ipsech_ena, ctx->sso_ena); 502 nix_dump("W0: ena \t\t\t%d\n", ctx->ena); 503 504 nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d", 505 ctx->lpb_drop_ena, ctx->spb_drop_ena); 506 nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d", 507 ctx->xqe_drop_ena, ctx->wqe_caching); 508 nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d", 509 ctx->pb_caching, ctx->sso_tt); 510 nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d", ctx->sso_grp, 511 ctx->lpb_aura); 512 nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura); 513 514 nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d", 515 ctx->xqe_hdr_split, ctx->xqe_imm_copy); 516 nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d", 517 ctx->xqe_imm_size, ctx->later_skip); 518 nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d", 519 ctx->first_skip, ctx->lpb_sizem1); 520 nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d", ctx->spb_ena, 521 ctx->wqe_skip); 522 nix_dump("W2: spb_sizem1 \t\t\t%d\n", ctx->spb_sizem1); 523 524 nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d", 525 ctx->spb_pool_pass, ctx->spb_pool_drop); 526 nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d", 527 ctx->spb_aura_pass, ctx->spb_aura_drop); 528 nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d", 529 ctx->wqe_pool_pass, ctx->wqe_pool_drop); 530 nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n", 531 ctx->xqe_pass, ctx->xqe_drop); 532 533 nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d", 534 ctx->qint_idx, ctx->rq_int_ena); 535 nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d", ctx->rq_int, 536 ctx->lpb_pool_pass); 537 nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d", 538 ctx->lpb_pool_drop, ctx->lpb_aura_pass); 539 nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop); 540 541 nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d", 542 ctx->flow_tagw, ctx->bad_utag); 543 nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n", ctx->good_utag, 544 ctx->ltag); 545 546 nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs); 547 nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts); 548 nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs); 549 nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts); 550 nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts); 551 } 552 553 void 554 nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s *ctx) 555 { 556 nix_dump("W0: wqe_aura \t\t\t%d\nW0: len_ol3_dis \t\t\t%d", 557 ctx->wqe_aura, ctx->len_ol3_dis); 558 nix_dump("W0: len_ol4_dis \t\t\t%d\nW0: len_il3_dis \t\t\t%d", 559 ctx->len_ol4_dis, ctx->len_il3_dis); 560 nix_dump("W0: len_il4_dis \t\t\t%d\nW0: csum_ol4_dis \t\t\t%d", 561 ctx->len_il4_dis, ctx->csum_ol4_dis); 562 nix_dump("W0: csum_ol3_dis \t\t\t%d\nW0: lenerr_dis \t\t\t%d", 563 ctx->csum_ol4_dis, ctx->lenerr_dis); 564 nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d", ctx->cq, 565 ctx->ena_wqwd); 566 nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d", 567 ctx->ipsech_ena, ctx->sso_ena); 568 nix_dump("W0: ena \t\t\t%d\n", ctx->ena); 569 570 nix_dump("W1: chi_ena \t\t%d\nW1: ipsecd_drop_en \t\t%d", ctx->chi_ena, 571 ctx->ipsecd_drop_en); 572 nix_dump("W1: pb_stashing \t\t\t%d", ctx->pb_stashing); 573 nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d", 574 ctx->lpb_drop_ena, ctx->spb_drop_ena); 575 nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d", 576 ctx->xqe_drop_ena, ctx->wqe_caching); 577 nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d", 578 ctx->pb_caching, ctx->sso_tt); 579 nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d", ctx->sso_grp, 580 ctx->lpb_aura); 581 nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura); 582 583 nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d", 584 ctx->xqe_hdr_split, ctx->xqe_imm_copy); 585 nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d", 586 ctx->xqe_imm_size, ctx->later_skip); 587 nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d", 588 ctx->first_skip, ctx->lpb_sizem1); 589 nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d", ctx->spb_ena, 590 ctx->wqe_skip); 591 nix_dump("W2: spb_sizem1 \t\t\t%d\nW2: policer_ena \t\t\t%d", 592 ctx->spb_sizem1, ctx->policer_ena); 593 nix_dump("W2: band_prof_id \t\t\t%d", ctx->band_prof_id); 594 595 nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d", 596 ctx->spb_pool_pass, ctx->spb_pool_drop); 597 nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d", 598 ctx->spb_aura_pass, ctx->spb_aura_drop); 599 nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d", 600 ctx->wqe_pool_pass, ctx->wqe_pool_drop); 601 nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n", 602 ctx->xqe_pass, ctx->xqe_drop); 603 604 nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d", 605 ctx->qint_idx, ctx->rq_int_ena); 606 nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d", ctx->rq_int, 607 ctx->lpb_pool_pass); 608 nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d", 609 ctx->lpb_pool_drop, ctx->lpb_aura_pass); 610 nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop); 611 612 nix_dump("W5: vwqe_skip \t\t\t%d\nW5: max_vsize_exp \t\t\t%d", 613 ctx->vwqe_skip, ctx->max_vsize_exp); 614 nix_dump("W5: vtime_wait \t\t\t%d\nW5: vwqe_ena \t\t\t%d", 615 ctx->vtime_wait, ctx->max_vsize_exp); 616 nix_dump("W5: ipsec_vwqe \t\t\t%d", ctx->ipsec_vwqe); 617 nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d", 618 ctx->flow_tagw, ctx->bad_utag); 619 nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n", ctx->good_utag, 620 ctx->ltag); 621 622 nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs); 623 nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts); 624 nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs); 625 nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts); 626 nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts); 627 } 628 629 static inline void 630 nix_lf_cq_dump(__io struct nix_cq_ctx_s *ctx) 631 { 632 nix_dump("W0: base \t\t\t0x%" PRIx64 "\n", ctx->base); 633 634 nix_dump("W1: wrptr \t\t\t%" PRIx64 "", (uint64_t)ctx->wrptr); 635 nix_dump("W1: avg_con \t\t\t%d\nW1: cint_idx \t\t\t%d", ctx->avg_con, 636 ctx->cint_idx); 637 nix_dump("W1: cq_err \t\t\t%d\nW1: qint_idx \t\t\t%d", ctx->cq_err, 638 ctx->qint_idx); 639 nix_dump("W1: bpid \t\t\t%d\nW1: bp_ena \t\t\t%d\n", ctx->bpid, 640 ctx->bp_ena); 641 642 nix_dump("W2: update_time \t\t%d\nW2: avg_level \t\t\t%d", 643 ctx->update_time, ctx->avg_level); 644 nix_dump("W2: head \t\t\t%d\nW2: tail \t\t\t%d\n", ctx->head, 645 ctx->tail); 646 647 nix_dump("W3: cq_err_int_ena \t\t%d\nW3: cq_err_int \t\t\t%d", 648 ctx->cq_err_int_ena, ctx->cq_err_int); 649 nix_dump("W3: qsize \t\t\t%d\nW3: caching \t\t\t%d", ctx->qsize, 650 ctx->caching); 651 nix_dump("W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d", ctx->substream, 652 ctx->ena); 653 nix_dump("W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d", ctx->drop_ena, 654 ctx->drop); 655 nix_dump("W3: bp \t\t\t\t%d\n", ctx->bp); 656 } 657 658 int 659 roc_nix_queues_ctx_dump(struct roc_nix *roc_nix) 660 { 661 struct nix *nix = roc_nix_to_nix_priv(roc_nix); 662 int rc = -1, q, rq = nix->nb_rx_queues; 663 struct npa_aq_enq_rsp *npa_rsp; 664 struct npa_aq_enq_req *npa_aq; 665 struct dev *dev = &nix->dev; 666 int sq = nix->nb_tx_queues; 667 struct npa_lf *npa_lf; 668 volatile void *ctx; 669 uint32_t sqb_aura; 670 671 npa_lf = idev_npa_obj_get(); 672 if (npa_lf == NULL) 673 return NPA_ERR_DEVICE_NOT_BOUNDED; 674 675 for (q = 0; q < rq; q++) { 676 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_CQ, q, &ctx); 677 if (rc) { 678 plt_err("Failed to get cq context"); 679 goto fail; 680 } 681 nix_dump("============== port=%d cq=%d ===============", 682 roc_nix->port_id, q); 683 nix_lf_cq_dump(ctx); 684 } 685 686 for (q = 0; q < rq; q++) { 687 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, q, &ctx); 688 if (rc) { 689 plt_err("Failed to get rq context"); 690 goto fail; 691 } 692 nix_dump("============== port=%d rq=%d ===============", 693 roc_nix->port_id, q); 694 if (roc_model_is_cn9k()) 695 nix_cn9k_lf_rq_dump(ctx); 696 else 697 nix_lf_rq_dump(ctx); 698 } 699 700 for (q = 0; q < sq; q++) { 701 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_SQ, q, &ctx); 702 if (rc) { 703 plt_err("Failed to get sq context"); 704 goto fail; 705 } 706 nix_dump("============== port=%d sq=%d ===============", 707 roc_nix->port_id, q); 708 if (roc_model_is_cn9k()) 709 nix_cn9k_lf_sq_dump(ctx, &sqb_aura); 710 else 711 nix_lf_sq_dump(ctx, &sqb_aura); 712 713 if (!npa_lf) { 714 plt_err("NPA LF does not exist"); 715 continue; 716 } 717 718 /* Dump SQB Aura minimal info */ 719 npa_aq = mbox_alloc_msg_npa_aq_enq(npa_lf->mbox); 720 if (npa_aq == NULL) 721 return -ENOSPC; 722 npa_aq->aura_id = sqb_aura; 723 npa_aq->ctype = NPA_AQ_CTYPE_AURA; 724 npa_aq->op = NPA_AQ_INSTOP_READ; 725 726 rc = mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp); 727 if (rc) { 728 plt_err("Failed to get sq's sqb_aura context"); 729 continue; 730 } 731 732 nix_dump("\nSQB Aura W0: Pool addr\t\t0x%" PRIx64 "", 733 npa_rsp->aura.pool_addr); 734 nix_dump("SQB Aura W1: ena\t\t\t%d", npa_rsp->aura.ena); 735 nix_dump("SQB Aura W2: count\t\t%" PRIx64 "", 736 (uint64_t)npa_rsp->aura.count); 737 nix_dump("SQB Aura W3: limit\t\t%" PRIx64 "", 738 (uint64_t)npa_rsp->aura.limit); 739 nix_dump("SQB Aura W3: fc_ena\t\t%d", npa_rsp->aura.fc_ena); 740 nix_dump("SQB Aura W4: fc_addr\t\t0x%" PRIx64 "\n", 741 npa_rsp->aura.fc_addr); 742 } 743 744 fail: 745 return rc; 746 } 747 748 /* Dumps struct nix_cqe_hdr_s and union nix_rx_parse_u */ 749 void 750 roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq) 751 { 752 const union nix_rx_parse_u *rx = 753 (const union nix_rx_parse_u *)((const uint64_t *)cq + 1); 754 const uint64_t *sgs = (const uint64_t *)(rx + 1); 755 int i; 756 757 nix_dump("tag \t\t0x%x\tq \t\t%d\t\tnode \t\t%d\tcqe_type \t%d", 758 cq->tag, cq->q, cq->node, cq->cqe_type); 759 760 nix_dump("W0: chan \t0x%x\t\tdesc_sizem1 \t%d", rx->chan, 761 rx->desc_sizem1); 762 nix_dump("W0: imm_copy \t%d\t\texpress \t%d", rx->imm_copy, 763 rx->express); 764 nix_dump("W0: wqwd \t%d\t\terrlev \t\t%d\t\terrcode \t%d", rx->wqwd, 765 rx->errlev, rx->errcode); 766 nix_dump("W0: latype \t%d\t\tlbtype \t\t%d\t\tlctype \t\t%d", 767 rx->latype, rx->lbtype, rx->lctype); 768 nix_dump("W0: ldtype \t%d\t\tletype \t\t%d\t\tlftype \t\t%d", 769 rx->ldtype, rx->letype, rx->lftype); 770 nix_dump("W0: lgtype \t%d \t\tlhtype \t\t%d", rx->lgtype, rx->lhtype); 771 772 nix_dump("W1: pkt_lenm1 \t%d", rx->pkt_lenm1); 773 nix_dump("W1: l2m \t%d\t\tl2b \t\t%d\t\tl3m \t\t%d\tl3b \t\t%d", 774 rx->l2m, rx->l2b, rx->l3m, rx->l3b); 775 nix_dump("W1: vtag0_valid %d\t\tvtag0_gone \t%d", rx->vtag0_valid, 776 rx->vtag0_gone); 777 nix_dump("W1: vtag1_valid %d\t\tvtag1_gone \t%d", rx->vtag1_valid, 778 rx->vtag1_gone); 779 nix_dump("W1: pkind \t%d", rx->pkind); 780 nix_dump("W1: vtag0_tci \t%d\t\tvtag1_tci \t%d", rx->vtag0_tci, 781 rx->vtag1_tci); 782 783 nix_dump("W2: laflags \t%d\t\tlbflags\t\t%d\t\tlcflags \t%d", 784 rx->laflags, rx->lbflags, rx->lcflags); 785 nix_dump("W2: ldflags \t%d\t\tleflags\t\t%d\t\tlfflags \t%d", 786 rx->ldflags, rx->leflags, rx->lfflags); 787 nix_dump("W2: lgflags \t%d\t\tlhflags \t%d", rx->lgflags, rx->lhflags); 788 789 nix_dump("W3: eoh_ptr \t%d\t\twqe_aura \t%d\t\tpb_aura \t%d", 790 rx->eoh_ptr, rx->wqe_aura, rx->pb_aura); 791 nix_dump("W3: match_id \t%d", rx->match_id); 792 793 nix_dump("W4: laptr \t%d\t\tlbptr \t\t%d\t\tlcptr \t\t%d", rx->laptr, 794 rx->lbptr, rx->lcptr); 795 nix_dump("W4: ldptr \t%d\t\tleptr \t\t%d\t\tlfptr \t\t%d", rx->ldptr, 796 rx->leptr, rx->lfptr); 797 nix_dump("W4: lgptr \t%d\t\tlhptr \t\t%d", rx->lgptr, rx->lhptr); 798 799 nix_dump("W5: vtag0_ptr \t%d\t\tvtag1_ptr \t%d\t\tflow_key_alg \t%d", 800 rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg); 801 802 for (i = 0; i < (rx->desc_sizem1 + 1) << 1; i++) 803 nix_dump("sg[%u] = %p", i, (void *)sgs[i]); 804 } 805 806 void 807 roc_nix_rq_dump(struct roc_nix_rq *rq) 808 { 809 nix_dump("nix_rq@%p", rq); 810 nix_dump(" qid = %d", rq->qid); 811 nix_dump(" aura_handle = 0x%" PRIx64 "", rq->aura_handle); 812 nix_dump(" ipsec_ena = %d", rq->ipsech_ena); 813 nix_dump(" first_skip = %d", rq->first_skip); 814 nix_dump(" later_skip = %d", rq->later_skip); 815 nix_dump(" lpb_size = %d", rq->lpb_size); 816 nix_dump(" sso_ena = %d", rq->sso_ena); 817 nix_dump(" tag_mask = %d", rq->tag_mask); 818 nix_dump(" flow_tag_width = %d", rq->flow_tag_width); 819 nix_dump(" tt = %d", rq->tt); 820 nix_dump(" hwgrp = %d", rq->hwgrp); 821 nix_dump(" vwqe_ena = %d", rq->vwqe_ena); 822 nix_dump(" vwqe_first_skip = %d", rq->vwqe_first_skip); 823 nix_dump(" vwqe_max_sz_exp = %d", rq->vwqe_max_sz_exp); 824 nix_dump(" vwqe_wait_tmo = %ld", rq->vwqe_wait_tmo); 825 nix_dump(" vwqe_aura_handle = %ld", rq->vwqe_aura_handle); 826 nix_dump(" roc_nix = %p", rq->roc_nix); 827 nix_dump(" inl_dev_ref = %d", rq->inl_dev_ref); 828 } 829 830 void 831 roc_nix_cq_dump(struct roc_nix_cq *cq) 832 { 833 nix_dump("nix_cq@%p", cq); 834 nix_dump(" qid = %d", cq->qid); 835 nix_dump(" qnb_desc = %d", cq->nb_desc); 836 nix_dump(" roc_nix = %p", cq->roc_nix); 837 nix_dump(" door = 0x%" PRIx64 "", cq->door); 838 nix_dump(" status = %p", cq->status); 839 nix_dump(" wdata = 0x%" PRIx64 "", cq->wdata); 840 nix_dump(" desc_base = %p", cq->desc_base); 841 nix_dump(" qmask = 0x%" PRIx32 "", cq->qmask); 842 } 843 844 void 845 roc_nix_sq_dump(struct roc_nix_sq *sq) 846 { 847 nix_dump("nix_sq@%p", sq); 848 nix_dump(" qid = %d", sq->qid); 849 nix_dump(" max_sqe_sz = %d", sq->max_sqe_sz); 850 nix_dump(" nb_desc = %d", sq->nb_desc); 851 nix_dump(" sqes_per_sqb_log2 = %d", sq->sqes_per_sqb_log2); 852 nix_dump(" roc_nix= %p", sq->roc_nix); 853 nix_dump(" aura_handle = 0x%" PRIx64 "", sq->aura_handle); 854 nix_dump(" nb_sqb_bufs_adj = %d", sq->nb_sqb_bufs_adj); 855 nix_dump(" nb_sqb_bufs = %d", sq->nb_sqb_bufs); 856 nix_dump(" io_addr = 0x%" PRIx64 "", sq->io_addr); 857 nix_dump(" lmt_addr = %p", sq->lmt_addr); 858 nix_dump(" sqe_mem = %p", sq->sqe_mem); 859 nix_dump(" fc = %p", sq->fc); 860 }; 861 862 static uint8_t 863 nix_tm_reg_dump_prep(uint16_t hw_lvl, uint16_t schq, uint16_t link, 864 uint64_t *reg, char regstr[][NIX_REG_NAME_SZ]) 865 { 866 uint8_t k = 0; 867 868 switch (hw_lvl) { 869 case NIX_TXSCH_LVL_SMQ: 870 reg[k] = NIX_AF_SMQX_CFG(schq); 871 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_SMQ[%u]_CFG", 872 schq); 873 874 reg[k] = NIX_AF_MDQX_PARENT(schq); 875 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_PARENT", 876 schq); 877 878 reg[k] = NIX_AF_MDQX_SCHEDULE(schq); 879 snprintf(regstr[k++], NIX_REG_NAME_SZ, 880 "NIX_AF_MDQ[%u]_SCHEDULE", schq); 881 882 reg[k] = NIX_AF_MDQX_PIR(schq); 883 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_PIR", 884 schq); 885 886 reg[k] = NIX_AF_MDQX_CIR(schq); 887 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_CIR", 888 schq); 889 890 reg[k] = NIX_AF_MDQX_SHAPE(schq); 891 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_SHAPE", 892 schq); 893 894 reg[k] = NIX_AF_MDQX_SW_XOFF(schq); 895 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_SW_XOFF", 896 schq); 897 break; 898 case NIX_TXSCH_LVL_TL4: 899 reg[k] = NIX_AF_TL4X_PARENT(schq); 900 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_PARENT", 901 schq); 902 903 reg[k] = NIX_AF_TL4X_TOPOLOGY(schq); 904 snprintf(regstr[k++], NIX_REG_NAME_SZ, 905 "NIX_AF_TL4[%u]_TOPOLOGY", schq); 906 907 reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq); 908 snprintf(regstr[k++], NIX_REG_NAME_SZ, 909 "NIX_AF_TL4[%u]_SDP_LINK_CFG", schq); 910 911 reg[k] = NIX_AF_TL4X_SCHEDULE(schq); 912 snprintf(regstr[k++], NIX_REG_NAME_SZ, 913 "NIX_AF_TL4[%u]_SCHEDULE", schq); 914 915 reg[k] = NIX_AF_TL4X_PIR(schq); 916 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_PIR", 917 schq); 918 919 reg[k] = NIX_AF_TL4X_CIR(schq); 920 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_CIR", 921 schq); 922 923 reg[k] = NIX_AF_TL4X_SHAPE(schq); 924 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_SHAPE", 925 schq); 926 927 reg[k] = NIX_AF_TL4X_SW_XOFF(schq); 928 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_SW_XOFF", 929 schq); 930 break; 931 case NIX_TXSCH_LVL_TL3: 932 reg[k] = NIX_AF_TL3X_PARENT(schq); 933 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_PARENT", 934 schq); 935 936 reg[k] = NIX_AF_TL3X_TOPOLOGY(schq); 937 snprintf(regstr[k++], NIX_REG_NAME_SZ, 938 "NIX_AF_TL3[%u]_TOPOLOGY", schq); 939 940 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link); 941 snprintf(regstr[k++], NIX_REG_NAME_SZ, 942 "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link); 943 944 reg[k] = NIX_AF_TL3X_SCHEDULE(schq); 945 snprintf(regstr[k++], NIX_REG_NAME_SZ, 946 "NIX_AF_TL3[%u]_SCHEDULE", schq); 947 948 reg[k] = NIX_AF_TL3X_PIR(schq); 949 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_PIR", 950 schq); 951 952 reg[k] = NIX_AF_TL3X_CIR(schq); 953 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_CIR", 954 schq); 955 956 reg[k] = NIX_AF_TL3X_SHAPE(schq); 957 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_SHAPE", 958 schq); 959 960 reg[k] = NIX_AF_TL3X_SW_XOFF(schq); 961 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_SW_XOFF", 962 schq); 963 break; 964 case NIX_TXSCH_LVL_TL2: 965 reg[k] = NIX_AF_TL2X_PARENT(schq); 966 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_PARENT", 967 schq); 968 969 reg[k] = NIX_AF_TL2X_TOPOLOGY(schq); 970 snprintf(regstr[k++], NIX_REG_NAME_SZ, 971 "NIX_AF_TL2[%u]_TOPOLOGY", schq); 972 973 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link); 974 snprintf(regstr[k++], NIX_REG_NAME_SZ, 975 "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link); 976 977 reg[k] = NIX_AF_TL2X_SCHEDULE(schq); 978 snprintf(regstr[k++], NIX_REG_NAME_SZ, 979 "NIX_AF_TL2[%u]_SCHEDULE", schq); 980 981 reg[k] = NIX_AF_TL2X_PIR(schq); 982 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_PIR", 983 schq); 984 985 reg[k] = NIX_AF_TL2X_CIR(schq); 986 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_CIR", 987 schq); 988 989 reg[k] = NIX_AF_TL2X_SHAPE(schq); 990 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_SHAPE", 991 schq); 992 993 reg[k] = NIX_AF_TL2X_SW_XOFF(schq); 994 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_SW_XOFF", 995 schq); 996 break; 997 case NIX_TXSCH_LVL_TL1: 998 999 reg[k] = NIX_AF_TL1X_TOPOLOGY(schq); 1000 snprintf(regstr[k++], NIX_REG_NAME_SZ, 1001 "NIX_AF_TL1[%u]_TOPOLOGY", schq); 1002 1003 reg[k] = NIX_AF_TL1X_SCHEDULE(schq); 1004 snprintf(regstr[k++], NIX_REG_NAME_SZ, 1005 "NIX_AF_TL1[%u]_SCHEDULE", schq); 1006 1007 reg[k] = NIX_AF_TL1X_CIR(schq); 1008 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL1[%u]_CIR", 1009 schq); 1010 1011 reg[k] = NIX_AF_TL1X_SW_XOFF(schq); 1012 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL1[%u]_SW_XOFF", 1013 schq); 1014 1015 reg[k] = NIX_AF_TL1X_DROPPED_PACKETS(schq); 1016 snprintf(regstr[k++], NIX_REG_NAME_SZ, 1017 "NIX_AF_TL1[%u]_DROPPED_PACKETS", schq); 1018 break; 1019 default: 1020 break; 1021 } 1022 1023 if (k > MAX_REGS_PER_MBOX_MSG) { 1024 nix_dump("\t!!!NIX TM Registers request overflow!!!"); 1025 return 0; 1026 } 1027 return k; 1028 } 1029 1030 static void 1031 nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl) 1032 { 1033 char regstr[MAX_REGS_PER_MBOX_MSG * 2][NIX_REG_NAME_SZ]; 1034 uint64_t reg[MAX_REGS_PER_MBOX_MSG * 2]; 1035 struct mbox *mbox = (&nix->dev)->mbox; 1036 struct nix_txschq_config *req, *rsp; 1037 const char *lvlstr, *parent_lvlstr; 1038 struct nix_tm_node *node, *parent; 1039 struct nix_tm_node *root = NULL; 1040 uint32_t schq, parent_schq; 1041 bool found = false; 1042 uint8_t j, k, rc; 1043 1044 TAILQ_FOREACH(node, list, node) { 1045 if (node->hw_lvl != hw_lvl) 1046 continue; 1047 1048 found = true; 1049 parent = node->parent; 1050 if (hw_lvl == NIX_TXSCH_LVL_CNT) { 1051 lvlstr = "SQ"; 1052 schq = node->id; 1053 } else { 1054 lvlstr = nix_tm_hwlvl2str(node->hw_lvl); 1055 schq = node->hw_id; 1056 } 1057 1058 if (parent) { 1059 parent_schq = parent->hw_id; 1060 parent_lvlstr = nix_tm_hwlvl2str(parent->hw_lvl); 1061 } else if (node->hw_lvl == NIX_TXSCH_LVL_TL1) { 1062 parent_schq = nix->tx_link; 1063 parent_lvlstr = "LINK"; 1064 } else { 1065 parent_schq = node->parent_hw_id; 1066 parent_lvlstr = nix_tm_hwlvl2str(node->hw_lvl + 1); 1067 } 1068 1069 nix_dump("\t(%p%s) %s_%d->%s_%d", node, 1070 node->child_realloc ? "[CR]" : "", lvlstr, schq, 1071 parent_lvlstr, parent_schq); 1072 1073 if (!(node->flags & NIX_TM_NODE_HWRES)) 1074 continue; 1075 1076 /* Need to dump TL1 when root is TL2 */ 1077 if (node->hw_lvl == nix->tm_root_lvl) 1078 root = node; 1079 1080 /* Dump registers only when HWRES is present */ 1081 k = nix_tm_reg_dump_prep(node->hw_lvl, schq, nix->tx_link, reg, 1082 regstr); 1083 if (!k) 1084 continue; 1085 1086 req = mbox_alloc_msg_nix_txschq_cfg(mbox); 1087 req->read = 1; 1088 req->lvl = node->hw_lvl; 1089 req->num_regs = k; 1090 mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k); 1091 rc = mbox_process_msg(mbox, (void **)&rsp); 1092 if (!rc) { 1093 for (j = 0; j < k; j++) 1094 nix_dump("\t\t%s=0x%016" PRIx64, regstr[j], 1095 rsp->regval[j]); 1096 } else { 1097 nix_dump("\t!!!Failed to dump registers!!!"); 1098 } 1099 } 1100 1101 if (found) 1102 nix_dump("\n"); 1103 1104 /* Dump TL1 node data when root level is TL2 */ 1105 if (root && root->hw_lvl == NIX_TXSCH_LVL_TL2) { 1106 k = nix_tm_reg_dump_prep(NIX_TXSCH_LVL_TL1, root->parent_hw_id, 1107 nix->tx_link, reg, regstr); 1108 if (!k) 1109 return; 1110 1111 req = mbox_alloc_msg_nix_txschq_cfg(mbox); 1112 req->read = 1; 1113 req->lvl = NIX_TXSCH_LVL_TL1; 1114 req->num_regs = k; 1115 mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k); 1116 rc = mbox_process_msg(mbox, (void **)&rsp); 1117 if (!rc) { 1118 for (j = 0; j < k; j++) 1119 nix_dump("\t\t%s=0x%016" PRIx64, regstr[j], 1120 rsp->regval[j]); 1121 } else { 1122 nix_dump("\t!!!Failed to dump registers!!!"); 1123 } 1124 nix_dump("\n"); 1125 } 1126 } 1127 1128 void 1129 roc_nix_tm_dump(struct roc_nix *roc_nix) 1130 { 1131 struct nix *nix = roc_nix_to_nix_priv(roc_nix); 1132 struct dev *dev = &nix->dev; 1133 uint8_t hw_lvl, i; 1134 1135 nix_dump("===TM hierarchy and registers dump of %s (pf:vf) (%d:%d)===", 1136 nix->pci_dev->name, dev_get_pf(dev->pf_func), 1137 dev_get_vf(dev->pf_func)); 1138 1139 /* Dump all trees */ 1140 for (i = 0; i < ROC_NIX_TM_TREE_MAX; i++) { 1141 nix_dump("\tTM %s:", nix_tm_tree2str(i)); 1142 for (hw_lvl = 0; hw_lvl <= NIX_TXSCH_LVL_CNT; hw_lvl++) 1143 nix_tm_dump_lvl(nix, &nix->trees[i], hw_lvl); 1144 } 1145 1146 /* Dump unused resources */ 1147 nix_dump("\tTM unused resources:"); 1148 hw_lvl = NIX_TXSCH_LVL_SMQ; 1149 for (; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) { 1150 nix_dump("\t\ttxschq %7s num = %d", 1151 nix_tm_hwlvl2str(hw_lvl), 1152 nix_tm_resource_avail(nix, hw_lvl, false)); 1153 1154 nix_bitmap_dump(nix->schq_bmp[hw_lvl]); 1155 nix_dump("\n"); 1156 1157 nix_dump("\t\ttxschq_contig %7s num = %d", 1158 nix_tm_hwlvl2str(hw_lvl), 1159 nix_tm_resource_avail(nix, hw_lvl, true)); 1160 nix_bitmap_dump(nix->schq_contig_bmp[hw_lvl]); 1161 nix_dump("\n"); 1162 } 1163 } 1164 1165 void 1166 roc_nix_dump(struct roc_nix *roc_nix) 1167 { 1168 struct nix *nix = roc_nix_to_nix_priv(roc_nix); 1169 struct dev *dev = &nix->dev; 1170 int i; 1171 1172 nix_dump("nix@%p", nix); 1173 nix_dump(" pf = %d", dev_get_pf(dev->pf_func)); 1174 nix_dump(" vf = %d", dev_get_vf(dev->pf_func)); 1175 nix_dump(" bar2 = 0x%" PRIx64, dev->bar2); 1176 nix_dump(" bar4 = 0x%" PRIx64, dev->bar4); 1177 nix_dump(" port_id = %d", roc_nix->port_id); 1178 nix_dump(" rss_tag_as_xor = %d", roc_nix->rss_tag_as_xor); 1179 nix_dump(" rss_tag_as_xor = %d", roc_nix->max_sqb_count); 1180 nix_dump(" outb_nb_desc = %u", roc_nix->outb_nb_desc); 1181 1182 nix_dump(" \tpci_dev = %p", nix->pci_dev); 1183 nix_dump(" \tbase = 0x%" PRIxPTR "", nix->base); 1184 nix_dump(" \tlmt_base = 0x%" PRIxPTR "", nix->lmt_base); 1185 nix_dump(" \treta_size = %d", nix->reta_sz); 1186 nix_dump(" \ttx_chan_base = %d", nix->tx_chan_base); 1187 nix_dump(" \trx_chan_base = %d", nix->rx_chan_base); 1188 nix_dump(" \tnb_rx_queues = %d", nix->nb_rx_queues); 1189 nix_dump(" \tnb_tx_queues = %d", nix->nb_tx_queues); 1190 nix_dump(" \tlso_tsov6_idx = %d", nix->lso_tsov6_idx); 1191 nix_dump(" \tlso_tsov4_idx = %d", nix->lso_tsov4_idx); 1192 nix_dump(" \tlso_udp_tun_v4v4 = %d", 1193 nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V4]); 1194 nix_dump(" \tlso_udp_tun_v4v6 = %d", 1195 nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V6]); 1196 nix_dump(" \tlso_udp_tun_v6v4 = %d", 1197 nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V4]); 1198 nix_dump(" \tlso_udp_tun_v6v6 = %d", 1199 nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V6]); 1200 nix_dump(" \tlso_tun_v4v4 = %d", 1201 nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V4]); 1202 nix_dump(" \tlso_tun_v4v6 = %d", 1203 nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V6]); 1204 nix_dump(" \tlso_tun_v6v4 = %d", 1205 nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V4]); 1206 nix_dump(" \tlso_tun_v6v6 = %d", 1207 nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V6]); 1208 nix_dump(" \tlf_rx_stats = %d", nix->lf_rx_stats); 1209 nix_dump(" \tlf_tx_stats = %d", nix->lf_tx_stats); 1210 nix_dump(" \trx_chan_cnt = %d", nix->rx_chan_cnt); 1211 nix_dump(" \ttx_chan_cnt = %d", nix->tx_chan_cnt); 1212 nix_dump(" \tcgx_links = %d", nix->cgx_links); 1213 nix_dump(" \tlbk_links = %d", nix->lbk_links); 1214 nix_dump(" \tsdp_links = %d", nix->sdp_links); 1215 nix_dump(" \ttx_link = %d", nix->tx_link); 1216 nix_dump(" \tsqb_size = %d", nix->sqb_size); 1217 nix_dump(" \tmsixoff = %d", nix->msixoff); 1218 for (i = 0; i < nix->nb_cpt_lf; i++) 1219 nix_dump(" \tcpt_msixoff[%d] = %d", i, nix->cpt_msixoff[i]); 1220 nix_dump(" \tcints = %d", nix->cints); 1221 nix_dump(" \tqints = %d", nix->qints); 1222 nix_dump(" \tsdp_link = %d", nix->sdp_link); 1223 nix_dump(" \tptp_en = %d", nix->ptp_en); 1224 nix_dump(" \trss_alg_idx = %d", nix->rss_alg_idx); 1225 nix_dump(" \ttx_pause = %d", nix->tx_pause); 1226 nix_dump(" \tinl_inb_ena = %d", nix->inl_inb_ena); 1227 nix_dump(" \tinl_outb_ena = %d", nix->inl_outb_ena); 1228 nix_dump(" \tinb_sa_base = 0x%p", nix->inb_sa_base); 1229 nix_dump(" \tinb_sa_sz = %" PRIu64, nix->inb_sa_sz); 1230 nix_dump(" \toutb_sa_base = 0x%p", nix->outb_sa_base); 1231 nix_dump(" \toutb_sa_sz = %" PRIu64, nix->outb_sa_sz); 1232 nix_dump(" \toutb_err_sso_pffunc = 0x%x", nix->outb_err_sso_pffunc); 1233 nix_dump(" \tcpt_lf_base = 0x%p", nix->cpt_lf_base); 1234 nix_dump(" \tnb_cpt_lf = %d", nix->nb_cpt_lf); 1235 nix_dump(" \tinb_inl_dev = %d", nix->inb_inl_dev); 1236 } 1237 1238 void 1239 roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev) 1240 { 1241 struct nix_inl_dev *inl_dev = 1242 (struct nix_inl_dev *)&roc_inl_dev->reserved; 1243 struct dev *dev = &inl_dev->dev; 1244 1245 nix_dump("nix_inl_dev@%p", inl_dev); 1246 nix_dump(" pf = %d", dev_get_pf(dev->pf_func)); 1247 nix_dump(" vf = %d", dev_get_vf(dev->pf_func)); 1248 nix_dump(" bar2 = 0x%" PRIx64, dev->bar2); 1249 nix_dump(" bar4 = 0x%" PRIx64, dev->bar4); 1250 1251 nix_dump(" \tpci_dev = %p", inl_dev->pci_dev); 1252 nix_dump(" \tnix_base = 0x%" PRIxPTR "", inl_dev->nix_base); 1253 nix_dump(" \tsso_base = 0x%" PRIxPTR "", inl_dev->sso_base); 1254 nix_dump(" \tssow_base = 0x%" PRIxPTR "", inl_dev->ssow_base); 1255 nix_dump(" \tnix_msixoff = %d", inl_dev->nix_msixoff); 1256 nix_dump(" \tsso_msixoff = %d", inl_dev->sso_msixoff); 1257 nix_dump(" \tssow_msixoff = %d", inl_dev->ssow_msixoff); 1258 nix_dump(" \tnix_cints = %d", inl_dev->cints); 1259 nix_dump(" \tnix_qints = %d", inl_dev->qints); 1260 nix_dump(" \trq_refs = %d", inl_dev->rq_refs); 1261 nix_dump(" \tinb_sa_base = 0x%p", inl_dev->inb_sa_base); 1262 nix_dump(" \tinb_sa_sz = %d", inl_dev->inb_sa_sz); 1263 nix_dump(" \txaq_buf_size = %u", inl_dev->xaq_buf_size); 1264 nix_dump(" \txae_waes = %u", inl_dev->xae_waes); 1265 nix_dump(" \tiue = %u", inl_dev->iue); 1266 nix_dump(" \txaq_aura = 0x%" PRIx64, inl_dev->xaq.aura_handle); 1267 nix_dump(" \txaq_mem = 0x%p", inl_dev->xaq.mem); 1268 1269 nix_dump(" \tinl_dev_rq:"); 1270 roc_nix_rq_dump(&inl_dev->rq); 1271 } 1272