1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2021 Marvell. 3 */ 4 5 #ifndef __NIX_HW_H__ 6 #define __NIX_HW_H__ 7 8 /* Register offsets */ 9 10 #define NIX_AF_CFG (0x0ull) 11 #define NIX_AF_STATUS (0x10ull) 12 #define NIX_AF_NDC_CFG (0x18ull) 13 #define NIX_AF_CONST (0x20ull) 14 #define NIX_AF_CONST1 (0x28ull) 15 #define NIX_AF_CONST2 (0x30ull) 16 #define NIX_AF_CONST3 (0x38ull) 17 #define NIX_AF_SQ_CONST (0x40ull) 18 #define NIX_AF_CQ_CONST (0x48ull) 19 #define NIX_AF_RQ_CONST (0x50ull) 20 #define NIX_AF_PL_CONST (0x58ull) /* [CN10K, .) */ 21 #define NIX_AF_PSE_CONST (0x60ull) 22 #define NIX_AF_TL1_CONST (0x70ull) 23 #define NIX_AF_TL2_CONST (0x78ull) 24 #define NIX_AF_TL3_CONST (0x80ull) 25 #define NIX_AF_TL4_CONST (0x88ull) 26 #define NIX_AF_MDQ_CONST (0x90ull) 27 #define NIX_AF_MC_MIRROR_CONST (0x98ull) 28 #define NIX_AF_LSO_CFG (0xa8ull) 29 #define NIX_AF_BLK_RST (0xb0ull) 30 #define NIX_AF_TX_TSTMP_CFG (0xc0ull) 31 #define NIX_AF_PL_TS (0xc8ull) /* [CN10K, .) */ 32 #define NIX_AF_RX_CFG (0xd0ull) 33 #define NIX_AF_AVG_DELAY (0xe0ull) 34 #define NIX_AF_CINT_DELAY (0xf0ull) 35 #define NIX_AF_VWQE_TIMER (0xf8ull) /* [CN10K, .) */ 36 #define NIX_AF_RX_MCAST_BASE (0x100ull) 37 #define NIX_AF_RX_MCAST_CFG (0x110ull) 38 #define NIX_AF_RX_MCAST_BUF_BASE (0x120ull) 39 #define NIX_AF_RX_MCAST_BUF_CFG (0x130ull) 40 #define NIX_AF_RX_MIRROR_BUF_BASE (0x140ull) 41 #define NIX_AF_RX_MIRROR_BUF_CFG (0x148ull) 42 #define NIX_AF_LF_RST (0x150ull) 43 #define NIX_AF_GEN_INT (0x160ull) 44 #define NIX_AF_GEN_INT_W1S (0x168ull) 45 #define NIX_AF_GEN_INT_ENA_W1S (0x170ull) 46 #define NIX_AF_GEN_INT_ENA_W1C (0x178ull) 47 #define NIX_AF_ERR_INT (0x180ull) 48 #define NIX_AF_ERR_INT_W1S (0x188ull) 49 #define NIX_AF_ERR_INT_ENA_W1S (0x190ull) 50 #define NIX_AF_ERR_INT_ENA_W1C (0x198ull) 51 #define NIX_AF_RAS (0x1a0ull) 52 #define NIX_AF_RAS_W1S (0x1a8ull) 53 #define NIX_AF_RAS_ENA_W1S (0x1b0ull) 54 #define NIX_AF_RAS_ENA_W1C (0x1b8ull) 55 #define NIX_AF_RVU_INT (0x1c0ull) 56 #define NIX_AF_RVU_INT_W1S (0x1c8ull) 57 #define NIX_AF_RVU_INT_ENA_W1S (0x1d0ull) 58 #define NIX_AF_RVU_INT_ENA_W1C (0x1d8ull) 59 #define NIX_AF_TCP_TIMER (0x1e0ull) 60 /* [CN10k, .) */ 61 #define NIX_AF_RX_DEF_ETX(a) (0x1f0ull | (uint64_t)(a) << 3) 62 #define NIX_AF_RX_DEF_OL2 (0x200ull) 63 #define NIX_AF_RX_DEF_GEN0_COLOR (0x208ull) /* [CN10K, .) */ 64 #define NIX_AF_RX_DEF_OIP4 (0x210ull) 65 #define NIX_AF_RX_DEF_GEN1_COLOR (0x218ull) /* [CN10K, .) */ 66 #define NIX_AF_RX_DEF_IIP4 (0x220ull) 67 #define NIX_AF_RX_DEF_VLAN0_PCP_DEI (0x228ull) /* [CN10K, .) */ 68 #define NIX_AF_RX_DEF_OIP6 (0x230ull) 69 #define NIX_AF_RX_DEF_VLAN1_PCP_DEI (0x238ull) /* [CN10K, .) */ 70 #define NIX_AF_RX_DEF_IIP6 (0x240ull) 71 #define NIX_AF_RX_DEF_OTCP (0x250ull) 72 #define NIX_AF_RX_DEF_ITCP (0x260ull) 73 #define NIX_AF_RX_DEF_OUDP (0x270ull) 74 #define NIX_AF_RX_DEF_IUDP (0x280ull) 75 #define NIX_AF_RX_DEF_OSCTP (0x290ull) 76 #define NIX_AF_RX_DEF_CST_APAD_0 (0x298ull) /* [CN10K, .) */ 77 #define NIX_AF_RX_DEF_ISCTP (0x2a0ull) 78 #define NIX_AF_RX_DEF_CST_APAD_1 (0x2a8ull) /* [CN10K, .) */ 79 #define NIX_AF_RX_DEF_IPSECX(a) (0x2b0ull | (uint64_t)(a) << 3) 80 #define NIX_AF_RX_DEF_IIP4_DSCP (0x2e0ull) /* [CN10K, .) */ 81 #define NIX_AF_RX_DEF_OIP4_DSCP (0x2e8ull) /* [CN10K, .) */ 82 #define NIX_AF_RX_DEF_IIP6_DSCP (0x2f0ull) /* [CN10K, .) */ 83 #define NIX_AF_RX_DEF_OIP6_DSCP (0x2f8ull) /* [CN10K, .) */ 84 #define NIX_AF_RX_IPSEC_GEN_CFG (0x300ull) 85 #define NIX_AF_RX_IPSEC_VWQE_GEN_CFG (0x310ull) /* [CN10K, .) */ 86 #define NIX_AF_RX_CPTX_INST_QSEL(a) (0x320ull | (uint64_t)(a) << 3) 87 #define NIX_AF_RX_CPTX_CREDIT(a) (0x360ull | (uint64_t)(a) << 3) 88 #define NIX_AF_NDC_RX_SYNC (0x3e0ull) 89 #define NIX_AF_NDC_TX_SYNC (0x3f0ull) 90 #define NIX_AF_AQ_CFG (0x400ull) 91 #define NIX_AF_AQ_BASE (0x410ull) 92 #define NIX_AF_AQ_STATUS (0x420ull) 93 #define NIX_AF_AQ_DOOR (0x430ull) 94 #define NIX_AF_AQ_DONE_WAIT (0x440ull) 95 #define NIX_AF_AQ_DONE (0x450ull) 96 #define NIX_AF_AQ_DONE_ACK (0x460ull) 97 #define NIX_AF_AQ_DONE_TIMER (0x470ull) 98 #define NIX_AF_AQ_DONE_ENA_W1S (0x490ull) 99 #define NIX_AF_AQ_DONE_ENA_W1C (0x498ull) 100 #define NIX_AF_RX_LINKX_CFG(a) (0x540ull | (uint64_t)(a) << 16) 101 #define NIX_AF_RX_SW_SYNC (0x550ull) 102 #define NIX_AF_RX_LINKX_WRR_CFG(a) (0x560ull | (uint64_t)(a) << 16) 103 #define NIX_AF_SEB_CFG (0x5f0ull) /* [CN10K, .) */ 104 #define NIX_AF_EXPR_TX_FIFO_STATUS (0x640ull) /* [CN9K, CN10K) */ 105 #define NIX_AF_NORM_TX_FIFO_STATUS (0x648ull) 106 #define NIX_AF_SDP_TX_FIFO_STATUS (0x650ull) 107 #define NIX_AF_TX_NPC_CAPTURE_CONFIG (0x660ull) 108 #define NIX_AF_TX_NPC_CAPTURE_INFO (0x668ull) 109 #define NIX_AF_TX_NPC_CAPTURE_RESPX(a) (0x680ull | (uint64_t)(a) << 3) 110 #define NIX_AF_SEB_ACTIVE_CYCLES_PCX(a) (0x6c0ull | (uint64_t)(a) << 3) 111 #define NIX_AF_SMQX_CFG(a) (0x700ull | (uint64_t)(a) << 16) 112 #define NIX_AF_SMQX_HEAD(a) (0x710ull | (uint64_t)(a) << 16) 113 #define NIX_AF_SMQX_TAIL(a) (0x720ull | (uint64_t)(a) << 16) 114 #define NIX_AF_SMQX_STATUS(a) (0x730ull | (uint64_t)(a) << 16) 115 #define NIX_AF_SMQX_NXT_HEAD(a) (0x740ull | (uint64_t)(a) << 16) 116 #define NIX_AF_SQM_ACTIVE_CYCLES_PC (0x770ull) 117 #define NIX_AF_SQM_SCLK_CNT (0x780ull) /* [CN10K, .) */ 118 #define NIX_AF_DWRR_SDP_MTU (0x790ull) /* [CN10K, .) */ 119 #define NIX_AF_DWRR_RPM_MTU (0x7a0ull) /* [CN10K, .) */ 120 #define NIX_AF_PSE_CHANNEL_LEVEL (0x800ull) 121 #define NIX_AF_PSE_SHAPER_CFG (0x810ull) 122 #define NIX_AF_PSE_ACTIVE_CYCLES_PC (0x8c0ull) 123 #define NIX_AF_MARK_FORMATX_CTL(a) (0x900ull | (uint64_t)(a) << 18) 124 #define NIX_AF_TX_LINKX_NORM_CREDIT(a) (0xa00ull | (uint64_t)(a) << 16) 125 /* [CN9K, CN10K) */ 126 #define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xa10ull | (uint64_t)(a) << 16) 127 /* [CN9K, CN10K) */ 128 #define NIX_AF_TX_LINKX_SW_XOFF(a) (0xa20ull | (uint64_t)(a) << 16) 129 /* [CN10K, .) */ 130 #define NIX_AF_TX_LINKX_NORM_CDT_ADJ(a) (0xa20ull | (uint64_t)(a) << 16) 131 #define NIX_AF_TX_LINKX_HW_XOFF(a) (0xa30ull | (uint64_t)(a) << 16) 132 #define NIX_AF_SDP_LINK_CREDIT (0xa40ull) 133 #define NIX_AF_SDP_LINK_CDT_ADJ (0xa50ull) /* [CN10K, .) */ 134 /* [CN9K, CN10K) */ 135 #define NIX_AF_SDP_SW_XOFFX(a) (0xa60ull | (uint64_t)(a) << 3) 136 #define NIX_AF_SDP_HW_XOFFX(a) (0xac0ull | (uint64_t)(a) << 3) 137 #define NIX_AF_TL4X_BP_STATUS(a) (0xb00ull | (uint64_t)(a) << 16) 138 #define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xb10ull | (uint64_t)(a) << 16) 139 #define NIX_AF_TL1_TW_ARB_CTL_DEBUG (0xbc0ull) /* [CN10K, .) */ 140 #define NIX_AF_TL1_TW_ARB_REQ_DEBUG (0xbc8ull) /* [CN10K, .) */ 141 #define NIX_AF_TL1X_SCHEDULE(a) (0xc00ull | (uint64_t)(a) << 16) 142 #define NIX_AF_TL1X_SHAPE(a) (0xc10ull | (uint64_t)(a) << 16) 143 #define NIX_AF_TL1X_CIR(a) (0xc20ull | (uint64_t)(a) << 16) 144 /* [CN9K, CN10K) */ 145 #define NIX_AF_TL1X_SHAPE_STATE(a) (0xc50ull | (uint64_t)(a) << 16) 146 /* [CN10K, .) */ 147 #define NIX_AF_TL1X_SHAPE_STATE_CIR(a) (0xc50ull | (uint64_t)(a) << 16) 148 #define NIX_AF_TL1X_SW_XOFF(a) (0xc70ull | (uint64_t)(a) << 16) 149 #define NIX_AF_TL1X_TOPOLOGY(a) (0xc80ull | (uint64_t)(a) << 16) 150 #define NIX_AF_TL1X_MD_DEBUG0(a) (0xcc0ull | (uint64_t)(a) << 16) 151 #define NIX_AF_TL1X_MD_DEBUG1(a) (0xcc8ull | (uint64_t)(a) << 16) 152 /* [CN9K, CN10K) */ 153 #define NIX_AF_TL1X_MD_DEBUG2(a) (0xcd0ull | (uint64_t)(a) << 16) 154 /* [CN10K, .) */ 155 #define NIX_AF_TL2X_SHAPE_STATE_CIR(a) (0xcd0ull | (uint64_t)(a) << 16) 156 /* [CN9K, CN10K) */ 157 #define NIX_AF_TL1X_MD_DEBUG3(a) (0xcd8ull | (uint64_t)(a) << 16) 158 #define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xd20ull | (uint64_t)(a) << 16) 159 #define NIX_AF_TL1X_DROPPED_BYTES(a) (0xd30ull | (uint64_t)(a) << 16) 160 #define NIX_AF_TL1X_RED_PACKETS(a) (0xd40ull | (uint64_t)(a) << 16) 161 #define NIX_AF_TL1X_RED_BYTES(a) (0xd50ull | (uint64_t)(a) << 16) 162 #define NIX_AF_TL1X_YELLOW_PACKETS(a) (0xd60ull | (uint64_t)(a) << 16) 163 #define NIX_AF_TL1X_YELLOW_BYTES(a) (0xd70ull | (uint64_t)(a) << 16) 164 #define NIX_AF_TL1X_GREEN_PACKETS(a) (0xd80ull | (uint64_t)(a) << 16) 165 #define NIX_AF_TL1X_GREEN_BYTES(a) (0xd90ull | (uint64_t)(a) << 16) 166 #define NIX_AF_MDQ_MD_COUNT (0xda0ull) /* [CN10K, .) */ 167 /* [CN10K, .) */ 168 #define NIX_AF_MDQX_OUT_MD_COUNT(a) (0xdb0ull | (uint64_t)(a) << 16) 169 #define NIX_AF_TL2_TW_ARB_CTL_DEBUG (0xdc0ull) /* [CN10K, .) */ 170 /* [CN10K, .) */ 171 #define NIX_AF_TL2_TWX_ARB_REQ_DEBUG0(a) (0xdc8ull | (uint64_t)(a) << 16) 172 /* [CN10K, .) */ 173 #define NIX_AF_TL2_TWX_ARB_REQ_DEBUG1(a) (0xdd0ull | (uint64_t)(a) << 16) 174 #define NIX_AF_TL2X_SCHEDULE(a) (0xe00ull | (uint64_t)(a) << 16) 175 #define NIX_AF_TL2X_SHAPE(a) (0xe10ull | (uint64_t)(a) << 16) 176 #define NIX_AF_TL2X_CIR(a) (0xe20ull | (uint64_t)(a) << 16) 177 #define NIX_AF_TL2X_PIR(a) (0xe30ull | (uint64_t)(a) << 16) 178 #define NIX_AF_TL2X_SCHED_STATE(a) (0xe40ull | (uint64_t)(a) << 16) 179 /* [CN9K, CN10K) */ 180 #define NIX_AF_TL2X_SHAPE_STATE(a) (0xe50ull | (uint64_t)(a) << 16) 181 /* [CN10K, .) */ 182 #define NIX_AF_TL2X_SHAPE_STATE_PIR(a) (0xe50ull | (uint64_t)(a) << 16) 183 #define NIX_AF_TL2X_SW_XOFF(a) (0xe70ull | (uint64_t)(a) << 16) 184 #define NIX_AF_TL2X_TOPOLOGY(a) (0xe80ull | (uint64_t)(a) << 16) 185 #define NIX_AF_TL2X_PARENT(a) (0xe88ull | (uint64_t)(a) << 16) 186 #define NIX_AF_TL2X_MD_DEBUG0(a) (0xec0ull | (uint64_t)(a) << 16) 187 #define NIX_AF_TL2X_MD_DEBUG1(a) (0xec8ull | (uint64_t)(a) << 16) 188 /* [CN9K, CN10K) */ 189 #define NIX_AF_TL2X_MD_DEBUG2(a) (0xed0ull | (uint64_t)(a) << 16) 190 /* [CN10K, .) */ 191 #define NIX_AF_TL3X_SHAPE_STATE_CIR(a) (0xed0ull | (uint64_t)(a) << 16) 192 /* [CN9K, CN10K) */ 193 #define NIX_AF_TL2X_MD_DEBUG3(a) (0xed8ull | (uint64_t)(a) << 16) 194 #define NIX_AF_TL3_TW_ARB_CTL_DEBUG (0xfc0ull) /* [CN10K, .) */ 195 /* [CN10k, .) */ 196 #define NIX_AF_TL3_TWX_ARB_REQ_DEBUG0(a) (0xfc8ull | (uint64_t)(a) << 16) 197 /* [CN10K, .) */ 198 #define NIX_AF_TL3_TWX_ARB_REQ_DEBUG1(a) (0xfd0ull | (uint64_t)(a) << 16) 199 #define NIX_AF_TL3X_SCHEDULE(a) (0x1000ull | (uint64_t)(a) << 16) 200 #define NIX_AF_TL3X_SHAPE(a) (0x1010ull | (uint64_t)(a) << 16) 201 #define NIX_AF_TL3X_CIR(a) (0x1020ull | (uint64_t)(a) << 16) 202 #define NIX_AF_TL3X_PIR(a) (0x1030ull | (uint64_t)(a) << 16) 203 #define NIX_AF_TL3X_SCHED_STATE(a) (0x1040ull | (uint64_t)(a) << 16) 204 /* [CN9K, CN10K) */ 205 #define NIX_AF_TL3X_SHAPE_STATE(a) (0x1050ull | (uint64_t)(a) << 16) 206 /* [CN10K, .) */ 207 #define NIX_AF_TL3X_SHAPE_STATE_PIR(a) (0x1050ull | (uint64_t)(a) << 16) 208 #define NIX_AF_TL3X_SW_XOFF(a) (0x1070ull | (uint64_t)(a) << 16) 209 #define NIX_AF_TL3X_TOPOLOGY(a) (0x1080ull | (uint64_t)(a) << 16) 210 #define NIX_AF_TL3X_PARENT(a) (0x1088ull | (uint64_t)(a) << 16) 211 #define NIX_AF_TL3X_MD_DEBUG0(a) (0x10c0ull | (uint64_t)(a) << 16) 212 #define NIX_AF_TL3X_MD_DEBUG1(a) (0x10c8ull | (uint64_t)(a) << 16) 213 /* [CN9K, CN10K) */ 214 #define NIX_AF_TL3X_MD_DEBUG2(a) (0x10d0ull | (uint64_t)(a) << 16) 215 /* [CN10K, .) */ 216 #define NIX_AF_TL4X_SHAPE_STATE_CIR(a) (0x10d0ull | (uint64_t)(a) << 16) 217 /* [CN9K, CN10K) */ 218 #define NIX_AF_TL3X_MD_DEBUG3(a) (0x10d8ull | (uint64_t)(a) << 16) 219 #define NIX_AF_TL4_TW_ARB_CTL_DEBUG (0x11c0ull) /* [CN10K, .) */ 220 /* [CN10K, .) */ 221 #define NIX_AF_TL4_TWX_ARB_REQ_DEBUG0(a) (0x11c8ull | (uint64_t)(a) << 16) 222 /* [CN10K, .) */ 223 #define NIX_AF_TL4_TWX_ARB_REQ_DEBUG1(a) (0x11d0ull | (uint64_t)(a) << 16) 224 #define NIX_AF_TL4X_SCHEDULE(a) (0x1200ull | (uint64_t)(a) << 16) 225 #define NIX_AF_TL4X_SHAPE(a) (0x1210ull | (uint64_t)(a) << 16) 226 #define NIX_AF_TL4X_CIR(a) (0x1220ull | (uint64_t)(a) << 16) 227 #define NIX_AF_TL4X_PIR(a) (0x1230ull | (uint64_t)(a) << 16) 228 #define NIX_AF_TL4X_SCHED_STATE(a) (0x1240ull | (uint64_t)(a) << 16) 229 #define NIX_AF_TL4X_SHAPE_STATE(a) (0x1250ull | (uint64_t)(a) << 16) 230 #define NIX_AF_TL4X_SW_XOFF(a) (0x1270ull | (uint64_t)(a) << 16) 231 #define NIX_AF_TL4X_TOPOLOGY(a) (0x1280ull | (uint64_t)(a) << 16) 232 #define NIX_AF_TL4X_PARENT(a) (0x1288ull | (uint64_t)(a) << 16) 233 #define NIX_AF_TL4X_MD_DEBUG0(a) (0x12c0ull | (uint64_t)(a) << 16) 234 #define NIX_AF_TL4X_MD_DEBUG1(a) (0x12c8ull | (uint64_t)(a) << 16) 235 /* [CN9K, CN10K) */ 236 #define NIX_AF_TL4X_MD_DEBUG2(a) (0x12d0ull | (uint64_t)(a) << 16) 237 /* [CN10K, .) */ 238 #define NIX_AF_MDQX_SHAPE_STATE_CIR(a) (0x12d0ull | (uint64_t)(a) << 16) 239 /* [CN9K, CN10K) */ 240 #define NIX_AF_TL4X_MD_DEBUG3(a) (0x12d8ull | (uint64_t)(a) << 16) 241 #define NIX_AF_MDQ_TW_ARB_CTL_DEBUG (0x13c0ull) /* [CN10K, .) */ 242 /* [CN10K, .) */ 243 #define NIX_AF_MDQ_TWX_ARB_REQ_DEBUG0(a) (0x13c8ull | (uint64_t)(a) << 16) 244 /* [CN10K, .) */ 245 #define NIX_AF_MDQ_TWX_ARB_REQ_DEBUG1(a) (0x13d0ull | (uint64_t)(a) << 16) 246 #define NIX_AF_MDQX_SCHEDULE(a) (0x1400ull | (uint64_t)(a) << 16) 247 #define NIX_AF_MDQX_SHAPE(a) (0x1410ull | (uint64_t)(a) << 16) 248 #define NIX_AF_MDQX_CIR(a) (0x1420ull | (uint64_t)(a) << 16) 249 #define NIX_AF_MDQX_PIR(a) (0x1430ull | (uint64_t)(a) << 16) 250 #define NIX_AF_MDQX_SCHED_STATE(a) (0x1440ull | (uint64_t)(a) << 16) 251 /* [CN9K, CN10K) */ 252 #define NIX_AF_MDQX_SHAPE_STATE(a) (0x1450ull | (uint64_t)(a) << 16) 253 /* [CN10K, .) */ 254 #define NIX_AF_MDQX_SHAPE_STATE_PIR(a) (0x1450ull | (uint64_t)(a) << 16) 255 #define NIX_AF_MDQX_SW_XOFF(a) (0x1470ull | (uint64_t)(a) << 16) 256 #define NIX_AF_MDQX_PARENT(a) (0x1480ull | (uint64_t)(a) << 16) 257 #define NIX_AF_MDQX_MD_DEBUG(a) (0x14c0ull | (uint64_t)(a) << 16) 258 /* [CN10K, .) */ 259 #define NIX_AF_MDQX_IN_MD_COUNT(a) (0x14e0ull | (uint64_t)(a) << 16) 260 /* [CN9K, CN10K) */ 261 #define NIX_AF_TL3_TL2X_CFG(a) (0x1600ull | (uint64_t)(a) << 16) 262 #define NIX_AF_TL3_TL2X_BP_STATUS(a) (0x1610ull | (uint64_t)(a) << 16) 263 #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) \ 264 (0x1700ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) 265 #define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b) \ 266 (0x1800ull | (uint64_t)(a) << 18 | (uint64_t)(b) << 3) 267 #define NIX_AF_TX_MCASTX(a) (0x1900ull | (uint64_t)(a) << 15) 268 #define NIX_AF_TX_VTAG_DEFX_CTL(a) (0x1a00ull | (uint64_t)(a) << 16) 269 #define NIX_AF_TX_VTAG_DEFX_DATA(a) (0x1a10ull | (uint64_t)(a) << 16) 270 #define NIX_AF_RX_BPIDX_STATUS(a) (0x1a20ull | (uint64_t)(a) << 17) 271 #define NIX_AF_RX_CHANX_CFG(a) (0x1a30ull | (uint64_t)(a) << 15) 272 #define NIX_AF_CINT_TIMERX(a) (0x1a40ull | (uint64_t)(a) << 18) 273 #define NIX_AF_LSO_FORMATX_FIELDX(a, b) \ 274 (0x1b00ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3) 275 #define NIX_AF_LFX_CFG(a) (0x4000ull | (uint64_t)(a) << 17) 276 /* [CN10K, .) */ 277 #define NIX_AF_LINKX_CFG(a) (0x4010ull | (uint64_t)(a) << 17) 278 #define NIX_AF_LFX_SQS_CFG(a) (0x4020ull | (uint64_t)(a) << 17) 279 #define NIX_AF_LFX_TX_CFG2(a) (0x4028ull | (uint64_t)(a) << 17) 280 #define NIX_AF_LFX_SQS_BASE(a) (0x4030ull | (uint64_t)(a) << 17) 281 #define NIX_AF_LFX_RQS_CFG(a) (0x4040ull | (uint64_t)(a) << 17) 282 #define NIX_AF_LFX_RQS_BASE(a) (0x4050ull | (uint64_t)(a) << 17) 283 #define NIX_AF_LFX_CQS_CFG(a) (0x4060ull | (uint64_t)(a) << 17) 284 #define NIX_AF_LFX_CQS_BASE(a) (0x4070ull | (uint64_t)(a) << 17) 285 #define NIX_AF_LFX_TX_CFG(a) (0x4080ull | (uint64_t)(a) << 17) 286 #define NIX_AF_LFX_TX_PARSE_CFG(a) (0x4090ull | (uint64_t)(a) << 17) 287 #define NIX_AF_LFX_RX_CFG(a) (0x40a0ull | (uint64_t)(a) << 17) 288 #define NIX_AF_LFX_RSS_CFG(a) (0x40c0ull | (uint64_t)(a) << 17) 289 #define NIX_AF_LFX_RSS_BASE(a) (0x40d0ull | (uint64_t)(a) << 17) 290 #define NIX_AF_LFX_QINTS_CFG(a) (0x4100ull | (uint64_t)(a) << 17) 291 #define NIX_AF_LFX_QINTS_BASE(a) (0x4110ull | (uint64_t)(a) << 17) 292 #define NIX_AF_LFX_CINTS_CFG(a) (0x4120ull | (uint64_t)(a) << 17) 293 #define NIX_AF_LFX_CINTS_BASE(a) (0x4130ull | (uint64_t)(a) << 17) 294 #define NIX_AF_LFX_RX_IPSEC_CFG0(a) (0x4140ull | (uint64_t)(a) << 17) 295 #define NIX_AF_LFX_RX_IPSEC_CFG1(a) (0x4148ull | (uint64_t)(a) << 17) 296 #define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a) (0x4150ull | (uint64_t)(a) << 17) 297 #define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) (0x4158ull | (uint64_t)(a) << 17) 298 #define NIX_AF_LFX_RX_IPSEC_SA_BASE(a) (0x4170ull | (uint64_t)(a) << 17) 299 #define NIX_AF_LFX_TX_STATUS(a) (0x4180ull | (uint64_t)(a) << 17) 300 #define NIX_AF_LFX_RX_VTAG_TYPEX(a, b) \ 301 (0x4200ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3) 302 #define NIX_AF_LFX_LOCKX(a, b) \ 303 (0x4300ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3) 304 #define NIX_AF_LFX_TX_STATX(a, b) \ 305 (0x4400ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3) 306 #define NIX_AF_LFX_RX_STATX(a, b) \ 307 (0x4500ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3) 308 #define NIX_AF_LFX_RSS_GRPX(a, b) \ 309 (0x4600ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3) 310 #define NIX_AF_RX_NPC_MC_RCV (0x4700ull) 311 #define NIX_AF_RX_NPC_MC_DROP (0x4710ull) 312 #define NIX_AF_RX_NPC_MIRROR_RCV (0x4720ull) 313 #define NIX_AF_RX_NPC_MIRROR_DROP (0x4730ull) 314 /* [CN10K, .) */ 315 #define NIX_AF_LFX_VWQE_NORM_COMPL(a) (0x4740ull | (uint64_t)(a) << 17) 316 /* [CN10K, .) */ 317 #define NIX_AF_LFX_VWQE_RLS_TIMEOUT(a) (0x4750ull | (uint64_t)(a) << 17) 318 /* [CN10K, .) */ 319 #define NIX_AF_LFX_VWQE_HASH_FULL(a) (0x4760ull | (uint64_t)(a) << 17) 320 /* [CN10K, .) */ 321 #define NIX_AF_LFX_VWQE_SA_FULL(a) (0x4770ull | (uint64_t)(a) << 17) 322 #define NIX_AF_VWQE_HASH_FUNC_MASK (0x47a0ull) /* [CN10K, .) */ 323 #define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800ull | (uint64_t)(a) << 16) 324 /* [CN10K, .) */ 325 #define NIX_AF_RX_LINKX_WRR_OUT_CFG(a) (0x4a00ull | (uint64_t)(a) << 16) 326 #define NIX_PRIV_AF_INT_CFG (0x8000000ull) 327 #define NIX_PRIV_LFX_CFG(a) (0x8000010ull | (uint64_t)(a) << 8) 328 #define NIX_PRIV_LFX_INT_CFG(a) (0x8000020ull | (uint64_t)(a) << 8) 329 #define NIX_AF_RVU_LF_CFG_DEBUG (0x8000030ull) 330 331 #define NIX_LF_RX_SECRETX(a) (0x0ull | (uint64_t)(a) << 3) 332 #define NIX_LF_CFG (0x100ull) 333 #define NIX_LF_GINT (0x200ull) 334 #define NIX_LF_GINT_W1S (0x208ull) 335 #define NIX_LF_GINT_ENA_W1C (0x210ull) 336 #define NIX_LF_GINT_ENA_W1S (0x218ull) 337 #define NIX_LF_ERR_INT (0x220ull) 338 #define NIX_LF_ERR_INT_W1S (0x228ull) 339 #define NIX_LF_ERR_INT_ENA_W1C (0x230ull) 340 #define NIX_LF_ERR_INT_ENA_W1S (0x238ull) 341 #define NIX_LF_RAS (0x240ull) 342 #define NIX_LF_RAS_W1S (0x248ull) 343 #define NIX_LF_RAS_ENA_W1C (0x250ull) 344 #define NIX_LF_RAS_ENA_W1S (0x258ull) 345 #define NIX_LF_SQ_OP_ERR_DBG (0x260ull) 346 #define NIX_LF_MNQ_ERR_DBG (0x270ull) 347 #define NIX_LF_SEND_ERR_DBG (0x280ull) 348 #define NIX_LF_TX_STATX(a) (0x300ull | (uint64_t)(a) << 3) 349 #define NIX_LF_RX_STATX(a) (0x400ull | (uint64_t)(a) << 3) 350 #define NIX_LF_OP_SENDX(a) (0x800ull | (uint64_t)(a) << 3) 351 #define NIX_LF_RQ_OP_INT (0x900ull) 352 #define NIX_LF_RQ_OP_OCTS (0x910ull) 353 #define NIX_LF_RQ_OP_PKTS (0x920ull) 354 #define NIX_LF_RQ_OP_DROP_OCTS (0x930ull) 355 #define NIX_LF_RQ_OP_DROP_PKTS (0x940ull) 356 #define NIX_LF_RQ_OP_RE_PKTS (0x950ull) 357 #define NIX_LF_OP_IPSEC_DYNO_CNT (0x980ull) 358 #define NIX_LF_OP_VWQE_FLUSH (0x9a0ull) /* [CN10K, .) */ 359 #define NIX_LF_PL_OP_BAND_PROF (0x9c0ull) /* [CN10K, .) */ 360 #define NIX_LF_SQ_OP_INT (0xa00ull) 361 #define NIX_LF_SQ_OP_OCTS (0xa10ull) 362 #define NIX_LF_SQ_OP_PKTS (0xa20ull) 363 #define NIX_LF_SQ_OP_STATUS (0xa30ull) 364 #define NIX_LF_SQ_OP_DROP_OCTS (0xa40ull) 365 #define NIX_LF_SQ_OP_DROP_PKTS (0xa50ull) 366 #define NIX_LF_SQ_OP_AGE_DROP_OCTS (0xa60ull) /* [CN10K, .) */ 367 #define NIX_LF_SQ_OP_AGE_DROP_PKTS (0xa70ull) /* [CN10K, .) */ 368 #define NIX_LF_CQ_OP_INT (0xb00ull) 369 #define NIX_LF_CQ_OP_DOOR (0xb30ull) 370 #define NIX_LF_CQ_OP_STATUS (0xb40ull) 371 #define NIX_LF_QINTX_CNT(a) (0xc00ull | (uint64_t)(a) << 12) 372 #define NIX_LF_QINTX_INT(a) (0xc10ull | (uint64_t)(a) << 12) 373 #define NIX_LF_QINTX_ENA_W1S(a) (0xc20ull | (uint64_t)(a) << 12) 374 #define NIX_LF_QINTX_ENA_W1C(a) (0xc30ull | (uint64_t)(a) << 12) 375 #define NIX_LF_CINTX_CNT(a) (0xd00ull | (uint64_t)(a) << 12) 376 #define NIX_LF_CINTX_WAIT(a) (0xd10ull | (uint64_t)(a) << 12) 377 #define NIX_LF_CINTX_INT(a) (0xd20ull | (uint64_t)(a) << 12) 378 #define NIX_LF_CINTX_INT_W1S(a) (0xd30ull | (uint64_t)(a) << 12) 379 #define NIX_LF_CINTX_ENA_W1S(a) (0xd40ull | (uint64_t)(a) << 12) 380 #define NIX_LF_CINTX_ENA_W1C(a) (0xd50ull | (uint64_t)(a) << 12) 381 /* [CN10K, .) */ 382 #define NIX_LF_RX_GEN_COLOR_CONVX(a) (0x4740ull | (uint64_t)(a) << 3) 383 #define NIX_LF_RX_VLAN0_COLOR_CONV (0x4760ull) /* [CN10K, .) */ 384 #define NIX_LF_RX_VLAN1_COLOR_CONV (0x4768ull) /* [CN10K, .) */ 385 #define NIX_LF_RX_IIP_COLOR_CONV_LO (0x4770ull) /* [CN10K, .) */ 386 #define NIX_LF_RX_IIP_COLOR_CONV_HI (0x4778ull) /* [CN10K, .) */ 387 #define NIX_LF_RX_OIP_COLOR_CONV_LO (0x4780ull) /* [CN10K, .) */ 388 #define NIX_LF_RX_OIP_COLOR_CONV_HI (0x4788ull) /* [CN10K, .) */ 389 390 /* Enum offsets */ 391 392 #define NIX_STAT_LF_TX_TX_UCAST (0x0ull) 393 #define NIX_STAT_LF_TX_TX_BCAST (0x1ull) 394 #define NIX_STAT_LF_TX_TX_MCAST (0x2ull) 395 #define NIX_STAT_LF_TX_TX_DROP (0x3ull) 396 #define NIX_STAT_LF_TX_TX_OCTS (0x4ull) 397 398 #define NIX_STAT_LF_RX_RX_OCTS (0x0ull) 399 #define NIX_STAT_LF_RX_RX_UCAST (0x1ull) 400 #define NIX_STAT_LF_RX_RX_BCAST (0x2ull) 401 #define NIX_STAT_LF_RX_RX_MCAST (0x3ull) 402 #define NIX_STAT_LF_RX_RX_DROP (0x4ull) 403 #define NIX_STAT_LF_RX_RX_DROP_OCTS (0x5ull) 404 #define NIX_STAT_LF_RX_RX_FCS (0x6ull) 405 #define NIX_STAT_LF_RX_RX_ERR (0x7ull) 406 #define NIX_STAT_LF_RX_RX_DRP_BCAST (0x8ull) 407 #define NIX_STAT_LF_RX_RX_DRP_MCAST (0x9ull) 408 #define NIX_STAT_LF_RX_RX_DRP_L3BCAST (0xaull) 409 #define NIX_STAT_LF_RX_RX_DRP_L3MCAST (0xbull) 410 411 #define NIX_STAT_LF_RX_RX_GC_OCTS_PASSED (0xcull) /* [CN10K, .) */ 412 #define NIX_STAT_LF_RX_RX_GC_PKTS_PASSED (0xdull) /* [CN10K, .) */ 413 #define NIX_STAT_LF_RX_RX_YC_OCTS_PASSED (0xeull) /* [CN10K, .) */ 414 #define NIX_STAT_LF_RX_RX_YC_PKTS_PASSED (0xfull) /* [CN10K, .) */ 415 #define NIX_STAT_LF_RX_RX_RC_OCTS_PASSED (0x10ull) /* [CN10K, .) */ 416 #define NIX_STAT_LF_RX_RX_RC_PKTS_PASSED (0x11ull) /* [CN10K, .) */ 417 #define NIX_STAT_LF_RX_RX_GC_OCTS_DROP (0x12ull) /* [CN10K, .) */ 418 #define NIX_STAT_LF_RX_RX_GC_PKTS_DROP (0x13ull) /* [CN10K, .) */ 419 #define NIX_STAT_LF_RX_RX_YC_OCTS_DROP (0x14ull) /* [CN10K, .) */ 420 #define NIX_STAT_LF_RX_RX_YC_PKTS_DROP (0x15ull) /* [CN10K, .) */ 421 #define NIX_STAT_LF_RX_RX_RC_OCTS_DROP (0x16ull) /* [CN10K, .) */ 422 #define NIX_STAT_LF_RX_RX_RC_PKTS_DROP (0x17ull) /* [CN10K, .) */ 423 #define NIX_STAT_LF_RX_RX_CPT_DROP_PKTS (0x18ull) /* [CN10K, .) */ 424 #define NIX_STAT_LF_RX_RX_IPSECD_DROP_PKTS (0x19ull) /* [CN10K, .) */ 425 426 #define CGX_RX_PKT_CNT (0x0ull) /* [CN9K, CN10K) */ 427 #define CGX_RX_OCT_CNT (0x1ull) /* [CN9K, CN10K) */ 428 #define CGX_RX_PAUSE_PKT_CNT (0x2ull) /* [CN9K, CN10K) */ 429 #define CGX_RX_PAUSE_OCT_CNT (0x3ull) /* [CN9K, CN10K) */ 430 #define CGX_RX_DMAC_FILT_PKT_CNT (0x4ull) /* [CN9K, CN10K) */ 431 #define CGX_RX_DMAC_FILT_OCT_CNT (0x5ull) /* [CN9K, CN10K) */ 432 #define CGX_RX_FIFO_DROP_PKT_CNT (0x6ull) /* [CN9K, CN10K) */ 433 #define CGX_RX_FIFO_DROP_OCT_CNT (0x7ull) /* [CN9K, CN10K) */ 434 #define CGX_RX_ERR_CNT (0x8ull) /* [CN9K, CN10K) */ 435 436 #define CGX_TX_COLLISION_DROP (0x0ull) /* [CN9K, CN10K) */ 437 #define CGX_TX_FRAME_DEFER_CNT (0x1ull) /* [CN9K, CN10K) */ 438 #define CGX_TX_MULTIPLE_COLLISION (0x2ull) /* [CN9K, CN10K) */ 439 #define CGX_TX_SINGLE_COLLISION (0x3ull) /* [CN9K, CN10K) */ 440 #define CGX_TX_OCT_CNT (0x4ull) /* [CN9K, CN10K) */ 441 #define CGX_TX_PKT_CNT (0x5ull) /* [CN9K, CN10K) */ 442 #define CGX_TX_1_63_PKT_CNT (0x6ull) /* [CN9K, CN10K) */ 443 #define CGX_TX_64_PKT_CNT (0x7ull) /* [CN9K, CN10K) */ 444 #define CGX_TX_65_127_PKT_CNT (0x8ull) /* [CN9K, CN10K) */ 445 #define CGX_TX_128_255_PKT_CNT (0x9ull) /* [CN9K, CN10K) */ 446 #define CGX_TX_256_511_PKT_CNT (0xaull) /* [CN9K, CN10K) */ 447 #define CGX_TX_512_1023_PKT_CNT (0xbull) /* [CN9K, CN10K) */ 448 #define CGX_TX_1024_1518_PKT_CNT (0xcull) /* [CN9K, CN10K) */ 449 #define CGX_TX_1519_MAX_PKT_CNT (0xdull) /* [CN9K, CN10K) */ 450 #define CGX_TX_BCAST_PKTS (0xeull) /* [CN9K, CN10K) */ 451 #define CGX_TX_MCAST_PKTS (0xfull) /* [CN9K, CN10K) */ 452 #define CGX_TX_UFLOW_PKTS (0x10ull) /* [CN9K, CN10K) */ 453 #define CGX_TX_PAUSE_PKTS (0x11ull) /* [CN9K, CN10K) */ 454 455 #define RPM_MTI_STAT_RX_OCT_CNT (0x0ull) /* [CN10K, .) */ 456 #define RPM_MTI_STAT_RX_OCT_RECV_OK (0x1ull) /* [CN10K, .) */ 457 #define RPM_MTI_STAT_RX_ALIG_ERR (0x2ull) /* [CN10K, .) */ 458 #define RPM_MTI_STAT_RX_CTRL_FRM_RECV (0x3ull) /* [CN10K, .) */ 459 #define RPM_MTI_STAT_RX_FRM_LONG (0x4ull) /* [CN10K, .) */ 460 #define RPM_MTI_STAT_RX_LEN_ERR (0x5ull) /* [CN10K, .) */ 461 #define RPM_MTI_STAT_RX_FRM_RECV (0x6ull) /* [CN10K, .) */ 462 #define RPM_MTI_STAT_RX_FRM_SEQ_ERR (0x7ull) /* [CN10K, .) */ 463 #define RPM_MTI_STAT_RX_VLAN_OK (0x8ull) /* [CN10K, .) */ 464 #define RPM_MTI_STAT_RX_IN_ERR (0x9ull) /* [CN10K, .) */ 465 #define RPM_MTI_STAT_RX_IN_UCAST_PKT (0xaull) /* [CN10K, .) */ 466 #define RPM_MTI_STAT_RX_IN_MCAST_PKT (0xbull) /* [CN10K, .) */ 467 #define RPM_MTI_STAT_RX_IN_BCAST_PKT (0xcull) /* [CN10K, .) */ 468 #define RPM_MTI_STAT_RX_DRP_EVENTS (0xdull) /* [CN10K, .) */ 469 #define RPM_MTI_STAT_RX_PKT (0xeull) /* [CN10K, .) */ 470 #define RPM_MTI_STAT_RX_UNDER_SIZE (0xfull) /* [CN10K, .) */ 471 #define RPM_MTI_STAT_RX_1_64_PKT_CNT (0x10ull) /* [CN10K, .) */ 472 #define RPM_MTI_STAT_RX_65_127_PKT_CNT (0x11ull) /* [CN10K, .) */ 473 #define RPM_MTI_STAT_RX_128_255_PKT_CNT (0x12ull) /* [CN10K, .) */ 474 #define RPM_MTI_STAT_RX_256_511_PKT_CNT (0x13ull) /* [CN10K, .) */ 475 #define RPM_MTI_STAT_RX_512_1023_PKT_CNT (0x14ull) /* [CN10K, .) */ 476 #define RPM_MTI_STAT_RX_1024_1518_PKT_CNT (0x15ull) /* [CN10K, .) */ 477 #define RPM_MTI_STAT_RX_1519_MAX_PKT_CNT (0x16ull) /* [CN10K, .) */ 478 #define RPM_MTI_STAT_RX_OVER_SIZE (0x17ull) /* [CN10K, .) */ 479 #define RPM_MTI_STAT_RX_JABBER (0x18ull) /* [CN10K, .) */ 480 #define RPM_MTI_STAT_RX_ETH_FRAGS (0x19ull) /* [CN10K, .) */ 481 #define RPM_MTI_STAT_RX_CBFC_CLASS_0 (0x1aull) /* [CN10K, .) */ 482 #define RPM_MTI_STAT_RX_CBFC_CLASS_1 (0x1bull) /* [CN10K, .) */ 483 #define RPM_MTI_STAT_RX_CBFC_CLASS_2 (0x1cull) /* [CN10K, .) */ 484 #define RPM_MTI_STAT_RX_CBFC_CLASS_3 (0x1dull) /* [CN10K, .) */ 485 #define RPM_MTI_STAT_RX_CBFC_CLASS_4 (0x1eull) /* [CN10K, .) */ 486 #define RPM_MTI_STAT_RX_CBFC_CLASS_5 (0x1full) /* [CN10K, .) */ 487 #define RPM_MTI_STAT_RX_CBFC_CLASS_6 (0x20ull) /* [CN10K, .) */ 488 #define RPM_MTI_STAT_RX_CBFC_CLASS_7 (0x21ull) /* [CN10K, .) */ 489 #define RPM_MTI_STAT_RX_CBFC_CLASS_8 (0x22ull) /* [CN10K, .) */ 490 #define RPM_MTI_STAT_RX_CBFC_CLASS_9 (0x23ull) /* [CN10K, .) */ 491 #define RPM_MTI_STAT_RX_CBFC_CLASS_10 (0x24ull) /* [CN10K, .) */ 492 #define RPM_MTI_STAT_RX_CBFC_CLASS_11 (0x25ull) /* [CN10K, .) */ 493 #define RPM_MTI_STAT_RX_CBFC_CLASS_12 (0x26ull) /* [CN10K, .) */ 494 #define RPM_MTI_STAT_RX_CBFC_CLASS_13 (0x27ull) /* [CN10K, .) */ 495 #define RPM_MTI_STAT_RX_CBFC_CLASS_14 (0x28ull) /* [CN10K, .) */ 496 #define RPM_MTI_STAT_RX_CBFC_CLASS_15 (0x29ull) /* [CN10K, .) */ 497 #define RPM_MTI_STAT_RX_MAC_CONTROL (0x2aull) /* [CN10K, .) */ 498 499 #define RPM_MTI_STAT_TX_OCT_CNT (0x0ull) /* [CN10K, .) */ 500 #define RPM_MTI_STAT_TX_OCT_TX_OK (0x1ull) /* [CN10K, .) */ 501 #define RPM_MTI_STAT_TX_PAUSE_MAC_CTRL (0x2ull) /* [CN10K, .) */ 502 #define RPM_MTI_STAT_TX_FRAMES_OK (0x3ull) /* [CN10K, .) */ 503 #define RPM_MTI_STAT_TX_VLAN_OK (0x4ull) /* [CN10K, .) */ 504 #define RPM_MTI_STAT_TX_OUT_ERR (0x5ull) /* [CN10K, .) */ 505 #define RPM_MTI_STAT_TX_UCAST_PKT_CNT (0x6ull) /* [CN10K, .) */ 506 #define RPM_MTI_STAT_TX_MCAST_PKT_CNT (0x7ull) /* [CN10K, .) */ 507 #define RPM_MTI_STAT_TX_BCAST_PKT_CNT (0x8ull) /* [CN10K, .) */ 508 #define RPM_MTI_STAT_TX_1_64_PKT_CNT (0x9ull) /* [CN10K, .) */ 509 #define RPM_MTI_STAT_TX_65_127_PKT_CNT (0xaull) /* [CN10K, .) */ 510 #define RPM_MTI_STAT_TX_128_255_PKT_CNT (0xbull) /* [CN10K, .) */ 511 #define RPM_MTI_STAT_TX_256_511_PKT_CNT (0xcull) /* [CN10K, .) */ 512 #define RPM_MTI_STAT_TX_512_1023_PKT_CNT (0xdull) /* [CN10K, .) */ 513 #define RPM_MTI_STAT_TX_1024_1518_PKT_CNT (0xeull) /* [CN10K, .) */ 514 #define RPM_MTI_STAT_TX_1519_MAX_PKT_CNT (0xfull) /* [CN10K, .) */ 515 #define RPM_MTI_STAT_TX_CBFC_CLASS_0 (0x10ull) /* [CN10K, .) */ 516 #define RPM_MTI_STAT_TX_CBFC_CLASS_1 (0x11ull) /* [CN10K, .) */ 517 #define RPM_MTI_STAT_TX_CBFC_CLASS_2 (0x12ull) /* [CN10K, .) */ 518 #define RPM_MTI_STAT_TX_CBFC_CLASS_3 (0x13ull) /* [CN10K, .) */ 519 #define RPM_MTI_STAT_TX_CBFC_CLASS_4 (0x14ull) /* [CN10K, .) */ 520 #define RPM_MTI_STAT_TX_CBFC_CLASS_5 (0x15ull) /* [CN10K, .) */ 521 #define RPM_MTI_STAT_TX_CBFC_CLASS_6 (0x16ull) /* [CN10K, .) */ 522 #define RPM_MTI_STAT_TX_CBFC_CLASS_7 (0x17ull) /* [CN10K, .) */ 523 #define RPM_MTI_STAT_TX_CBFC_CLASS_8 (0x18ull) /* [CN10K, .) */ 524 #define RPM_MTI_STAT_TX_CBFC_CLASS_9 (0x19ull) /* [CN10K, .) */ 525 #define RPM_MTI_STAT_TX_CBFC_CLASS_10 (0x1aull) /* [CN10K, .) */ 526 #define RPM_MTI_STAT_TX_CBFC_CLASS_11 (0x1bull) /* [CN10K, .) */ 527 #define RPM_MTI_STAT_TX_CBFC_CLASS_12 (0x1cull) /* [CN10K, .) */ 528 #define RPM_MTI_STAT_TX_CBFC_CLASS_13 (0x1dull) /* [CN10K, .) */ 529 #define RPM_MTI_STAT_TX_CBFC_CLASS_14 (0x1eull) /* [CN10K, .) */ 530 #define RPM_MTI_STAT_TX_CBFC_CLASS_15 (0x1full) /* [CN10K, .) */ 531 #define RPM_MTI_STAT_TX_MAC_CONTROL_FRAMES (0x20ull) /* [CN10K, .) */ 532 #define RPM_MTI_STAT_TX_PKT_CNT (0x21ull) /* [CN10K, .) */ 533 534 #define NIX_SQOPERR_SQ_OOR (0x0ull) 535 #define NIX_SQOPERR_SQ_CTX_FAULT (0x1ull) 536 #define NIX_SQOPERR_SQ_CTX_POISON (0x2ull) 537 #define NIX_SQOPERR_SQ_DISABLED (0x3ull) 538 #define NIX_SQOPERR_MAX_SQE_SIZE_ERR (0x4ull) 539 #define NIX_SQOPERR_SQE_OFLOW (0x5ull) 540 #define NIX_SQOPERR_SQB_NULL (0x6ull) 541 #define NIX_SQOPERR_SQB_FAULT (0x7ull) 542 #define NIX_SQOPERR_SQE_SIZEM1_ZERO (0x8ull) /* [CN10K, .) */ 543 544 #define NIX_SQINT_LMT_ERR (0x0ull) 545 #define NIX_SQINT_MNQ_ERR (0x1ull) 546 #define NIX_SQINT_SEND_ERR (0x2ull) 547 #define NIX_SQINT_SQB_ALLOC_FAIL (0x3ull) 548 549 #define NIX_SEND_STATUS_GOOD (0x0ull) 550 #define NIX_SEND_STATUS_SQ_CTX_FAULT (0x1ull) 551 #define NIX_SEND_STATUS_SQ_CTX_POISON (0x2ull) 552 #define NIX_SEND_STATUS_SQB_FAULT (0x3ull) 553 #define NIX_SEND_STATUS_SQB_POISON (0x4ull) 554 #define NIX_SEND_STATUS_SEND_HDR_ERR (0x5ull) 555 #define NIX_SEND_STATUS_SEND_EXT_ERR (0x6ull) 556 #define NIX_SEND_STATUS_JUMP_FAULT (0x7ull) 557 #define NIX_SEND_STATUS_JUMP_POISON (0x8ull) 558 #define NIX_SEND_STATUS_SEND_CRC_ERR (0x10ull) 559 #define NIX_SEND_STATUS_SEND_IMM_ERR (0x11ull) 560 #define NIX_SEND_STATUS_SEND_SG_ERR (0x12ull) 561 #define NIX_SEND_STATUS_SEND_MEM_ERR (0x13ull) 562 #define NIX_SEND_STATUS_INVALID_SUBDC (0x14ull) 563 #define NIX_SEND_STATUS_SUBDC_ORDER_ERR (0x15ull) 564 #define NIX_SEND_STATUS_DATA_FAULT (0x16ull) 565 #define NIX_SEND_STATUS_DATA_POISON (0x17ull) 566 #define NIX_SEND_STATUS_NPC_DROP_ACTION (0x20ull) 567 #define NIX_SEND_STATUS_LOCK_VIOL (0x21ull) 568 #define NIX_SEND_STATUS_NPC_UCAST_CHAN_ERR (0x22ull) 569 #define NIX_SEND_STATUS_NPC_MCAST_CHAN_ERR (0x23ull) 570 #define NIX_SEND_STATUS_NPC_MCAST_ABORT (0x24ull) 571 #define NIX_SEND_STATUS_NPC_VTAG_PTR_ERR (0x25ull) 572 #define NIX_SEND_STATUS_NPC_VTAG_SIZE_ERR (0x26ull) 573 #define NIX_SEND_STATUS_SEND_MEM_FAULT (0x27ull) 574 #define NIX_SEND_STATUS_SEND_STATS_ERR (0x28ull) 575 576 #define NIX_SENDSTATSALG_NOP (0x0ull) 577 #define NIX_SENDSTATSALG_ADD_PKT_CNT (0x1ull) 578 #define NIX_SENDSTATSALG_ADD_BYTE_CNT (0x2ull) 579 #define NIX_SENDSTATSALG_ADD_PKT_BYTE_CNT (0x3ull) 580 #define NIX_SENDSTATSALG_UPDATE_PKT_CNT_ON_DROP (0x4ull) 581 #define NIX_SENDSTATSALG_UPDATE_BYTE_CNT_ON_DROP (0x5ull) 582 #define NIX_SENDSTATSALG_UPDATE_PKT_BYTE_CNT_ON_DROP (0x6ull) 583 584 #define NIX_SENDMEMDSZ_B64 (0x0ull) 585 #define NIX_SENDMEMDSZ_B32 (0x1ull) 586 #define NIX_SENDMEMDSZ_B16 (0x2ull) 587 #define NIX_SENDMEMDSZ_B8 (0x3ull) 588 589 #define NIX_SENDMEMALG_SET (0x0ull) 590 #define NIX_SENDMEMALG_SETTSTMP (0x1ull) 591 #define NIX_SENDMEMALG_SETRSLT (0x2ull) 592 #define NIX_SENDMEMALG_ADD (0x8ull) 593 #define NIX_SENDMEMALG_SUB (0x9ull) 594 #define NIX_SENDMEMALG_ADDLEN (0xaull) 595 #define NIX_SENDMEMALG_SUBLEN (0xbull) 596 #define NIX_SENDMEMALG_ADDMBUF (0xcull) 597 #define NIX_SENDMEMALG_SUBMBUF (0xdull) 598 599 #define NIX_SUBDC_NOP (0x0ull) 600 #define NIX_SUBDC_EXT (0x1ull) 601 #define NIX_SUBDC_CRC (0x2ull) 602 #define NIX_SUBDC_IMM (0x3ull) 603 #define NIX_SUBDC_SG (0x4ull) 604 #define NIX_SUBDC_MEM (0x5ull) 605 #define NIX_SUBDC_JUMP (0x6ull) 606 #define NIX_SUBDC_WORK (0x7ull) 607 #define NIX_SUBDC_SG2 (0x8ull) /* [CN10K, .) */ 608 #define NIX_SUBDC_AGE_AND_STATS (0x9ull) /* [CN10K, .) */ 609 #define NIX_SUBDC_SOD (0xfull) 610 611 #define NIX_STYPE_STF (0x0ull) 612 #define NIX_STYPE_STT (0x1ull) 613 #define NIX_STYPE_STP (0x2ull) 614 615 #define NIX_RX_ACTIONOP_DROP (0x0ull) 616 #define NIX_RX_ACTIONOP_UCAST (0x1ull) 617 #define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull) 618 #define NIX_RX_ACTIONOP_MCAST (0x3ull) 619 #define NIX_RX_ACTIONOP_RSS (0x4ull) 620 #define NIX_RX_ACTIONOP_PF_FUNC_DROP (0x5ull) 621 #define NIX_RX_ACTIONOP_MIRROR (0x6ull) 622 #define NIX_RX_ACTIONOP_DEFAULT (0xfull) 623 624 #define NIX_RX_VTAGACTION_VTAG0_RELPTR (0x0ull) 625 #define NIX_RX_VTAGACTION_VTAG1_RELPTR (0x4ull) 626 #define NIX_RX_VTAGACTION_VTAG_VALID (0x1ull) 627 #define NIX_TX_VTAGACTION_VTAG0_RELPTR (sizeof(struct nix_inst_hdr_s) + 2 * 6) 628 #define NIX_TX_VTAGACTION_VTAG1_RELPTR \ 629 (sizeof(struct nix_inst_hdr_s) + 2 * 6 + 4) 630 #define NIX_RQINT_DROP (0x0ull) 631 #define NIX_RQINT_RED (0x1ull) 632 #define NIX_RQINT_R2 (0x2ull) 633 #define NIX_RQINT_R3 (0x3ull) 634 #define NIX_RQINT_R4 (0x4ull) 635 #define NIX_RQINT_R5 (0x5ull) 636 #define NIX_RQINT_R6 (0x6ull) 637 #define NIX_RQINT_R7 (0x7ull) 638 639 #define NIX_MAXSQESZ_W16 (0x0ull) 640 #define NIX_MAXSQESZ_W8 (0x1ull) 641 642 #define NIX_LSOALG_NOP (0x0ull) 643 #define NIX_LSOALG_ADD_SEGNUM (0x1ull) 644 #define NIX_LSOALG_ADD_PAYLEN (0x2ull) 645 #define NIX_LSOALG_ADD_OFFSET (0x3ull) 646 #define NIX_LSOALG_TCP_FLAGS (0x4ull) 647 648 #define NIX_MNQERR_SQ_CTX_FAULT (0x0ull) 649 #define NIX_MNQERR_SQ_CTX_POISON (0x1ull) 650 #define NIX_MNQERR_SQB_FAULT (0x2ull) 651 #define NIX_MNQERR_SQB_POISON (0x3ull) 652 #define NIX_MNQERR_TOTAL_ERR (0x4ull) 653 #define NIX_MNQERR_LSO_ERR (0x5ull) 654 #define NIX_MNQERR_CQ_QUERY_ERR (0x6ull) 655 #define NIX_MNQERR_MAX_SQE_SIZE_ERR (0x7ull) 656 #define NIX_MNQERR_MAXLEN_ERR (0x8ull) 657 #define NIX_MNQERR_SQE_SIZEM1_ZERO (0x9ull) 658 659 #define NIX_MDTYPE_RSVD (0x0ull) 660 #define NIX_MDTYPE_FLUSH (0x1ull) 661 #define NIX_MDTYPE_PMD (0x2ull) 662 663 #define NIX_NDC_TX_PORT_LMT (0x0ull) 664 #define NIX_NDC_TX_PORT_ENQ (0x1ull) 665 #define NIX_NDC_TX_PORT_MNQ (0x2ull) 666 #define NIX_NDC_TX_PORT_DEQ (0x3ull) 667 #define NIX_NDC_TX_PORT_DMA (0x4ull) 668 #define NIX_NDC_TX_PORT_XQE (0x5ull) 669 670 #define NIX_NDC_RX_PORT_AQ (0x0ull) 671 #define NIX_NDC_RX_PORT_CQ (0x1ull) 672 #define NIX_NDC_RX_PORT_CINT (0x2ull) 673 #define NIX_NDC_RX_PORT_MC (0x3ull) 674 #define NIX_NDC_RX_PORT_PKT (0x4ull) 675 #define NIX_NDC_RX_PORT_RQ (0x5ull) 676 677 #define NIX_RE_OPCODE_RE_NONE (0x0ull) 678 #define NIX_RE_OPCODE_RE_PARTIAL (0x1ull) 679 #define NIX_RE_OPCODE_RE_JABBER (0x2ull) 680 #define NIX_RE_OPCODE_RE_FCS (0x7ull) 681 #define NIX_RE_OPCODE_RE_FCS_RCV (0x8ull) 682 #define NIX_RE_OPCODE_RE_TERMINATE (0x9ull) 683 #define NIX_RE_OPCODE_RE_RX_CTL (0xbull) 684 #define NIX_RE_OPCODE_RE_SKIP (0xcull) 685 #define NIX_RE_OPCODE_RE_DMAPKT (0xfull) 686 #define NIX_RE_OPCODE_UNDERSIZE (0x10ull) 687 #define NIX_RE_OPCODE_OVERSIZE (0x11ull) 688 #define NIX_RE_OPCODE_OL2_LENMISM (0x12ull) 689 690 #define NIX_REDALG_STD (0x0ull) 691 #define NIX_REDALG_SEND (0x1ull) 692 #define NIX_REDALG_STALL (0x2ull) 693 #define NIX_REDALG_DISCARD (0x3ull) 694 695 #define NIX_RX_BAND_PROF_ACTIONRESULT_PASS (0x0ull) /* [CN10K, .) */ 696 #define NIX_RX_BAND_PROF_ACTIONRESULT_DROP (0x1ull) /* [CN10K, .) */ 697 #define NIX_RX_BAND_PROF_ACTIONRESULT_RED (0x2ull) /* [CN10K, .) */ 698 699 #define NIX_RX_BAND_PROF_LAYER_LEAF (0x0ull) /* [CN10K, .) */ 700 #define NIX_RX_BAND_PROF_LAYER_INVALID (0x1ull) /* [CN10K, .) */ 701 #define NIX_RX_BAND_PROF_LAYER_MIDDLE (0x2ull) /* [CN10K, .) */ 702 #define NIX_RX_BAND_PROF_LAYER_TOP (0x3ull) /* [CN10K, .) */ 703 #define NIX_RX_BAND_PROF_LAYER_MAX (0x4ull) /* [CN10K, .) */ 704 705 #define NIX_RX_BAND_PROF_PC_MODE_VLAN (0x0ull) /* [CN10K, .) */ 706 #define NIX_RX_BAND_PROF_PC_MODE_DSCP (0x1ull) /* [CN10K, .) */ 707 #define NIX_RX_BAND_PROF_PC_MODE_GEN (0x2ull) /* [CN10K, .) */ 708 #define NIX_RX_BAND_PROF_PC_MODE_RSVD (0x3ull) /* [CN10K, .) */ 709 710 #define NIX_RX_COLORRESULT_GREEN (0x0ull) /* [CN10K, .) */ 711 #define NIX_RX_COLORRESULT_YELLOW (0x1ull) /* [CN10K, .) */ 712 #define NIX_RX_COLORRESULT_RED (0x2ull) /* [CN10K, .) */ 713 714 #define NIX_RX_MCOP_RQ (0x0ull) 715 #define NIX_RX_MCOP_RSS (0x1ull) 716 717 #define NIX_RX_PERRCODE_NPC_RESULT_ERR (0x2ull) 718 #define NIX_RX_PERRCODE_MCAST_FAULT (0x4ull) 719 #define NIX_RX_PERRCODE_MIRROR_FAULT (0x5ull) 720 #define NIX_RX_PERRCODE_MCAST_POISON (0x6ull) 721 #define NIX_RX_PERRCODE_MIRROR_POISON (0x7ull) 722 #define NIX_RX_PERRCODE_DATA_FAULT (0x8ull) 723 #define NIX_RX_PERRCODE_MEMOUT (0x9ull) 724 #define NIX_RX_PERRCODE_BUFS_OFLOW (0xaull) 725 #define NIX_RX_PERRCODE_OL3_LEN (0x10ull) 726 #define NIX_RX_PERRCODE_OL4_LEN (0x11ull) 727 #define NIX_RX_PERRCODE_OL4_CHK (0x12ull) 728 #define NIX_RX_PERRCODE_OL4_PORT (0x13ull) 729 #define NIX_RX_PERRCODE_IL3_LEN (0x20ull) 730 #define NIX_RX_PERRCODE_IL4_LEN (0x21ull) 731 #define NIX_RX_PERRCODE_IL4_CHK (0x22ull) 732 #define NIX_RX_PERRCODE_IL4_PORT (0x23ull) 733 734 #define NIX_SA_ALG_NON_MS (0x0ull) /* [CN10K, .) */ 735 #define NIX_SA_ALG_MS_CISCO (0x1ull) /* [CN10K, .) */ 736 #define NIX_SA_ALG_MS_VIPTELA (0x2ull) /* [CN10K, .) */ 737 738 #define NIX_SENDCRCALG_CRC32 (0x0ull) 739 #define NIX_SENDCRCALG_CRC32C (0x1ull) 740 #define NIX_SENDCRCALG_ONES16 (0x2ull) 741 742 #define NIX_SENDL3TYPE_NONE (0x0ull) 743 #define NIX_SENDL3TYPE_IP4 (0x2ull) 744 #define NIX_SENDL3TYPE_IP4_CKSUM (0x3ull) 745 #define NIX_SENDL3TYPE_IP6 (0x4ull) 746 747 #define NIX_SENDL4TYPE_NONE (0x0ull) 748 #define NIX_SENDL4TYPE_TCP_CKSUM (0x1ull) 749 #define NIX_SENDL4TYPE_SCTP_CKSUM (0x2ull) 750 #define NIX_SENDL4TYPE_UDP_CKSUM (0x3ull) 751 752 #define NIX_SENDLDTYPE_LDD (0x0ull) 753 #define NIX_SENDLDTYPE_LDT (0x1ull) 754 #define NIX_SENDLDTYPE_LDWB (0x2ull) 755 756 #define NIX_XQESZ_W64 (0x0ull) 757 #define NIX_XQESZ_W16 (0x1ull) 758 759 #define NIX_XQE_TYPE_INVALID (0x0ull) 760 #define NIX_XQE_TYPE_RX (0x1ull) 761 #define NIX_XQE_TYPE_RX_IPSECS (0x2ull) 762 #define NIX_XQE_TYPE_RX_IPSECH (0x3ull) 763 #define NIX_XQE_TYPE_RX_IPSECD (0x4ull) 764 #define NIX_XQE_TYPE_RX_VWQE (0x5ull) /* [CN10K, .) */ 765 #define NIX_XQE_TYPE_RES_6 (0x6ull) 766 #define NIX_XQE_TYPE_RES_7 (0x7ull) 767 #define NIX_XQE_TYPE_SEND (0x8ull) 768 #define NIX_XQE_TYPE_RES_9 (0x9ull) 769 #define NIX_XQE_TYPE_RES_A (0xAull) 770 #define NIX_XQE_TYPE_RES_B (0xBull) 771 #define NIX_XQE_TYPE_RES_C (0xCull) 772 #define NIX_XQE_TYPE_RES_D (0xDull) 773 #define NIX_XQE_TYPE_RES_E (0xEull) 774 #define NIX_XQE_TYPE_RES_F (0xFull) 775 776 #define NIX_TX_VTAGOP_NOP (0x0ull) 777 #define NIX_TX_VTAGOP_INSERT (0x1ull) 778 #define NIX_TX_VTAGOP_REPLACE (0x2ull) 779 780 #define NIX_VTAGSIZE_T4 (0x0ull) 781 #define NIX_VTAGSIZE_T8 (0x1ull) 782 783 #define NIX_TXLAYER_OL3 (0x0ull) 784 #define NIX_TXLAYER_OL4 (0x1ull) 785 #define NIX_TXLAYER_IL3 (0x2ull) 786 #define NIX_TXLAYER_IL4 (0x3ull) 787 788 #define NIX_TX_ACTIONOP_DROP (0x0ull) 789 #define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull) 790 #define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull) 791 #define NIX_TX_ACTIONOP_MCAST (0x3ull) 792 #define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull) 793 794 #define NIX_AQ_COMP_NOTDONE (0x0ull) 795 #define NIX_AQ_COMP_GOOD (0x1ull) 796 #define NIX_AQ_COMP_SWERR (0x2ull) 797 #define NIX_AQ_COMP_CTX_POISON (0x3ull) 798 #define NIX_AQ_COMP_CTX_FAULT (0x4ull) 799 #define NIX_AQ_COMP_LOCKERR (0x5ull) 800 #define NIX_AQ_COMP_SQB_ALLOC_FAIL (0x6ull) 801 802 #define NIX_AF_INT_VEC_RVU (0x0ull) 803 #define NIX_AF_INT_VEC_GEN (0x1ull) 804 #define NIX_AF_INT_VEC_AQ_DONE (0x2ull) 805 #define NIX_AF_INT_VEC_AF_ERR (0x3ull) 806 #define NIX_AF_INT_VEC_POISON (0x4ull) 807 808 #define NIX_AQINT_GEN_RX_MCAST_DROP (0x0ull) 809 #define NIX_AQINT_GEN_RX_MIRROR_DROP (0x1ull) 810 #define NIX_AQINT_GEN_TL1_DRAIN (0x3ull) 811 #define NIX_AQINT_GEN_SMQ_FLUSH_DONE (0x4ull) 812 813 #define NIX_AQ_INSTOP_NOP (0x0ull) 814 #define NIX_AQ_INSTOP_INIT (0x1ull) 815 #define NIX_AQ_INSTOP_WRITE (0x2ull) 816 #define NIX_AQ_INSTOP_READ (0x3ull) 817 #define NIX_AQ_INSTOP_LOCK (0x4ull) 818 #define NIX_AQ_INSTOP_UNLOCK (0x5ull) 819 820 #define NIX_AQ_CTYPE_RQ (0x0ull) 821 #define NIX_AQ_CTYPE_SQ (0x1ull) 822 #define NIX_AQ_CTYPE_CQ (0x2ull) 823 #define NIX_AQ_CTYPE_MCE (0x3ull) 824 #define NIX_AQ_CTYPE_RSS (0x4ull) 825 #define NIX_AQ_CTYPE_DYNO (0x5ull) 826 #define NIX_AQ_CTYPE_BAND_PROF (0x6ull) /* [CN10K, .) */ 827 828 #define NIX_COLORRESULT_GREEN (0x0ull) 829 #define NIX_COLORRESULT_YELLOW (0x1ull) 830 #define NIX_COLORRESULT_RED_SEND (0x2ull) 831 #define NIX_COLORRESULT_RED_DROP (0x3ull) 832 833 #define NIX_CHAN_LBKX_CHX(a, b) \ 834 (0x000ull | ((uint64_t)(a) << 8) | (uint64_t)(b)) 835 #define NIX_CHAN_CPT_CH_END (0x4ffull) /* [CN10K, .) */ 836 #define NIX_CHAN_CPT_CH_START (0x800ull) /* [CN10K, .) */ 837 #define NIX_CHAN_R4 (0x400ull) /* [CN9K, CN10K) */ 838 #define NIX_CHAN_R5 (0x500ull) 839 #define NIX_CHAN_R6 (0x600ull) 840 #define NIX_CHAN_SDP_CH_END (0x7ffull) 841 #define NIX_CHAN_SDP_CH_START (0x700ull) 842 /* [CN9K, CN10K) */ 843 #define NIX_CHAN_CGXX_LMACX_CHX(a, b, c) \ 844 (0x800ull | ((uint64_t)(a) << 8) | ((uint64_t)(b) << 4) | (uint64_t)(c)) 845 /* [CN10K, .) */ 846 #define NIX_CHAN_RPMX_LMACX_CHX(a, b, c) \ 847 (0x800ull | ((uint64_t)(a) << 8) | ((uint64_t)(b) << 4) | (uint64_t)(c)) 848 849 /* The mask is to extract lower 10-bits of channel number 850 * which CPT will pass to X2P. 851 */ 852 #define NIX_CHAN_CPT_X2P_MASK (0x3ffull) 853 854 #define NIX_INTF_SDP (0x4ull) 855 #define NIX_INTF_CGX0 (0x0ull) /* [CN9K, CN10K) */ 856 #define NIX_INTF_CGX1 (0x1ull) /* [CN9K, CN10K) */ 857 #define NIX_INTF_CGX2 (0x2ull) /* [CN9K, CN10K) */ 858 #define NIX_INTF_RPM0 (0x0ull) /* [CN10K, .) */ 859 #define NIX_INTF_RPM1 (0x1ull) /* [CN10K, .) */ 860 #define NIX_INTF_RPM2 (0x2ull) /* [CN10K, .) */ 861 #define NIX_INTF_LBK0 (0x3ull) 862 #define NIX_INTF_CPT0 (0x5ull) /* [CN10K, .) */ 863 864 #define NIX_CQERRINT_DOOR_ERR (0x0ull) 865 #define NIX_CQERRINT_WR_FULL (0x1ull) 866 #define NIX_CQERRINT_CQE_FAULT (0x2ull) 867 #define NIX_CQERRINT_CPT_DROP (0x3ull) /* [CN10KB, .) */ 868 869 #define NIX_LINK_SDP (0xdull) /* [CN10K, .) */ 870 #define NIX_LINK_CPT (0xeull) /* [CN10K, .) */ 871 #define NIX_LINK_MC (0xfull) /* [CN10K, .) */ 872 /* [CN10K, .) */ 873 #define NIX_LINK_RPMX_LMACX(a, b) \ 874 (0x00ull | ((uint64_t)(a) << 2) | (uint64_t)(b)) 875 #define NIX_LINK_LBK0 (0xcull) 876 877 #define NIX_LF_INT_VEC_GINT (0x80ull) 878 #define NIX_LF_INT_VEC_ERR_INT (0x81ull) 879 #define NIX_LF_INT_VEC_POISON (0x82ull) 880 #define NIX_LF_INT_VEC_QINT_END (0x3full) 881 #define NIX_LF_INT_VEC_QINT_START (0x0ull) 882 #define NIX_LF_INT_VEC_CINT_END (0x7full) 883 #define NIX_LF_INT_VEC_CINT_START (0x40ull) 884 885 #define NIX_INTF_RX (0x0ull) 886 #define NIX_INTF_TX (0x1ull) 887 888 /* Enums definitions */ 889 890 /* Structures definitions */ 891 892 /* NIX aging and send stats subdescriptor structure */ 893 struct nix_age_and_send_stats_s { 894 uint64_t threshold : 29; 895 uint64_t latency_drop : 1; 896 uint64_t aging : 1; 897 uint64_t wmem : 1; 898 uint64_t ooffset : 12; 899 uint64_t ioffset : 12; 900 uint64_t sel : 1; 901 uint64_t alg : 3; 902 uint64_t subdc : 4; 903 uint64_t addr : 64; /* W1 */ 904 }; 905 906 /* NIX admin queue instruction structure */ 907 struct nix_aq_inst_s { 908 uint64_t op : 4; 909 uint64_t ctype : 4; 910 uint64_t lf : 7; 911 uint64_t rsvd_23_15 : 9; 912 uint64_t cindex : 20; 913 uint64_t rsvd_62_44 : 19; 914 uint64_t doneint : 1; 915 uint64_t res_addr : 64; /* W1 */ 916 }; 917 918 /* NIX admin queue result structure */ 919 struct nix_aq_res_s { 920 uint64_t op : 4; 921 uint64_t ctype : 4; 922 uint64_t compcode : 8; 923 uint64_t doneint : 1; 924 uint64_t rsvd_63_17 : 47; 925 uint64_t rsvd_127_64 : 64; /* W1 */ 926 }; 927 928 /* NIX bandwidth profile structure */ 929 struct nix_band_prof_s { 930 uint64_t pc_mode : 2; 931 uint64_t icolor : 2; 932 uint64_t tnl_ena : 1; 933 uint64_t rsvd_7_5 : 3; 934 uint64_t peir_exponent : 5; 935 uint64_t rsvd_15_13 : 3; 936 uint64_t pebs_exponent : 5; 937 uint64_t rsvd_23_21 : 3; 938 uint64_t cir_exponent : 5; 939 uint64_t rsvd_31_29 : 3; 940 uint64_t cbs_exponent : 5; 941 uint64_t rsvd_39_37 : 3; 942 uint64_t peir_mantissa : 8; 943 uint64_t pebs_mantissa : 8; 944 uint64_t cir_mantissa : 8; 945 uint64_t cbs_mantissa : 8; 946 uint64_t lmode : 1; 947 uint64_t l_sellect : 3; 948 uint64_t rdiv : 4; 949 uint64_t adjust_exponent : 5; 950 uint64_t rsvd_86_85 : 2; 951 uint64_t adjust_mantissa : 9; 952 uint64_t gc_action : 2; 953 uint64_t yc_action : 2; 954 uint64_t rc_action : 2; 955 uint64_t meter_algo : 2; 956 uint64_t band_prof_id : 7; 957 uint64_t rsvd_118_111 : 8; 958 uint64_t hl_en : 1; 959 uint64_t rsvd_127_120 : 8; 960 uint64_t ts : 48; 961 uint64_t rsvd_191_176 : 16; 962 uint64_t pe_accum : 32; 963 uint64_t c_accum : 32; 964 uint64_t green_pkt_pass : 48; 965 uint64_t rsvd_319_304 : 16; 966 uint64_t yellow_pkt_pass : 48; 967 uint64_t rsvd_383_368 : 16; 968 uint64_t red_pkt_pass : 48; 969 uint64_t rsvd_447_432 : 16; 970 uint64_t green_octs_pass : 48; 971 uint64_t rsvd_511_496 : 16; 972 uint64_t yellow_octs_pass : 48; 973 uint64_t rsvd_575_560 : 16; 974 uint64_t red_octs_pass : 48; 975 uint64_t rsvd_639_624 : 16; 976 uint64_t green_pkt_drop : 48; 977 uint64_t rsvd_703_688 : 16; 978 uint64_t yellow_pkt_drop : 48; 979 uint64_t rsvd_767_752 : 16; 980 uint64_t red_pkt_drop : 48; 981 uint64_t rsvd_831_816 : 16; 982 uint64_t green_octs_drop : 48; 983 uint64_t rsvd_895_880 : 16; 984 uint64_t yellow_octs_drop : 48; 985 uint64_t rsvd_959_944 : 16; 986 uint64_t red_octs_drop : 48; 987 uint64_t rsvd_1023_1008 : 16; 988 }; 989 990 /* NIX completion interrupt context hardware structure */ 991 struct nix_cint_hw_s { 992 uint64_t ecount : 32; 993 uint64_t qcount : 16; 994 uint64_t intr : 1; 995 uint64_t ena : 1; 996 uint64_t timer_idx : 8; 997 uint64_t rsvd_63_58 : 6; 998 uint64_t ecount_wait : 32; 999 uint64_t qcount_wait : 16; 1000 uint64_t time_wait : 8; 1001 uint64_t rsvd_127_120 : 8; 1002 }; 1003 1004 /* NIX completion queue entry header structure */ 1005 struct nix_cqe_hdr_s { 1006 uint64_t tag : 32; 1007 uint64_t q : 20; 1008 uint64_t rsvd_57_52 : 6; 1009 uint64_t node : 2; 1010 uint64_t cqe_type : 4; 1011 }; 1012 1013 /* NIX completion queue context structure */ 1014 struct nix_cq_ctx_s { 1015 uint64_t base : 64; /* W0 */ 1016 uint64_t lbp_ena : 1; 1017 uint64_t lbpid_low : 3; 1018 uint64_t bp_ena : 1; 1019 uint64_t lbpid_med : 3; 1020 uint64_t bpid : 9; 1021 uint64_t lbpid_high : 3; 1022 uint64_t qint_idx : 7; 1023 uint64_t cq_err : 1; 1024 uint64_t cint_idx : 7; 1025 uint64_t avg_con : 9; 1026 uint64_t wrptr : 20; 1027 uint64_t tail : 20; 1028 uint64_t head : 20; 1029 uint64_t avg_level : 8; 1030 uint64_t update_time : 16; 1031 uint64_t bp : 8; 1032 uint64_t drop : 8; 1033 uint64_t drop_ena : 1; 1034 uint64_t ena : 1; 1035 uint64_t cpt_drop_err_en : 1; 1036 uint64_t rsvd_211 : 1; 1037 uint64_t substream : 12; 1038 uint64_t stash_thresh : 4; 1039 uint64_t lbp_frac : 4; 1040 uint64_t caching : 1; 1041 uint64_t stashing : 1; 1042 uint64_t rsvd_235_234 : 2; 1043 uint64_t qsize : 4; 1044 uint64_t cq_err_int : 8; 1045 uint64_t cq_err_int_ena : 8; 1046 }; 1047 1048 /* NIX instruction header structure */ 1049 struct nix_inst_hdr_s { 1050 uint64_t pf_func : 16; 1051 uint64_t sq : 20; 1052 uint64_t rsvd_63_36 : 28; 1053 }; 1054 1055 /* NIX i/o virtual address structure */ 1056 struct nix_iova_s { 1057 uint64_t addr : 64; /* W0 */ 1058 }; 1059 1060 /* NIX IPsec dynamic ordering counter structure */ 1061 struct nix_ipsec_dyno_s { 1062 uint32_t count : 32; /* W0 */ 1063 }; 1064 1065 /* NIX memory value structure */ 1066 struct nix_mem_result_s { 1067 uint64_t v : 1; 1068 uint64_t color : 2; 1069 uint64_t rsvd_63_3 : 61; 1070 }; 1071 1072 /* NIX statistics operation write data structure */ 1073 struct nix_op_q_wdata_s { 1074 uint64_t rsvd_31_0 : 32; 1075 uint64_t q : 20; 1076 uint64_t rsvd_63_52 : 12; 1077 }; 1078 1079 /* NIX queue interrupt context hardware structure */ 1080 struct nix_qint_hw_s { 1081 uint32_t count : 22; 1082 uint32_t rsvd_30_22 : 9; 1083 uint32_t ena : 1; 1084 }; 1085 1086 /* [CN10K, .) NIX receive queue context structure */ 1087 struct nix_cn10k_rq_ctx_hw_s { 1088 uint64_t ena : 1; 1089 uint64_t sso_ena : 1; 1090 uint64_t ipsech_ena : 1; 1091 uint64_t ena_wqwd : 1; 1092 uint64_t cq : 20; 1093 uint64_t rsvd_36_24 : 13; 1094 uint64_t lenerr_dis : 1; 1095 uint64_t csum_il4_dis : 1; 1096 uint64_t csum_ol4_dis : 1; 1097 uint64_t len_il4_dis : 1; 1098 uint64_t len_il3_dis : 1; 1099 uint64_t len_ol4_dis : 1; 1100 uint64_t len_ol3_dis : 1; 1101 uint64_t wqe_aura : 20; 1102 uint64_t spb_aura : 20; 1103 uint64_t lpb_aura : 20; 1104 uint64_t sso_grp : 10; 1105 uint64_t sso_tt : 2; 1106 uint64_t pb_caching : 2; 1107 uint64_t wqe_caching : 1; 1108 uint64_t xqe_drop_ena : 1; 1109 uint64_t spb_drop_ena : 1; 1110 uint64_t lpb_drop_ena : 1; 1111 uint64_t pb_stashing : 1; 1112 uint64_t ipsecd_drop_en : 1; 1113 uint64_t chi_ena : 1; 1114 uint64_t rsvd_127_125 : 3; 1115 uint64_t band_prof_id : 10; 1116 uint64_t rsvd_138 : 1; 1117 uint64_t policer_ena : 1; 1118 uint64_t spb_sizem1 : 6; 1119 uint64_t wqe_skip : 2; 1120 uint64_t spb_high_sizem1 : 3; 1121 uint64_t spb_ena : 1; 1122 uint64_t lpb_sizem1 : 12; 1123 uint64_t first_skip : 7; 1124 uint64_t rsvd_171 : 1; 1125 uint64_t later_skip : 6; 1126 uint64_t xqe_imm_size : 6; 1127 uint64_t rsvd_189_184 : 6; 1128 uint64_t xqe_imm_copy : 1; 1129 uint64_t xqe_hdr_split : 1; 1130 uint64_t xqe_drop : 8; 1131 uint64_t xqe_pass : 8; 1132 uint64_t wqe_pool_drop : 8; 1133 uint64_t wqe_pool_pass : 8; 1134 uint64_t spb_aura_drop : 8; 1135 uint64_t spb_aura_pass : 8; 1136 uint64_t spb_pool_drop : 8; 1137 uint64_t spb_pool_pass : 8; 1138 uint64_t lpb_aura_drop : 8; 1139 uint64_t lpb_aura_pass : 8; 1140 uint64_t lpb_pool_drop : 8; 1141 uint64_t lpb_pool_pass : 8; 1142 uint64_t rsvd_319_288 : 32; 1143 uint64_t ltag : 24; 1144 uint64_t good_utag : 8; 1145 uint64_t bad_utag : 8; 1146 uint64_t flow_tagw : 6; 1147 uint64_t ipsec_vwqe : 1; 1148 uint64_t vwqe_ena : 1; 1149 uint64_t vtime_wait : 8; 1150 uint64_t max_vsize_exp : 4; 1151 uint64_t vwqe_skip : 2; 1152 uint64_t rsvd_383_382 : 2; 1153 uint64_t octs : 48; 1154 uint64_t rsvd_447_432 : 16; 1155 uint64_t pkts : 48; 1156 uint64_t rsvd_511_496 : 16; 1157 uint64_t drop_octs : 48; 1158 uint64_t rsvd_575_560 : 16; 1159 uint64_t drop_pkts : 48; 1160 uint64_t rsvd_639_624 : 16; 1161 uint64_t re_pkts : 48; 1162 uint64_t rsvd_702_688 : 15; 1163 uint64_t ena_copy : 1; 1164 uint64_t rsvd_739_704 : 36; 1165 uint64_t rq_int : 8; 1166 uint64_t rq_int_ena : 8; 1167 uint64_t qint_idx : 7; 1168 uint64_t rsvd_767_763 : 5; 1169 uint64_t rsvd_831_768 : 64; /* W12 */ 1170 uint64_t rsvd_895_832 : 64; /* W13 */ 1171 uint64_t rsvd_959_896 : 64; /* W14 */ 1172 uint64_t rsvd_1023_960 : 64; /* W15 */ 1173 }; 1174 1175 /* NIX receive queue context structure */ 1176 struct nix_rq_ctx_hw_s { 1177 uint64_t ena : 1; 1178 uint64_t sso_ena : 1; 1179 uint64_t ipsech_ena : 1; 1180 uint64_t ena_wqwd : 1; 1181 uint64_t cq : 20; 1182 uint64_t substream : 20; 1183 uint64_t wqe_aura : 20; 1184 uint64_t spb_aura : 20; 1185 uint64_t lpb_aura : 20; 1186 uint64_t sso_grp : 10; 1187 uint64_t sso_tt : 2; 1188 uint64_t pb_caching : 2; 1189 uint64_t wqe_caching : 1; 1190 uint64_t xqe_drop_ena : 1; 1191 uint64_t spb_drop_ena : 1; 1192 uint64_t lpb_drop_ena : 1; 1193 uint64_t wqe_skip : 2; 1194 uint64_t rsvd_127_124 : 4; 1195 uint64_t rsvd_139_128 : 12; 1196 uint64_t spb_sizem1 : 6; 1197 uint64_t rsvd_150_146 : 5; 1198 uint64_t spb_ena : 1; 1199 uint64_t lpb_sizem1 : 12; 1200 uint64_t first_skip : 7; 1201 uint64_t rsvd_171 : 1; 1202 uint64_t later_skip : 6; 1203 uint64_t xqe_imm_size : 6; 1204 uint64_t rsvd_189_184 : 6; 1205 uint64_t xqe_imm_copy : 1; 1206 uint64_t xqe_hdr_split : 1; 1207 uint64_t xqe_drop : 8; 1208 uint64_t xqe_pass : 8; 1209 uint64_t wqe_pool_drop : 8; 1210 uint64_t wqe_pool_pass : 8; 1211 uint64_t spb_aura_drop : 8; 1212 uint64_t spb_aura_pass : 8; 1213 uint64_t spb_pool_drop : 8; 1214 uint64_t spb_pool_pass : 8; 1215 uint64_t lpb_aura_drop : 8; 1216 uint64_t lpb_aura_pass : 8; 1217 uint64_t lpb_pool_drop : 8; 1218 uint64_t lpb_pool_pass : 8; 1219 uint64_t rsvd_319_288 : 32; 1220 uint64_t ltag : 24; 1221 uint64_t good_utag : 8; 1222 uint64_t bad_utag : 8; 1223 uint64_t flow_tagw : 6; 1224 uint64_t rsvd_383_366 : 18; 1225 uint64_t octs : 48; 1226 uint64_t rsvd_447_432 : 16; 1227 uint64_t pkts : 48; 1228 uint64_t rsvd_511_496 : 16; 1229 uint64_t drop_octs : 48; 1230 uint64_t rsvd_575_560 : 16; 1231 uint64_t drop_pkts : 48; 1232 uint64_t rsvd_639_624 : 16; 1233 uint64_t re_pkts : 48; 1234 uint64_t rsvd_702_688 : 15; 1235 uint64_t ena_copy : 1; 1236 uint64_t rsvd_739_704 : 36; 1237 uint64_t rq_int : 8; 1238 uint64_t rq_int_ena : 8; 1239 uint64_t qint_idx : 7; 1240 uint64_t rsvd_767_763 : 5; 1241 uint64_t rsvd_831_768 : 64; /* W12 */ 1242 uint64_t rsvd_895_832 : 64; /* W13 */ 1243 uint64_t rsvd_959_896 : 64; /* W14 */ 1244 uint64_t rsvd_1023_960 : 64; /* W15 */ 1245 }; 1246 1247 /* [CN10K, .) NIX Receive queue context structure */ 1248 struct nix_cn10k_rq_ctx_s { 1249 uint64_t ena : 1; 1250 uint64_t sso_ena : 1; 1251 uint64_t ipsech_ena : 1; 1252 uint64_t ena_wqwd : 1; 1253 uint64_t cq : 20; 1254 uint64_t rsvd_34_24 : 11; 1255 uint64_t port_ol4_dis : 1; 1256 uint64_t port_il4_dis : 1; 1257 uint64_t lenerr_dis : 1; 1258 uint64_t csum_il4_dis : 1; 1259 uint64_t csum_ol4_dis : 1; 1260 uint64_t len_il4_dis : 1; 1261 uint64_t len_il3_dis : 1; 1262 uint64_t len_ol4_dis : 1; 1263 uint64_t len_ol3_dis : 1; 1264 uint64_t wqe_aura : 20; 1265 uint64_t spb_aura : 20; 1266 uint64_t lpb_aura : 20; 1267 uint64_t sso_grp : 10; 1268 uint64_t sso_tt : 2; 1269 uint64_t pb_caching : 2; 1270 uint64_t wqe_caching : 1; 1271 uint64_t xqe_drop_ena : 1; 1272 uint64_t spb_drop_ena : 1; 1273 uint64_t lpb_drop_ena : 1; 1274 uint64_t pb_stashing : 1; 1275 uint64_t ipsecd_drop_en : 1; 1276 uint64_t chi_ena : 1; 1277 uint64_t rsvd_127_125 : 3; 1278 uint64_t band_prof_id : 10; 1279 uint64_t rsvd_138 : 1; 1280 uint64_t policer_ena : 1; 1281 uint64_t spb_sizem1 : 6; 1282 uint64_t wqe_skip : 2; 1283 uint64_t spb_high_sizem1 : 3; 1284 uint64_t spb_ena : 1; 1285 uint64_t lpb_sizem1 : 12; 1286 uint64_t first_skip : 7; 1287 uint64_t rsvd_171 : 1; 1288 uint64_t later_skip : 6; 1289 uint64_t xqe_imm_size : 6; 1290 uint64_t rsvd_189_184 : 6; 1291 uint64_t xqe_imm_copy : 1; 1292 uint64_t xqe_hdr_split : 1; 1293 uint64_t xqe_drop : 8; 1294 uint64_t xqe_pass : 8; 1295 uint64_t wqe_pool_drop : 8; 1296 uint64_t wqe_pool_pass : 8; 1297 uint64_t spb_aura_drop : 8; 1298 uint64_t spb_aura_pass : 8; 1299 uint64_t spb_pool_drop : 8; 1300 uint64_t spb_pool_pass : 8; 1301 uint64_t lpb_aura_drop : 8; 1302 uint64_t lpb_aura_pass : 8; 1303 uint64_t lpb_pool_drop : 8; 1304 uint64_t lpb_pool_pass : 8; 1305 uint64_t rsvd_291_288 : 4; 1306 uint64_t rq_int : 8; 1307 uint64_t rq_int_ena : 8; 1308 uint64_t qint_idx : 7; 1309 uint64_t rsvd_319_315 : 5; 1310 uint64_t ltag : 24; 1311 uint64_t good_utag : 8; 1312 uint64_t bad_utag : 8; 1313 uint64_t flow_tagw : 6; 1314 uint64_t ipsec_vwqe : 1; 1315 uint64_t vwqe_ena : 1; 1316 uint64_t vtime_wait : 8; 1317 uint64_t max_vsize_exp : 4; 1318 uint64_t vwqe_skip : 2; 1319 uint64_t rsvd_383_382 : 2; 1320 uint64_t octs : 48; 1321 uint64_t rsvd_447_432 : 16; 1322 uint64_t pkts : 48; 1323 uint64_t rsvd_511_496 : 16; 1324 uint64_t drop_octs : 48; 1325 uint64_t rsvd_575_560 : 16; 1326 uint64_t drop_pkts : 48; 1327 uint64_t rsvd_639_624 : 16; 1328 uint64_t re_pkts : 48; 1329 uint64_t rsvd_703_688 : 16; 1330 uint64_t rsvd_767_704 : 64; /* W11 */ 1331 uint64_t rsvd_831_768 : 64; /* W12 */ 1332 uint64_t rsvd_895_832 : 64; /* W13 */ 1333 uint64_t rsvd_959_896 : 64; /* W14 */ 1334 uint64_t rsvd_1023_960 : 64; /* W15 */ 1335 }; 1336 1337 /* NIX receive queue context structure */ 1338 struct nix_rq_ctx_s { 1339 uint64_t ena : 1; 1340 uint64_t sso_ena : 1; 1341 uint64_t ipsech_ena : 1; 1342 uint64_t ena_wqwd : 1; 1343 uint64_t cq : 20; 1344 uint64_t substream : 20; 1345 uint64_t wqe_aura : 20; 1346 uint64_t spb_aura : 20; 1347 uint64_t lpb_aura : 20; 1348 uint64_t sso_grp : 10; 1349 uint64_t sso_tt : 2; 1350 uint64_t pb_caching : 2; 1351 uint64_t wqe_caching : 1; 1352 uint64_t xqe_drop_ena : 1; 1353 uint64_t spb_drop_ena : 1; 1354 uint64_t lpb_drop_ena : 1; 1355 uint64_t rsvd_127_122 : 6; 1356 uint64_t rsvd_139_128 : 12; 1357 uint64_t spb_sizem1 : 6; 1358 uint64_t wqe_skip : 2; 1359 uint64_t rsvd_150_148 : 3; 1360 uint64_t spb_ena : 1; 1361 uint64_t lpb_sizem1 : 12; 1362 uint64_t first_skip : 7; 1363 uint64_t rsvd_171 : 1; 1364 uint64_t later_skip : 6; 1365 uint64_t xqe_imm_size : 6; 1366 uint64_t rsvd_189_184 : 6; 1367 uint64_t xqe_imm_copy : 1; 1368 uint64_t xqe_hdr_split : 1; 1369 uint64_t xqe_drop : 8; 1370 uint64_t xqe_pass : 8; 1371 uint64_t wqe_pool_drop : 8; 1372 uint64_t wqe_pool_pass : 8; 1373 uint64_t spb_aura_drop : 8; 1374 uint64_t spb_aura_pass : 8; 1375 uint64_t spb_pool_drop : 8; 1376 uint64_t spb_pool_pass : 8; 1377 uint64_t lpb_aura_drop : 8; 1378 uint64_t lpb_aura_pass : 8; 1379 uint64_t lpb_pool_drop : 8; 1380 uint64_t lpb_pool_pass : 8; 1381 uint64_t rsvd_291_288 : 4; 1382 uint64_t rq_int : 8; 1383 uint64_t rq_int_ena : 8; 1384 uint64_t qint_idx : 7; 1385 uint64_t rsvd_319_315 : 5; 1386 uint64_t ltag : 24; 1387 uint64_t good_utag : 8; 1388 uint64_t bad_utag : 8; 1389 uint64_t flow_tagw : 6; 1390 uint64_t rsvd_383_366 : 18; 1391 uint64_t octs : 48; 1392 uint64_t rsvd_447_432 : 16; 1393 uint64_t pkts : 48; 1394 uint64_t rsvd_511_496 : 16; 1395 uint64_t drop_octs : 48; 1396 uint64_t rsvd_575_560 : 16; 1397 uint64_t drop_pkts : 48; 1398 uint64_t rsvd_639_624 : 16; 1399 uint64_t re_pkts : 48; 1400 uint64_t rsvd_703_688 : 16; 1401 uint64_t rsvd_767_704 : 64; /* W11 */ 1402 uint64_t rsvd_831_768 : 64; /* W12 */ 1403 uint64_t rsvd_895_832 : 64; /* W13 */ 1404 uint64_t rsvd_959_896 : 64; /* W14 */ 1405 uint64_t rsvd_1023_960 : 64; /* W15 */ 1406 }; 1407 1408 /* NIX receive side scaling entry structure */ 1409 struct nix_rsse_s { 1410 uint32_t rq : 20; 1411 uint32_t rsvd_31_20 : 12; 1412 }; 1413 1414 /* NIX receive action structure */ 1415 struct nix_rx_action_s { 1416 uint64_t op : 4; 1417 uint64_t pf_func : 16; 1418 uint64_t index : 20; 1419 uint64_t match_id : 16; 1420 uint64_t flow_key_alg : 5; 1421 uint64_t rsvd_63_61 : 3; 1422 }; 1423 1424 /* NIX receive immediate sub descriptor structure */ 1425 struct nix_rx_imm_s { 1426 uint64_t size : 16; 1427 uint64_t apad : 3; 1428 uint64_t rsvd_59_19 : 41; 1429 uint64_t subdc : 4; 1430 }; 1431 1432 /* NIX receive multicast/mirror entry structure */ 1433 struct nix_rx_mce_s { 1434 uint64_t op : 2; 1435 uint64_t rsvd_2 : 1; 1436 uint64_t eol : 1; 1437 uint64_t index : 20; 1438 uint64_t rsvd_31_24 : 8; 1439 uint64_t pf_func : 16; 1440 uint64_t next : 16; 1441 }; 1442 1443 /* NIX receive parse structure */ 1444 union nix_rx_parse_u { 1445 struct { 1446 uint64_t chan : 12; 1447 uint64_t desc_sizem1 : 5; 1448 uint64_t imm_copy : 1; 1449 uint64_t express : 1; 1450 uint64_t wqwd : 1; 1451 uint64_t errlev : 4; 1452 uint64_t errcode : 8; 1453 uint64_t latype : 4; 1454 uint64_t lbtype : 4; 1455 uint64_t lctype : 4; 1456 uint64_t ldtype : 4; 1457 uint64_t letype : 4; 1458 uint64_t lftype : 4; 1459 uint64_t lgtype : 4; 1460 uint64_t lhtype : 4; 1461 uint64_t pkt_lenm1 : 16; 1462 uint64_t l2m : 1; 1463 uint64_t l2b : 1; 1464 uint64_t l3m : 1; 1465 uint64_t l3b : 1; 1466 uint64_t vtag0_valid : 1; 1467 uint64_t vtag0_gone : 1; 1468 uint64_t vtag1_valid : 1; 1469 uint64_t vtag1_gone : 1; 1470 uint64_t pkind : 6; 1471 uint64_t nix_idx : 2; 1472 uint64_t vtag0_tci : 16; 1473 uint64_t vtag1_tci : 16; 1474 uint64_t laflags : 8; 1475 uint64_t lbflags : 8; 1476 uint64_t lcflags : 8; 1477 uint64_t ldflags : 8; 1478 uint64_t leflags : 8; 1479 uint64_t lfflags : 8; 1480 uint64_t lgflags : 8; 1481 uint64_t lhflags : 8; 1482 uint64_t eoh_ptr : 8; 1483 uint64_t wqe_aura : 20; 1484 uint64_t pb_aura : 20; 1485 uint64_t match_id : 16; 1486 uint64_t laptr : 8; 1487 uint64_t lbptr : 8; 1488 uint64_t lcptr : 8; 1489 uint64_t ldptr : 8; 1490 uint64_t leptr : 8; 1491 uint64_t lfptr : 8; 1492 uint64_t lgptr : 8; 1493 uint64_t lhptr : 8; 1494 uint64_t vtag0_ptr : 8; 1495 uint64_t vtag1_ptr : 8; 1496 uint64_t flow_key_alg : 5; 1497 uint64_t rsvd_341 : 1; 1498 uint64_t rsvd_349_342 : 8; 1499 uint64_t rsvd_353_350 : 4; 1500 uint64_t rsvd_359_354 : 6; 1501 uint64_t color : 2; 1502 uint64_t rsvd_381_362 : 20; 1503 uint64_t rsvd_382 : 1; 1504 uint64_t rsvd_383 : 1; 1505 uint64_t rsvd_447_384 : 64; /* W6 */ 1506 }; 1507 struct { 1508 uint64_t chan : 12; 1509 uint64_t desc_sizem1 : 5; 1510 uint64_t imm_copy : 1; 1511 uint64_t express : 1; 1512 uint64_t wqwd : 1; 1513 uint64_t errlev : 4; 1514 uint64_t errcode : 8; 1515 uint64_t latype : 4; 1516 uint64_t lbtype : 4; 1517 uint64_t lctype : 4; 1518 uint64_t ldtype : 4; 1519 uint64_t letype : 4; 1520 uint64_t lftype : 4; 1521 uint64_t lgtype : 4; 1522 uint64_t lhtype : 4; 1523 uint64_t pkt_lenm1 : 16; 1524 uint64_t l2m : 1; 1525 uint64_t l2b : 1; 1526 uint64_t l3m : 1; 1527 uint64_t l3b : 1; 1528 uint64_t vtag0_valid : 1; 1529 uint64_t vtag0_gone : 1; 1530 uint64_t vtag1_valid : 1; 1531 uint64_t vtag1_gone : 1; 1532 uint64_t pkind : 6; 1533 uint64_t rsvd_95_94 : 2; 1534 uint64_t vtag0_tci : 16; 1535 uint64_t vtag1_tci : 16; 1536 uint64_t laflags : 8; 1537 uint64_t lbflags : 8; 1538 uint64_t lcflags : 8; 1539 uint64_t ldflags : 8; 1540 uint64_t leflags : 8; 1541 uint64_t lfflags : 8; 1542 uint64_t lgflags : 8; 1543 uint64_t lhflags : 8; 1544 uint64_t eoh_ptr : 8; 1545 uint64_t wqe_aura : 20; 1546 uint64_t pb_aura : 20; 1547 uint64_t match_id : 16; 1548 uint64_t laptr : 8; 1549 uint64_t lbptr : 8; 1550 uint64_t lcptr : 8; 1551 uint64_t ldptr : 8; 1552 uint64_t leptr : 8; 1553 uint64_t lfptr : 8; 1554 uint64_t lgptr : 8; 1555 uint64_t lhptr : 8; 1556 uint64_t vtag0_ptr : 8; 1557 uint64_t vtag1_ptr : 8; 1558 uint64_t flow_key_alg : 5; 1559 uint64_t rsvd_383_341 : 43; 1560 uint64_t rsvd_447_384 : 64; /* W6 */ 1561 } cn9k; 1562 }; 1563 1564 /* NIX receive scatter/gather sub descriptor structure */ 1565 struct nix_rx_sg_s { 1566 uint64_t seg1_size : 16; 1567 uint64_t seg2_size : 16; 1568 uint64_t seg3_size : 16; 1569 uint64_t segs : 2; 1570 uint64_t rsvd_59_50 : 10; 1571 uint64_t subdc : 4; 1572 }; 1573 1574 /* NIX receive vtag action structure */ 1575 union nix_rx_vtag_action_u { 1576 struct { 1577 uint64_t vtag0_relptr : 8; 1578 uint64_t vtag0_lid : 3; 1579 uint64_t sa_xor : 1; 1580 uint64_t vtag0_type : 3; 1581 uint64_t vtag0_valid : 1; 1582 uint64_t sa_lo : 16; 1583 uint64_t vtag1_relptr : 8; 1584 uint64_t vtag1_lid : 3; 1585 uint64_t rsvd_43 : 1; 1586 uint64_t vtag1_type : 3; 1587 uint64_t vtag1_valid : 1; 1588 uint64_t sa_hi : 16; 1589 }; 1590 struct { 1591 uint64_t vtag0_relptr : 8; 1592 uint64_t vtag0_lid : 3; 1593 uint64_t rsvd_11 : 1; 1594 uint64_t vtag0_type : 3; 1595 uint64_t vtag0_valid : 1; 1596 uint64_t rsvd_31_16 : 16; 1597 uint64_t vtag1_relptr : 8; 1598 uint64_t vtag1_lid : 3; 1599 uint64_t rsvd_43 : 1; 1600 uint64_t vtag1_type : 3; 1601 uint64_t vtag1_valid : 1; 1602 uint64_t rsvd_63_48 : 16; 1603 } cn9k; 1604 }; 1605 1606 /* NIX send completion structure */ 1607 struct nix_send_comp_s { 1608 uint64_t status : 8; 1609 uint64_t sqe_id : 16; 1610 uint64_t rsvd_63_24 : 40; 1611 }; 1612 1613 /* NIX send CRC sub descriptor structure */ 1614 struct nix_send_crc_s { 1615 uint64_t size : 16; 1616 uint64_t start : 16; 1617 uint64_t insert : 16; 1618 uint64_t rsvd_57_48 : 10; 1619 uint64_t alg : 2; 1620 uint64_t subdc : 4; 1621 uint64_t iv : 32; 1622 uint64_t rsvd_127_96 : 32; 1623 }; 1624 1625 /* NIX send extended header sub descriptor structure */ 1626 union nix_send_ext_w0_u { 1627 uint64_t u; 1628 struct { 1629 uint64_t lso_mps : 14; 1630 uint64_t lso : 1; 1631 uint64_t tstmp : 1; 1632 uint64_t lso_sb : 8; 1633 uint64_t lso_format : 5; 1634 uint64_t rsvd_31_29 : 3; 1635 uint64_t shp_chg : 9; 1636 uint64_t shp_dis : 1; 1637 uint64_t shp_ra : 2; 1638 uint64_t markptr : 8; 1639 uint64_t markform : 7; 1640 uint64_t mark_en : 1; 1641 uint64_t subdc : 4; 1642 }; 1643 }; 1644 1645 union nix_send_ext_w1_u { 1646 uint64_t u; 1647 struct { 1648 uint64_t vlan0_ins_ptr : 8; 1649 uint64_t vlan0_ins_tci : 16; 1650 uint64_t vlan1_ins_ptr : 8; 1651 uint64_t vlan1_ins_tci : 16; 1652 uint64_t vlan0_ins_ena : 1; 1653 uint64_t vlan1_ins_ena : 1; 1654 uint64_t init_color : 2; 1655 uint64_t rsvd_127_116 : 12; 1656 }; 1657 struct { 1658 uint64_t vlan0_ins_ptr : 8; 1659 uint64_t vlan0_ins_tci : 16; 1660 uint64_t vlan1_ins_ptr : 8; 1661 uint64_t vlan1_ins_tci : 16; 1662 uint64_t vlan0_ins_ena : 1; 1663 uint64_t vlan1_ins_ena : 1; 1664 uint64_t rsvd_127_114 : 14; 1665 } cn9k; 1666 }; 1667 1668 struct nix_send_ext_s { 1669 union nix_send_ext_w0_u w0; 1670 union nix_send_ext_w1_u w1; 1671 }; 1672 1673 /* NIX send header sub descriptor structure */ 1674 union nix_send_hdr_w0_u { 1675 uint64_t u; 1676 struct { 1677 uint64_t total : 18; 1678 uint64_t rsvd_18 : 1; 1679 uint64_t df : 1; 1680 uint64_t aura : 20; 1681 uint64_t sizem1 : 3; 1682 uint64_t pnc : 1; 1683 uint64_t sq : 20; 1684 }; 1685 }; 1686 1687 union nix_send_hdr_w1_u { 1688 uint64_t u; 1689 struct { 1690 uint64_t ol3ptr : 8; 1691 uint64_t ol4ptr : 8; 1692 uint64_t il3ptr : 8; 1693 uint64_t il4ptr : 8; 1694 uint64_t ol3type : 4; 1695 uint64_t ol4type : 4; 1696 uint64_t il3type : 4; 1697 uint64_t il4type : 4; 1698 uint64_t sqe_id : 16; 1699 }; 1700 }; 1701 1702 struct nix_send_hdr_s { 1703 union nix_send_hdr_w0_u w0; 1704 union nix_send_hdr_w1_u w1; 1705 }; 1706 1707 /* NIX send immediate sub descriptor structure */ 1708 struct nix_send_imm_s { 1709 uint64_t size : 16; 1710 uint64_t apad : 3; 1711 uint64_t rsvd_59_19 : 41; 1712 uint64_t subdc : 4; 1713 }; 1714 1715 /* NIX send jump sub descriptor structure */ 1716 struct nix_send_jump_s { 1717 uint64_t sizem1 : 7; 1718 uint64_t rsvd_13_7 : 7; 1719 uint64_t ld_type : 2; 1720 uint64_t aura : 20; 1721 uint64_t rsvd_58_36 : 23; 1722 uint64_t f : 1; 1723 uint64_t subdc : 4; 1724 uint64_t addr : 64; /* W1 */ 1725 }; 1726 1727 /* NIX send memory sub descriptor structure */ 1728 union nix_send_mem_w0_u { 1729 uint64_t u; 1730 struct { 1731 uint64_t offset : 16; 1732 uint64_t rsvd_51_16 : 36; 1733 uint64_t per_lso_seg : 1; 1734 uint64_t wmem : 1; 1735 uint64_t dsz : 2; 1736 uint64_t alg : 4; 1737 uint64_t subdc : 4; 1738 }; 1739 struct { 1740 uint64_t offset : 16; 1741 uint64_t rsvd_52_16 : 37; 1742 uint64_t wmem : 1; 1743 uint64_t dsz : 2; 1744 uint64_t alg : 4; 1745 uint64_t subdc : 4; 1746 } cn9k; 1747 }; 1748 1749 struct nix_send_mem_s { 1750 union nix_send_mem_w0_u w0; 1751 uint64_t addr : 64; /* W1 */ 1752 }; 1753 1754 /* NIX send scatter/gather sub descriptor structure */ 1755 union nix_send_sg2_s { 1756 uint64_t u; 1757 struct { 1758 uint64_t seg1_size : 16; 1759 uint64_t aura : 20; 1760 uint64_t i1 : 1; 1761 uint64_t fabs : 1; 1762 uint64_t foff : 8; 1763 uint64_t rsvd_57_46 : 12; 1764 uint64_t ld_type : 2; 1765 uint64_t subdc : 4; 1766 }; 1767 }; 1768 1769 union nix_send_sg_s { 1770 uint64_t u; 1771 struct { 1772 uint64_t seg1_size : 16; 1773 uint64_t seg2_size : 16; 1774 uint64_t seg3_size : 16; 1775 uint64_t segs : 2; 1776 uint64_t rsvd_54_50 : 5; 1777 uint64_t i1 : 1; 1778 uint64_t i2 : 1; 1779 uint64_t i3 : 1; 1780 uint64_t ld_type : 2; 1781 uint64_t subdc : 4; 1782 }; 1783 }; 1784 1785 /* NIX send work sub descriptor structure */ 1786 struct nix_send_work_s { 1787 uint64_t tag : 32; 1788 uint64_t tt : 2; 1789 uint64_t grp : 10; 1790 uint64_t rsvd_59_44 : 16; 1791 uint64_t subdc : 4; 1792 uint64_t addr : 64; /* W1 */ 1793 }; 1794 1795 /* [CN10K, .) NIX sq context hardware structure */ 1796 struct nix_cn10k_sq_ctx_hw_s { 1797 uint64_t ena : 1; 1798 uint64_t substream : 20; 1799 uint64_t max_sqe_size : 2; 1800 uint64_t sqe_way_mask : 16; 1801 uint64_t sqb_aura : 20; 1802 uint64_t gbl_rsvd1 : 5; 1803 uint64_t cq_id : 20; 1804 uint64_t cq_ena : 1; 1805 uint64_t qint_idx : 6; 1806 uint64_t gbl_rsvd2 : 1; 1807 uint64_t sq_int : 8; 1808 uint64_t sq_int_ena : 8; 1809 uint64_t xoff : 1; 1810 uint64_t sqe_stype : 2; 1811 uint64_t gbl_rsvd : 17; 1812 uint64_t head_sqb : 64; /* W2 */ 1813 uint64_t head_offset : 6; 1814 uint64_t sqb_dequeue_count : 16; 1815 uint64_t default_chan : 12; 1816 uint64_t sdp_mcast : 1; 1817 uint64_t sso_ena : 1; 1818 uint64_t dse_rsvd1 : 28; 1819 uint64_t sqb_enqueue_count : 16; 1820 uint64_t tail_offset : 6; 1821 uint64_t lmt_dis : 1; 1822 uint64_t smq_rr_weight : 14; 1823 uint64_t dnq_rsvd1 : 27; 1824 uint64_t tail_sqb : 64; /* W5 */ 1825 uint64_t next_sqb : 64; /* W6 */ 1826 uint64_t smq : 10; 1827 uint64_t smq_pend : 1; 1828 uint64_t smq_next_sq : 20; 1829 uint64_t smq_next_sq_vld : 1; 1830 uint64_t mnq_dis : 1; 1831 uint64_t scm1_rsvd2 : 31; 1832 uint64_t smenq_sqb : 64; /* W8 */ 1833 uint64_t smenq_offset : 6; 1834 uint64_t cq_limit : 8; 1835 uint64_t smq_rr_count : 32; 1836 uint64_t scm_lso_rem : 18; 1837 uint64_t smq_lso_segnum : 8; 1838 uint64_t vfi_lso_total : 18; 1839 uint64_t vfi_lso_sizem1 : 3; 1840 uint64_t vfi_lso_sb : 8; 1841 uint64_t vfi_lso_mps : 14; 1842 uint64_t vfi_lso_vlan0_ins_ena : 1; 1843 uint64_t vfi_lso_vlan1_ins_ena : 1; 1844 uint64_t vfi_lso_vld : 1; 1845 uint64_t smenq_next_sqb_vld : 1; 1846 uint64_t scm_dq_rsvd1 : 9; 1847 uint64_t smenq_next_sqb : 64; /* W11 */ 1848 uint64_t age_drop_octs : 32; 1849 uint64_t age_drop_pkts : 32; 1850 uint64_t drop_pkts : 48; 1851 uint64_t drop_octs_lsw : 16; 1852 uint64_t drop_octs_msw : 32; 1853 uint64_t pkts_lsw : 32; 1854 uint64_t pkts_msw : 16; 1855 uint64_t octs : 48; 1856 }; 1857 1858 /* NIX sq context hardware structure */ 1859 struct nix_sq_ctx_hw_s { 1860 uint64_t ena : 1; 1861 uint64_t substream : 20; 1862 uint64_t max_sqe_size : 2; 1863 uint64_t sqe_way_mask : 16; 1864 uint64_t sqb_aura : 20; 1865 uint64_t gbl_rsvd1 : 5; 1866 uint64_t cq_id : 20; 1867 uint64_t cq_ena : 1; 1868 uint64_t qint_idx : 6; 1869 uint64_t gbl_rsvd2 : 1; 1870 uint64_t sq_int : 8; 1871 uint64_t sq_int_ena : 8; 1872 uint64_t xoff : 1; 1873 uint64_t sqe_stype : 2; 1874 uint64_t gbl_rsvd : 17; 1875 uint64_t head_sqb : 64; /* W2 */ 1876 uint64_t head_offset : 6; 1877 uint64_t sqb_dequeue_count : 16; 1878 uint64_t default_chan : 12; 1879 uint64_t sdp_mcast : 1; 1880 uint64_t sso_ena : 1; 1881 uint64_t dse_rsvd1 : 28; 1882 uint64_t sqb_enqueue_count : 16; 1883 uint64_t tail_offset : 6; 1884 uint64_t lmt_dis : 1; 1885 uint64_t smq_rr_quantum : 24; 1886 uint64_t dnq_rsvd1 : 17; 1887 uint64_t tail_sqb : 64; /* W5 */ 1888 uint64_t next_sqb : 64; /* W6 */ 1889 uint64_t mnq_dis : 1; 1890 uint64_t smq : 9; 1891 uint64_t smq_pend : 1; 1892 uint64_t smq_next_sq : 20; 1893 uint64_t smq_next_sq_vld : 1; 1894 uint64_t scm1_rsvd2 : 32; 1895 uint64_t smenq_sqb : 64; /* W8 */ 1896 uint64_t smenq_offset : 6; 1897 uint64_t cq_limit : 8; 1898 uint64_t smq_rr_count : 25; 1899 uint64_t scm_lso_rem : 18; 1900 uint64_t scm_dq_rsvd0 : 7; 1901 uint64_t smq_lso_segnum : 8; 1902 uint64_t vfi_lso_total : 18; 1903 uint64_t vfi_lso_sizem1 : 3; 1904 uint64_t vfi_lso_sb : 8; 1905 uint64_t vfi_lso_mps : 14; 1906 uint64_t vfi_lso_vlan0_ins_ena : 1; 1907 uint64_t vfi_lso_vlan1_ins_ena : 1; 1908 uint64_t vfi_lso_vld : 1; 1909 uint64_t smenq_next_sqb_vld : 1; 1910 uint64_t scm_dq_rsvd1 : 9; 1911 uint64_t smenq_next_sqb : 64; /* W11 */ 1912 uint64_t seb_rsvd1 : 64; /* W12 */ 1913 uint64_t drop_pkts : 48; 1914 uint64_t drop_octs_lsw : 16; 1915 uint64_t drop_octs_msw : 32; 1916 uint64_t pkts_lsw : 32; 1917 uint64_t pkts_msw : 16; 1918 uint64_t octs : 48; 1919 }; 1920 1921 /* [CN10K, .) NIX Send queue context structure */ 1922 struct nix_cn10k_sq_ctx_s { 1923 uint64_t ena : 1; 1924 uint64_t qint_idx : 6; 1925 uint64_t substream : 20; 1926 uint64_t sdp_mcast : 1; 1927 uint64_t cq : 20; 1928 uint64_t sqe_way_mask : 16; 1929 uint64_t smq : 10; 1930 uint64_t cq_ena : 1; 1931 uint64_t xoff : 1; 1932 uint64_t sso_ena : 1; 1933 uint64_t smq_rr_weight : 14; 1934 uint64_t default_chan : 12; 1935 uint64_t sqb_count : 16; 1936 uint64_t rsvd_120_119 : 2; 1937 uint64_t smq_rr_count_lb : 7; 1938 uint64_t smq_rr_count_ub : 25; 1939 uint64_t sqb_aura : 20; 1940 uint64_t sq_int : 8; 1941 uint64_t sq_int_ena : 8; 1942 uint64_t sqe_stype : 2; 1943 uint64_t rsvd_191 : 1; 1944 uint64_t max_sqe_size : 2; 1945 uint64_t cq_limit : 8; 1946 uint64_t lmt_dis : 1; 1947 uint64_t mnq_dis : 1; 1948 uint64_t smq_next_sq : 20; 1949 uint64_t smq_lso_segnum : 8; 1950 uint64_t tail_offset : 6; 1951 uint64_t smenq_offset : 6; 1952 uint64_t head_offset : 6; 1953 uint64_t smenq_next_sqb_vld : 1; 1954 uint64_t smq_pend : 1; 1955 uint64_t smq_next_sq_vld : 1; 1956 uint64_t rsvd_255_253 : 3; 1957 uint64_t next_sqb : 64; /* W4 */ 1958 uint64_t tail_sqb : 64; /* W5 */ 1959 uint64_t smenq_sqb : 64; /* W6 */ 1960 uint64_t smenq_next_sqb : 64; /* W7 */ 1961 uint64_t head_sqb : 64; /* W8 */ 1962 uint64_t rsvd_583_576 : 8; 1963 uint64_t vfi_lso_total : 18; 1964 uint64_t vfi_lso_sizem1 : 3; 1965 uint64_t vfi_lso_sb : 8; 1966 uint64_t vfi_lso_mps : 14; 1967 uint64_t vfi_lso_vlan0_ins_ena : 1; 1968 uint64_t vfi_lso_vlan1_ins_ena : 1; 1969 uint64_t vfi_lso_vld : 1; 1970 uint64_t rsvd_639_630 : 10; 1971 uint64_t scm_lso_rem : 18; 1972 uint64_t rsvd_703_658 : 46; 1973 uint64_t octs : 48; 1974 uint64_t rsvd_767_752 : 16; 1975 uint64_t pkts : 48; 1976 uint64_t rsvd_831_816 : 16; 1977 uint64_t aged_drop_octs : 32; 1978 uint64_t aged_drop_pkts : 32; 1979 uint64_t drop_octs : 48; 1980 uint64_t rsvd_959_944 : 16; 1981 uint64_t drop_pkts : 48; 1982 uint64_t rsvd_1023_1008 : 16; 1983 }; 1984 1985 /* NIX send queue context structure */ 1986 struct nix_sq_ctx_s { 1987 uint64_t ena : 1; 1988 uint64_t qint_idx : 6; 1989 uint64_t substream : 20; 1990 uint64_t sdp_mcast : 1; 1991 uint64_t cq : 20; 1992 uint64_t sqe_way_mask : 16; 1993 uint64_t smq : 9; 1994 uint64_t cq_ena : 1; 1995 uint64_t xoff : 1; 1996 uint64_t sso_ena : 1; 1997 uint64_t smq_rr_quantum : 24; 1998 uint64_t default_chan : 12; 1999 uint64_t sqb_count : 16; 2000 uint64_t smq_rr_count : 25; 2001 uint64_t sqb_aura : 20; 2002 uint64_t sq_int : 8; 2003 uint64_t sq_int_ena : 8; 2004 uint64_t sqe_stype : 2; 2005 uint64_t rsvd_191 : 1; 2006 uint64_t max_sqe_size : 2; 2007 uint64_t cq_limit : 8; 2008 uint64_t lmt_dis : 1; 2009 uint64_t mnq_dis : 1; 2010 uint64_t smq_next_sq : 20; 2011 uint64_t smq_lso_segnum : 8; 2012 uint64_t tail_offset : 6; 2013 uint64_t smenq_offset : 6; 2014 uint64_t head_offset : 6; 2015 uint64_t smenq_next_sqb_vld : 1; 2016 uint64_t smq_pend : 1; 2017 uint64_t smq_next_sq_vld : 1; 2018 uint64_t rsvd_255_253 : 3; 2019 uint64_t next_sqb : 64; /* W4 */ 2020 uint64_t tail_sqb : 64; /* W5 */ 2021 uint64_t smenq_sqb : 64; /* W6 */ 2022 uint64_t smenq_next_sqb : 64; /* W7 */ 2023 uint64_t head_sqb : 64; /* W8 */ 2024 uint64_t rsvd_583_576 : 8; 2025 uint64_t vfi_lso_total : 18; 2026 uint64_t vfi_lso_sizem1 : 3; 2027 uint64_t vfi_lso_sb : 8; 2028 uint64_t vfi_lso_mps : 14; 2029 uint64_t vfi_lso_vlan0_ins_ena : 1; 2030 uint64_t vfi_lso_vlan1_ins_ena : 1; 2031 uint64_t vfi_lso_vld : 1; 2032 uint64_t rsvd_639_630 : 10; 2033 uint64_t scm_lso_rem : 18; 2034 uint64_t rsvd_703_658 : 46; 2035 uint64_t octs : 48; 2036 uint64_t rsvd_767_752 : 16; 2037 uint64_t pkts : 48; 2038 uint64_t rsvd_831_816 : 16; 2039 uint64_t rsvd_895_832 : 64; /* W13 */ 2040 uint64_t drop_octs : 48; 2041 uint64_t rsvd_959_944 : 16; 2042 uint64_t drop_pkts : 48; 2043 uint64_t rsvd_1023_1008 : 16; 2044 }; 2045 2046 /* NIX transmit action structure */ 2047 struct nix_tx_action_s { 2048 uint64_t op : 4; 2049 uint64_t rsvd_11_4 : 8; 2050 uint64_t index : 20; 2051 uint64_t match_id : 16; 2052 uint64_t rsvd_63_48 : 16; 2053 }; 2054 2055 /* NIX transmit vtag action structure */ 2056 struct nix_tx_vtag_action_s { 2057 uint64_t vtag0_relptr : 8; 2058 uint64_t vtag0_lid : 3; 2059 uint64_t rsvd_11 : 1; 2060 uint64_t vtag0_op : 2; 2061 uint64_t rsvd_15_14 : 2; 2062 uint64_t vtag0_def : 10; 2063 uint64_t rsvd_31_26 : 6; 2064 uint64_t vtag1_relptr : 8; 2065 uint64_t vtag1_lid : 3; 2066 uint64_t rsvd_43 : 1; 2067 uint64_t vtag1_op : 2; 2068 uint64_t rsvd_47_46 : 2; 2069 uint64_t vtag1_def : 10; 2070 uint64_t rsvd_63_58 : 6; 2071 }; 2072 2073 /* NIX work queue entry header structure */ 2074 struct nix_wqe_hdr_s { 2075 uint64_t tag : 32; 2076 uint64_t tt : 2; 2077 uint64_t grp : 10; 2078 uint64_t node : 2; 2079 uint64_t q : 14; 2080 uint64_t wqe_type : 4; 2081 }; 2082 2083 /* NIX Rx flow key algorithm field structure */ 2084 struct nix_rx_flowkey_alg { 2085 uint64_t key_offset : 6; 2086 uint64_t ln_mask : 1; 2087 uint64_t fn_mask : 1; 2088 uint64_t hdr_offset : 8; 2089 uint64_t bytesm1 : 5; 2090 uint64_t lid : 3; 2091 uint64_t reserved_24_24 : 1; 2092 uint64_t ena : 1; 2093 uint64_t sel_chan : 1; 2094 uint64_t ltype_mask : 4; 2095 uint64_t ltype_match : 4; 2096 uint64_t reserved_35_63 : 29; 2097 }; 2098 2099 /* NIX LSO format field structure */ 2100 struct nix_lso_format { 2101 uint64_t offset : 8; 2102 uint64_t layer : 2; 2103 uint64_t rsvd_10_11 : 2; 2104 uint64_t sizem1 : 2; 2105 uint64_t rsvd_14_15 : 2; 2106 uint64_t alg : 3; 2107 uint64_t rsvd_19_63 : 45; 2108 }; 2109 2110 #define NIX_LSO_FIELD_MAX (8) 2111 #define NIX_LSO_FIELD_ALG_MASK GENMASK(18, 16) 2112 #define NIX_LSO_FIELD_SZ_MASK GENMASK(13, 12) 2113 #define NIX_LSO_FIELD_LY_MASK GENMASK(9, 8) 2114 #define NIX_LSO_FIELD_OFF_MASK GENMASK(7, 0) 2115 2116 #define NIX_LSO_FIELD_MASK \ 2117 (NIX_LSO_FIELD_OFF_MASK | NIX_LSO_FIELD_LY_MASK | \ 2118 NIX_LSO_FIELD_SZ_MASK | NIX_LSO_FIELD_ALG_MASK) 2119 2120 #define NIX_CN9K_MAX_HW_FRS 9212UL 2121 #define NIX_LBK_MAX_HW_FRS 65535UL 2122 #define NIX_SDP_MAX_HW_FRS 65535UL 2123 #define NIX_SDP_16K_HW_FRS 16380UL 2124 #define NIX_RPM_MAX_HW_FRS 16380UL 2125 #define NIX_MIN_HW_FRS 40UL 2126 2127 /** NIX policer rate limits */ 2128 #define NIX_BPF_MAX_RATE_DIV_EXP 12 2129 #define NIX_BPF_MAX_RATE_EXPONENT 0x16 2130 #define NIX_BPF_MAX_RATE_MANTISSA 0xff 2131 2132 #define NIX_BPF_RATE_CONST 8000000000ULL 2133 2134 /* NIX rate calculation in Bits/Sec 2135 * PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA]) 2136 * << NIX_*_PIR[RATE_EXPONENT]) / 256 2137 * PIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT])) 2138 * 2139 * CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA]) 2140 * << NIX_*_CIR[RATE_EXPONENT]) / 256 2141 * CIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT])) 2142 */ 2143 #define NIX_BPF_RATE(policer_timeunit, exponent, mantissa, div_exp) \ 2144 ((NIX_BPF_RATE_CONST * ((256 + (mantissa)) << (exponent))) / \ 2145 (((1ull << (div_exp)) * 256 * policer_timeunit))) 2146 2147 #define NIX_BPF_DEFAULT_ADJUST_MANTISSA 511 2148 #define NIX_BPF_DEFAULT_ADJUST_EXPONENT 0 2149 2150 /** NIX burst limits */ 2151 #define NIX_BPF_MAX_BURST_EXPONENT 0xf 2152 #define NIX_BPF_MAX_BURST_MANTISSA 0xff 2153 2154 /* NIX burst calculation 2155 * PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA]) 2156 * << (NIX_*_PIR[BURST_EXPONENT] + 1)) 2157 * / 256 2158 * 2159 * CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA]) 2160 * << (NIX_*_CIR[BURST_EXPONENT] + 1)) 2161 * / 256 2162 */ 2163 #define NIX_BPF_BURST(exponent, mantissa) \ 2164 (((256 + (mantissa)) << ((exponent) + 1)) / 256) 2165 2166 /** Meter burst limits */ 2167 #define NIX_BPF_BURST_MIN NIX_BPF_BURST(0, 0) 2168 #define NIX_BPF_BURST_MAX \ 2169 NIX_BPF_BURST(NIX_BPF_MAX_BURST_EXPONENT, NIX_BPF_MAX_BURST_MANTISSA) 2170 2171 /* NIX rate limits */ 2172 #define NIX_TM_MAX_RATE_DIV_EXP 12 2173 #define NIX_TM_MAX_RATE_EXPONENT 0xf 2174 #define NIX_TM_MAX_RATE_MANTISSA 0xff 2175 2176 #define NIX_TM_SHAPER_RATE_CONST ((uint64_t)2E6) 2177 2178 /* NIX rate calculation in Bits/Sec 2179 * PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA]) 2180 * << NIX_*_PIR[RATE_EXPONENT]) / 256 2181 * PIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT])) 2182 * 2183 * CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA]) 2184 * << NIX_*_CIR[RATE_EXPONENT]) / 256 2185 * CIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT])) 2186 */ 2187 #define NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp) \ 2188 ((NIX_TM_SHAPER_RATE_CONST * ((256 + (mantissa)) << (exponent))) / \ 2189 (((1ull << (div_exp)) * 256))) 2190 2191 /* Rate limit in Bits/Sec */ 2192 #define NIX_TM_MIN_SHAPER_RATE NIX_TM_SHAPER_RATE(0, 0, NIX_TM_MAX_RATE_DIV_EXP) 2193 2194 #define NIX_TM_MAX_SHAPER_RATE \ 2195 NIX_TM_SHAPER_RATE(NIX_TM_MAX_RATE_EXPONENT, NIX_TM_MAX_RATE_MANTISSA, \ 2196 0) 2197 2198 #define NIX_TM_MIN_SHAPER_PPS_RATE 25 2199 #define NIX_TM_MAX_SHAPER_PPS_RATE (100ul << 20) 2200 2201 /* NIX burst limits */ 2202 #define NIX_TM_MAX_BURST_EXPONENT 0xful 2203 #define NIX_TM_MAX_BURST_MANTISSA 0x7ffful 2204 #define NIX_CN9K_TM_MAX_BURST_MANTISSA 0xfful 2205 2206 /* NIX burst calculation 2207 * PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA]) 2208 * << (NIX_*_PIR[BURST_EXPONENT] + 1)) 2209 * / 256 2210 * 2211 * CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA]) 2212 * << (NIX_*_CIR[BURST_EXPONENT] + 1)) 2213 * / 256 2214 */ 2215 #define NIX_TM_SHAPER_BURST(exponent, mantissa) \ 2216 (((256ul + (mantissa)) << ((exponent) + 1)) / 256ul) 2217 2218 /* Burst limit in Bytes */ 2219 #define NIX_TM_MIN_SHAPER_BURST NIX_TM_SHAPER_BURST(0, 0) 2220 2221 #define NIX_TM_MAX_SHAPER_BURST \ 2222 NIX_TM_SHAPER_BURST(NIX_TM_MAX_BURST_EXPONENT, \ 2223 NIX_TM_MAX_BURST_MANTISSA) 2224 2225 #define NIX_CN9K_TM_MAX_SHAPER_BURST \ 2226 NIX_TM_SHAPER_BURST(NIX_TM_MAX_BURST_EXPONENT, \ 2227 NIX_CN9K_TM_MAX_BURST_MANTISSA) 2228 2229 /* Min is limited so that NIX_AF_SMQX_CFG[MINLEN]+ADJUST is not -ve */ 2230 #define NIX_TM_LENGTH_ADJUST_MIN ((int)-NIX_MIN_HW_FRS + 1) 2231 #define NIX_TM_LENGTH_ADJUST_MAX 255 2232 2233 #define NIX_TM_TLX_SP_PRIO_MAX 10 2234 #define NIX_CN9K_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1) 2235 #define NIX_TM_RR_WEIGHT_MAX (BIT_ULL(14) - 1) 2236 2237 /* [CN9K, CN10K) */ 2238 #define NIX_CN9K_TXSCH_LVL_SMQ_MAX 512 2239 2240 /* [CN10K, .) */ 2241 #define NIX_TXSCH_LVL_SMQ_MAX 832 2242 2243 /* [CN9K, .) */ 2244 #define NIX_TXSCH_LVL_TL4_MAX 512 2245 #define NIX_TXSCH_LVL_TL3_MAX 256 2246 #define NIX_TXSCH_LVL_TL2_MAX 256 2247 #define NIX_TXSCH_LVL_TL1_MAX 28 2248 2249 #define NIX_CQ_OP_STAT_OP_ERR 63 2250 #define NIX_CQ_OP_STAT_CQ_ERR 46 2251 2252 #define NIX_RQ_CN10K_SPB_MAX_SIZE 4096 2253 2254 /* [CN9K, .) */ 2255 #define NIX_LSO_SEG_MAX 256 2256 #define NIX_LSO_MPS_MAX (BIT_ULL(14) - 1) 2257 2258 /* Software defined LSO base format IDX */ 2259 #define NIX_LSO_FORMAT_IDX_TSOV4 0 2260 #define NIX_LSO_FORMAT_IDX_TSOV6 1 2261 2262 /* [CN10K, .) */ 2263 #define NIX_SENDSTATALG_MASK 0x7 2264 #define NIX_SENDSTATALG_SEL_MASK 0x8 2265 #define NIX_SENDSTAT_IOFFSET_MASK 0xFFF 2266 #define NIX_SENDSTAT_OOFFSET_MASK 0xFFF 2267 2268 #endif /* __NIX_HW_H__ */ 2269