15566a3e3SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
25566a3e3SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation
3c752998bSGaetan Rivet */
4c752998bSGaetan Rivet
5c752998bSGaetan Rivet #include <string.h>
6c752998bSGaetan Rivet #include <dirent.h>
7c752998bSGaetan Rivet
8c752998bSGaetan Rivet #include <rte_log.h>
9c752998bSGaetan Rivet #include <rte_pci.h>
10c752998bSGaetan Rivet #include <rte_bus_pci.h>
11c752998bSGaetan Rivet #include <rte_malloc.h>
12c752998bSGaetan Rivet #include <rte_devargs.h>
13c752998bSGaetan Rivet #include <rte_memcpy.h>
14c752998bSGaetan Rivet #include <rte_vfio.h>
15c752998bSGaetan Rivet
16c752998bSGaetan Rivet #include "eal_filesystem.h"
17c752998bSGaetan Rivet
18c752998bSGaetan Rivet #include "private.h"
19c752998bSGaetan Rivet #include "pci_init.h"
20c752998bSGaetan Rivet
21c752998bSGaetan Rivet /**
22c752998bSGaetan Rivet * @file
23aa777f00SThomas Monjalon * PCI probing using Linux sysfs.
24c752998bSGaetan Rivet */
25c752998bSGaetan Rivet
26c752998bSGaetan Rivet static int
pci_get_kernel_driver_by_path(const char * filename,char * dri_name,size_t len)2752f711f7SAndy Green pci_get_kernel_driver_by_path(const char *filename, char *dri_name,
2852f711f7SAndy Green size_t len)
29c752998bSGaetan Rivet {
30c752998bSGaetan Rivet int count;
31c752998bSGaetan Rivet char path[PATH_MAX];
32c752998bSGaetan Rivet char *name;
33c752998bSGaetan Rivet
34c752998bSGaetan Rivet if (!filename || !dri_name)
35c752998bSGaetan Rivet return -1;
36c752998bSGaetan Rivet
37c752998bSGaetan Rivet count = readlink(filename, path, PATH_MAX);
38c752998bSGaetan Rivet if (count >= PATH_MAX)
39c752998bSGaetan Rivet return -1;
40c752998bSGaetan Rivet
41c752998bSGaetan Rivet /* For device does not have a driver */
42c752998bSGaetan Rivet if (count < 0)
43c752998bSGaetan Rivet return 1;
44c752998bSGaetan Rivet
45c752998bSGaetan Rivet path[count] = '\0';
46c752998bSGaetan Rivet
47c752998bSGaetan Rivet name = strrchr(path, '/');
48c752998bSGaetan Rivet if (name) {
4952f711f7SAndy Green strlcpy(dri_name, name + 1, len);
50c752998bSGaetan Rivet return 0;
51c752998bSGaetan Rivet }
52c752998bSGaetan Rivet
53c752998bSGaetan Rivet return -1;
54c752998bSGaetan Rivet }
55c752998bSGaetan Rivet
56c752998bSGaetan Rivet /* Map pci device */
57c752998bSGaetan Rivet int
rte_pci_map_device(struct rte_pci_device * dev)58c752998bSGaetan Rivet rte_pci_map_device(struct rte_pci_device *dev)
59c752998bSGaetan Rivet {
60c752998bSGaetan Rivet int ret = -1;
61c752998bSGaetan Rivet
62c752998bSGaetan Rivet /* try mapping the NIC resources using VFIO if it exists */
63c752998bSGaetan Rivet switch (dev->kdrv) {
647c0d798aSDavid Marchand case RTE_PCI_KDRV_VFIO:
65c752998bSGaetan Rivet #ifdef VFIO_PRESENT
66c752998bSGaetan Rivet if (pci_vfio_is_enabled())
67c752998bSGaetan Rivet ret = pci_vfio_map_resource(dev);
68c752998bSGaetan Rivet #endif
69c752998bSGaetan Rivet break;
707c0d798aSDavid Marchand case RTE_PCI_KDRV_IGB_UIO:
717c0d798aSDavid Marchand case RTE_PCI_KDRV_UIO_GENERIC:
72c752998bSGaetan Rivet if (rte_eal_using_phys_addrs()) {
73c752998bSGaetan Rivet /* map resources for devices that use uio */
74c752998bSGaetan Rivet ret = pci_uio_map_resource(dev);
75c752998bSGaetan Rivet }
76c752998bSGaetan Rivet break;
77c752998bSGaetan Rivet default:
78*849f773bSDavid Marchand PCI_LOG(DEBUG, " Not managed by a supported kernel driver, skipped");
79c752998bSGaetan Rivet ret = 1;
80c752998bSGaetan Rivet break;
81c752998bSGaetan Rivet }
82c752998bSGaetan Rivet
83c752998bSGaetan Rivet return ret;
84c752998bSGaetan Rivet }
85c752998bSGaetan Rivet
86c752998bSGaetan Rivet /* Unmap pci device */
87c752998bSGaetan Rivet void
rte_pci_unmap_device(struct rte_pci_device * dev)88c752998bSGaetan Rivet rte_pci_unmap_device(struct rte_pci_device *dev)
89c752998bSGaetan Rivet {
90c752998bSGaetan Rivet /* try unmapping the NIC resources using VFIO if it exists */
91c752998bSGaetan Rivet switch (dev->kdrv) {
927c0d798aSDavid Marchand case RTE_PCI_KDRV_VFIO:
93c752998bSGaetan Rivet #ifdef VFIO_PRESENT
94c752998bSGaetan Rivet if (pci_vfio_is_enabled())
95c752998bSGaetan Rivet pci_vfio_unmap_resource(dev);
96c752998bSGaetan Rivet #endif
97c752998bSGaetan Rivet break;
987c0d798aSDavid Marchand case RTE_PCI_KDRV_IGB_UIO:
997c0d798aSDavid Marchand case RTE_PCI_KDRV_UIO_GENERIC:
100c752998bSGaetan Rivet /* unmap resources for devices that use uio */
101c752998bSGaetan Rivet pci_uio_unmap_resource(dev);
102c752998bSGaetan Rivet break;
103c752998bSGaetan Rivet default:
104*849f773bSDavid Marchand PCI_LOG(DEBUG, " Not managed by a supported kernel driver, skipped");
105c752998bSGaetan Rivet break;
106c752998bSGaetan Rivet }
107c752998bSGaetan Rivet }
108c752998bSGaetan Rivet
1097411d032SAnatoly Burakov static int
find_max_end_va(const struct rte_memseg_list * msl,void * arg)11066cc45e2SAnatoly Burakov find_max_end_va(const struct rte_memseg_list *msl, void *arg)
1117411d032SAnatoly Burakov {
1124104b2a4SAnatoly Burakov size_t sz = msl->len;
11366cc45e2SAnatoly Burakov void *end_va = RTE_PTR_ADD(msl->base_va, sz);
1147411d032SAnatoly Burakov void **max_va = arg;
1157411d032SAnatoly Burakov
1167411d032SAnatoly Burakov if (*max_va < end_va)
1177411d032SAnatoly Burakov *max_va = end_va;
1187411d032SAnatoly Burakov return 0;
1197411d032SAnatoly Burakov }
1207411d032SAnatoly Burakov
121c752998bSGaetan Rivet void *
pci_find_max_end_va(void)122c752998bSGaetan Rivet pci_find_max_end_va(void)
123c752998bSGaetan Rivet {
1247411d032SAnatoly Burakov void *va = NULL;
125c752998bSGaetan Rivet
12666cc45e2SAnatoly Burakov rte_memseg_list_walk(find_max_end_va, &va);
1277411d032SAnatoly Burakov return va;
128c752998bSGaetan Rivet }
129c752998bSGaetan Rivet
13066cc45e2SAnatoly Burakov
131c752998bSGaetan Rivet /* parse one line of the "resource" sysfs file (note that the 'line'
132c752998bSGaetan Rivet * string is modified)
133c752998bSGaetan Rivet */
134c752998bSGaetan Rivet int
pci_parse_one_sysfs_resource(char * line,size_t len,uint64_t * phys_addr,uint64_t * end_addr,uint64_t * flags)135c752998bSGaetan Rivet pci_parse_one_sysfs_resource(char *line, size_t len, uint64_t *phys_addr,
136c752998bSGaetan Rivet uint64_t *end_addr, uint64_t *flags)
137c752998bSGaetan Rivet {
138c752998bSGaetan Rivet union pci_resource_info {
139c752998bSGaetan Rivet struct {
140c752998bSGaetan Rivet char *phys_addr;
141c752998bSGaetan Rivet char *end_addr;
142c752998bSGaetan Rivet char *flags;
143c752998bSGaetan Rivet };
144c752998bSGaetan Rivet char *ptrs[PCI_RESOURCE_FMT_NVAL];
145c752998bSGaetan Rivet } res_info;
146c752998bSGaetan Rivet
147c752998bSGaetan Rivet if (rte_strsplit(line, len, res_info.ptrs, 3, ' ') != 3) {
148*849f773bSDavid Marchand PCI_LOG(ERR, "%s(): bad resource format", __func__);
149c752998bSGaetan Rivet return -1;
150c752998bSGaetan Rivet }
151c752998bSGaetan Rivet errno = 0;
152c752998bSGaetan Rivet *phys_addr = strtoull(res_info.phys_addr, NULL, 16);
153c752998bSGaetan Rivet *end_addr = strtoull(res_info.end_addr, NULL, 16);
154c752998bSGaetan Rivet *flags = strtoull(res_info.flags, NULL, 16);
155c752998bSGaetan Rivet if (errno != 0) {
156*849f773bSDavid Marchand PCI_LOG(ERR, "%s(): bad resource format", __func__);
157c752998bSGaetan Rivet return -1;
158c752998bSGaetan Rivet }
159c752998bSGaetan Rivet
160c752998bSGaetan Rivet return 0;
161c752998bSGaetan Rivet }
162c752998bSGaetan Rivet
163c752998bSGaetan Rivet /* parse the "resource" sysfs file */
164c752998bSGaetan Rivet static int
pci_parse_sysfs_resource(const char * filename,struct rte_pci_device * dev)165c752998bSGaetan Rivet pci_parse_sysfs_resource(const char *filename, struct rte_pci_device *dev)
166c752998bSGaetan Rivet {
167c752998bSGaetan Rivet FILE *f;
168c752998bSGaetan Rivet char buf[BUFSIZ];
169c752998bSGaetan Rivet int i;
170c752998bSGaetan Rivet uint64_t phys_addr, end_addr, flags;
171c752998bSGaetan Rivet
172c752998bSGaetan Rivet f = fopen(filename, "r");
173c752998bSGaetan Rivet if (f == NULL) {
174*849f773bSDavid Marchand PCI_LOG(ERR, "Cannot open sysfs resource");
175c752998bSGaetan Rivet return -1;
176c752998bSGaetan Rivet }
177c752998bSGaetan Rivet
178c752998bSGaetan Rivet for (i = 0; i<PCI_MAX_RESOURCE; i++) {
179c752998bSGaetan Rivet
180c752998bSGaetan Rivet if (fgets(buf, sizeof(buf), f) == NULL) {
181*849f773bSDavid Marchand PCI_LOG(ERR, "%s(): cannot read resource", __func__);
182c752998bSGaetan Rivet goto error;
183c752998bSGaetan Rivet }
184c752998bSGaetan Rivet if (pci_parse_one_sysfs_resource(buf, sizeof(buf), &phys_addr,
185c752998bSGaetan Rivet &end_addr, &flags) < 0)
186c752998bSGaetan Rivet goto error;
187c752998bSGaetan Rivet
188c752998bSGaetan Rivet if (flags & IORESOURCE_MEM) {
189c752998bSGaetan Rivet dev->mem_resource[i].phys_addr = phys_addr;
190c752998bSGaetan Rivet dev->mem_resource[i].len = end_addr - phys_addr + 1;
191c752998bSGaetan Rivet /* not mapped for now */
192c752998bSGaetan Rivet dev->mem_resource[i].addr = NULL;
193c752998bSGaetan Rivet }
194c752998bSGaetan Rivet }
195c752998bSGaetan Rivet fclose(f);
196c752998bSGaetan Rivet return 0;
197c752998bSGaetan Rivet
198c752998bSGaetan Rivet error:
199c752998bSGaetan Rivet fclose(f);
200c752998bSGaetan Rivet return -1;
201c752998bSGaetan Rivet }
202c752998bSGaetan Rivet
203c752998bSGaetan Rivet /* Scan one pci sysfs entry, and fill the devices list from it. */
204c752998bSGaetan Rivet static int
pci_scan_one(const char * dirname,const struct rte_pci_addr * addr)205c752998bSGaetan Rivet pci_scan_one(const char *dirname, const struct rte_pci_addr *addr)
206c752998bSGaetan Rivet {
207c752998bSGaetan Rivet char filename[PATH_MAX];
208c752998bSGaetan Rivet unsigned long tmp;
20987a02023SChenbo Xia struct rte_pci_device_internal *pdev;
210c752998bSGaetan Rivet struct rte_pci_device *dev;
211c752998bSGaetan Rivet char driver[PATH_MAX];
212c752998bSGaetan Rivet int ret;
213c752998bSGaetan Rivet
21487a02023SChenbo Xia pdev = malloc(sizeof(*pdev));
21587a02023SChenbo Xia if (pdev == NULL) {
216*849f773bSDavid Marchand PCI_LOG(ERR, "Cannot allocate memory for internal pci device");
217c752998bSGaetan Rivet return -1;
21887a02023SChenbo Xia }
219c752998bSGaetan Rivet
22087a02023SChenbo Xia memset(pdev, 0, sizeof(*pdev));
22187a02023SChenbo Xia dev = &pdev->device;
2226844d146SThomas Monjalon dev->device.bus = &rte_pci_bus.bus;
223c752998bSGaetan Rivet dev->addr = *addr;
224c752998bSGaetan Rivet
225c752998bSGaetan Rivet /* get vendor id */
226c752998bSGaetan Rivet snprintf(filename, sizeof(filename), "%s/vendor", dirname);
227c752998bSGaetan Rivet if (eal_parse_sysfs_value(filename, &tmp) < 0) {
22887a02023SChenbo Xia pci_free(pdev);
229c752998bSGaetan Rivet return -1;
230c752998bSGaetan Rivet }
231c752998bSGaetan Rivet dev->id.vendor_id = (uint16_t)tmp;
232c752998bSGaetan Rivet
233c752998bSGaetan Rivet /* get device id */
234c752998bSGaetan Rivet snprintf(filename, sizeof(filename), "%s/device", dirname);
235c752998bSGaetan Rivet if (eal_parse_sysfs_value(filename, &tmp) < 0) {
23687a02023SChenbo Xia pci_free(pdev);
237c752998bSGaetan Rivet return -1;
238c752998bSGaetan Rivet }
239c752998bSGaetan Rivet dev->id.device_id = (uint16_t)tmp;
240c752998bSGaetan Rivet
241c752998bSGaetan Rivet /* get subsystem_vendor id */
242c752998bSGaetan Rivet snprintf(filename, sizeof(filename), "%s/subsystem_vendor",
243c752998bSGaetan Rivet dirname);
244c752998bSGaetan Rivet if (eal_parse_sysfs_value(filename, &tmp) < 0) {
24587a02023SChenbo Xia pci_free(pdev);
246c752998bSGaetan Rivet return -1;
247c752998bSGaetan Rivet }
248c752998bSGaetan Rivet dev->id.subsystem_vendor_id = (uint16_t)tmp;
249c752998bSGaetan Rivet
250c752998bSGaetan Rivet /* get subsystem_device id */
251c752998bSGaetan Rivet snprintf(filename, sizeof(filename), "%s/subsystem_device",
252c752998bSGaetan Rivet dirname);
253c752998bSGaetan Rivet if (eal_parse_sysfs_value(filename, &tmp) < 0) {
25487a02023SChenbo Xia pci_free(pdev);
255c752998bSGaetan Rivet return -1;
256c752998bSGaetan Rivet }
257c752998bSGaetan Rivet dev->id.subsystem_device_id = (uint16_t)tmp;
258c752998bSGaetan Rivet
259c752998bSGaetan Rivet /* get class_id */
260c752998bSGaetan Rivet snprintf(filename, sizeof(filename), "%s/class",
261c752998bSGaetan Rivet dirname);
262c752998bSGaetan Rivet if (eal_parse_sysfs_value(filename, &tmp) < 0) {
26387a02023SChenbo Xia pci_free(pdev);
264c752998bSGaetan Rivet return -1;
265c752998bSGaetan Rivet }
266c752998bSGaetan Rivet /* the least 24 bits are valid: class, subclass, program interface */
267c752998bSGaetan Rivet dev->id.class_id = (uint32_t)tmp & RTE_CLASS_ANY_ID;
268c752998bSGaetan Rivet
269c752998bSGaetan Rivet /* get max_vfs */
270c752998bSGaetan Rivet dev->max_vfs = 0;
271c752998bSGaetan Rivet snprintf(filename, sizeof(filename), "%s/max_vfs", dirname);
272c752998bSGaetan Rivet if (!access(filename, F_OK) &&
273c752998bSGaetan Rivet eal_parse_sysfs_value(filename, &tmp) == 0)
274c752998bSGaetan Rivet dev->max_vfs = (uint16_t)tmp;
275c752998bSGaetan Rivet else {
276c752998bSGaetan Rivet /* for non igb_uio driver, need kernel version >= 3.8 */
277c752998bSGaetan Rivet snprintf(filename, sizeof(filename),
278c752998bSGaetan Rivet "%s/sriov_numvfs", dirname);
279c752998bSGaetan Rivet if (!access(filename, F_OK) &&
280c752998bSGaetan Rivet eal_parse_sysfs_value(filename, &tmp) == 0)
281c752998bSGaetan Rivet dev->max_vfs = (uint16_t)tmp;
282c752998bSGaetan Rivet }
283c752998bSGaetan Rivet
284c752998bSGaetan Rivet /* get numa node, default to 0 if not present */
2857dcd73e3SOlivier Matz snprintf(filename, sizeof(filename), "%s/numa_node", dirname);
286c752998bSGaetan Rivet
2877dcd73e3SOlivier Matz if (access(filename, F_OK) == 0 &&
2887dcd73e3SOlivier Matz eal_parse_sysfs_value(filename, &tmp) == 0)
289c752998bSGaetan Rivet dev->device.numa_node = tmp;
290c752998bSGaetan Rivet else
2917dcd73e3SOlivier Matz dev->device.numa_node = SOCKET_ID_ANY;
292c752998bSGaetan Rivet
2938f4de2dbSDavid Marchand pci_common_set(dev);
294c752998bSGaetan Rivet
295c752998bSGaetan Rivet /* parse resources */
296c752998bSGaetan Rivet snprintf(filename, sizeof(filename), "%s/resource", dirname);
297c752998bSGaetan Rivet if (pci_parse_sysfs_resource(filename, dev) < 0) {
298*849f773bSDavid Marchand PCI_LOG(ERR, "%s(): cannot parse resource", __func__);
29987a02023SChenbo Xia pci_free(pdev);
300c752998bSGaetan Rivet return -1;
301c752998bSGaetan Rivet }
302c752998bSGaetan Rivet
303c752998bSGaetan Rivet /* parse driver */
304c752998bSGaetan Rivet snprintf(filename, sizeof(filename), "%s/driver", dirname);
30552f711f7SAndy Green ret = pci_get_kernel_driver_by_path(filename, driver, sizeof(driver));
306c752998bSGaetan Rivet if (ret < 0) {
307*849f773bSDavid Marchand PCI_LOG(ERR, "Fail to get kernel driver");
30887a02023SChenbo Xia pci_free(pdev);
309c752998bSGaetan Rivet return -1;
310c752998bSGaetan Rivet }
311c752998bSGaetan Rivet
312c752998bSGaetan Rivet if (!ret) {
313c752998bSGaetan Rivet if (!strcmp(driver, "vfio-pci"))
3147c0d798aSDavid Marchand dev->kdrv = RTE_PCI_KDRV_VFIO;
315c752998bSGaetan Rivet else if (!strcmp(driver, "igb_uio"))
3167c0d798aSDavid Marchand dev->kdrv = RTE_PCI_KDRV_IGB_UIO;
317c752998bSGaetan Rivet else if (!strcmp(driver, "uio_pci_generic"))
3187c0d798aSDavid Marchand dev->kdrv = RTE_PCI_KDRV_UIO_GENERIC;
319c752998bSGaetan Rivet else
3207c0d798aSDavid Marchand dev->kdrv = RTE_PCI_KDRV_UNKNOWN;
321c79a1c67SJerin Jacob } else {
32287a02023SChenbo Xia pci_free(pdev);
323c79a1c67SJerin Jacob return 0;
324c79a1c67SJerin Jacob }
325c752998bSGaetan Rivet /* device is valid, add in list (sorted) */
326c752998bSGaetan Rivet if (TAILQ_EMPTY(&rte_pci_bus.device_list)) {
327c752998bSGaetan Rivet rte_pci_add_device(dev);
328c752998bSGaetan Rivet } else {
329c752998bSGaetan Rivet struct rte_pci_device *dev2;
330c752998bSGaetan Rivet int ret;
331c752998bSGaetan Rivet
332c752998bSGaetan Rivet TAILQ_FOREACH(dev2, &rte_pci_bus.device_list, next) {
3330e3ef055SGaetan Rivet ret = rte_pci_addr_cmp(&dev->addr, &dev2->addr);
334c752998bSGaetan Rivet if (ret > 0)
335c752998bSGaetan Rivet continue;
336c752998bSGaetan Rivet
337c752998bSGaetan Rivet if (ret < 0) {
338c752998bSGaetan Rivet rte_pci_insert_device(dev2, dev);
339c752998bSGaetan Rivet } else { /* already registered */
34055e411b3SQi Zhang if (!rte_dev_is_probed(&dev2->device)) {
341c752998bSGaetan Rivet dev2->kdrv = dev->kdrv;
342c752998bSGaetan Rivet dev2->max_vfs = dev->max_vfs;
3439d3ad80aSJim Harris dev2->id = dev->id;
3448f4de2dbSDavid Marchand pci_common_set(dev2);
34555e411b3SQi Zhang memmove(dev2->mem_resource,
34655e411b3SQi Zhang dev->mem_resource,
347c752998bSGaetan Rivet sizeof(dev->mem_resource));
34855e411b3SQi Zhang } else {
34955e411b3SQi Zhang /**
35055e411b3SQi Zhang * If device is plugged and driver is
35155e411b3SQi Zhang * probed already, (This happens when
35255e411b3SQi Zhang * we call rte_dev_probe which will
35355e411b3SQi Zhang * scan all device on the bus) we don't
35455e411b3SQi Zhang * need to do anything here unless...
35555e411b3SQi Zhang **/
35655e411b3SQi Zhang if (dev2->kdrv != dev->kdrv ||
3579d3ad80aSJim Harris dev2->max_vfs != dev->max_vfs ||
3589d3ad80aSJim Harris memcmp(&dev2->id, &dev->id, sizeof(dev2->id)))
35955e411b3SQi Zhang /*
36055e411b3SQi Zhang * This should not happens.
36155e411b3SQi Zhang * But it is still possible if
36255e411b3SQi Zhang * we unbind a device from
36355e411b3SQi Zhang * vfio or uio before hotplug
36455e411b3SQi Zhang * remove and rebind it with
36555e411b3SQi Zhang * a different configure.
36655e411b3SQi Zhang * So we just print out the
36755e411b3SQi Zhang * error as an alarm.
36855e411b3SQi Zhang */
369*849f773bSDavid Marchand PCI_LOG(ERR, "Unexpected device scan at %s!",
37055e411b3SQi Zhang filename);
371fc67ae91SSomnath Kotur else if (dev2->device.devargs !=
372fc67ae91SSomnath Kotur dev->device.devargs) {
373fc67ae91SSomnath Kotur rte_devargs_remove(dev2->device.devargs);
3748f4de2dbSDavid Marchand pci_common_set(dev2);
375fc67ae91SSomnath Kotur }
37655e411b3SQi Zhang }
37787a02023SChenbo Xia pci_free(pdev);
378c752998bSGaetan Rivet }
379c752998bSGaetan Rivet return 0;
380c752998bSGaetan Rivet }
381c752998bSGaetan Rivet
382c752998bSGaetan Rivet rte_pci_add_device(dev);
383c752998bSGaetan Rivet }
384c752998bSGaetan Rivet
385c752998bSGaetan Rivet return 0;
386c752998bSGaetan Rivet }
387c752998bSGaetan Rivet
388c752998bSGaetan Rivet /*
389c752998bSGaetan Rivet * split up a pci address into its constituent parts.
390c752998bSGaetan Rivet */
391c752998bSGaetan Rivet static int
parse_pci_addr_format(const char * buf,int bufsize,struct rte_pci_addr * addr)392c752998bSGaetan Rivet parse_pci_addr_format(const char *buf, int bufsize, struct rte_pci_addr *addr)
393c752998bSGaetan Rivet {
394c752998bSGaetan Rivet /* first split on ':' */
395c752998bSGaetan Rivet union splitaddr {
396c752998bSGaetan Rivet struct {
397c752998bSGaetan Rivet char *domain;
398c752998bSGaetan Rivet char *bus;
399c752998bSGaetan Rivet char *devid;
400c752998bSGaetan Rivet char *function;
401c752998bSGaetan Rivet };
402c752998bSGaetan Rivet char *str[PCI_FMT_NVAL]; /* last element-separator is "." not ":" */
403c752998bSGaetan Rivet } splitaddr;
404c752998bSGaetan Rivet
405c752998bSGaetan Rivet char *buf_copy = strndup(buf, bufsize);
406c752998bSGaetan Rivet if (buf_copy == NULL)
407c752998bSGaetan Rivet return -1;
408c752998bSGaetan Rivet
409c752998bSGaetan Rivet if (rte_strsplit(buf_copy, bufsize, splitaddr.str, PCI_FMT_NVAL, ':')
410c752998bSGaetan Rivet != PCI_FMT_NVAL - 1)
411c752998bSGaetan Rivet goto error;
412c752998bSGaetan Rivet /* final split is on '.' between devid and function */
413c752998bSGaetan Rivet splitaddr.function = strchr(splitaddr.devid,'.');
414c752998bSGaetan Rivet if (splitaddr.function == NULL)
415c752998bSGaetan Rivet goto error;
416c752998bSGaetan Rivet *splitaddr.function++ = '\0';
417c752998bSGaetan Rivet
418c752998bSGaetan Rivet /* now convert to int values */
419c752998bSGaetan Rivet errno = 0;
420c752998bSGaetan Rivet addr->domain = strtoul(splitaddr.domain, NULL, 16);
421c752998bSGaetan Rivet addr->bus = strtoul(splitaddr.bus, NULL, 16);
422c752998bSGaetan Rivet addr->devid = strtoul(splitaddr.devid, NULL, 16);
423c752998bSGaetan Rivet addr->function = strtoul(splitaddr.function, NULL, 10);
424c752998bSGaetan Rivet if (errno != 0)
425c752998bSGaetan Rivet goto error;
426c752998bSGaetan Rivet
427c752998bSGaetan Rivet free(buf_copy); /* free the copy made with strdup */
428c752998bSGaetan Rivet return 0;
429c752998bSGaetan Rivet error:
430c752998bSGaetan Rivet free(buf_copy);
431c752998bSGaetan Rivet return -1;
432c752998bSGaetan Rivet }
433c752998bSGaetan Rivet
434c752998bSGaetan Rivet /*
435c752998bSGaetan Rivet * Scan the content of the PCI bus, and the devices in the devices
436c752998bSGaetan Rivet * list
437c752998bSGaetan Rivet */
438c752998bSGaetan Rivet int
rte_pci_scan(void)439c752998bSGaetan Rivet rte_pci_scan(void)
440c752998bSGaetan Rivet {
441c752998bSGaetan Rivet struct dirent *e;
442c752998bSGaetan Rivet DIR *dir;
443c752998bSGaetan Rivet char dirname[PATH_MAX];
444c752998bSGaetan Rivet struct rte_pci_addr addr;
445c752998bSGaetan Rivet
446c752998bSGaetan Rivet /* for debug purposes, PCI can be disabled */
447c752998bSGaetan Rivet if (!rte_eal_has_pci())
448c752998bSGaetan Rivet return 0;
449c752998bSGaetan Rivet
450c52dd394SThomas Monjalon dir = opendir(rte_pci_get_sysfs_path());
451c752998bSGaetan Rivet if (dir == NULL) {
452*849f773bSDavid Marchand PCI_LOG(ERR, "%s(): opendir failed: %s", __func__, strerror(errno));
453c752998bSGaetan Rivet return -1;
454c752998bSGaetan Rivet }
455c752998bSGaetan Rivet
456c752998bSGaetan Rivet while ((e = readdir(dir)) != NULL) {
457c752998bSGaetan Rivet if (e->d_name[0] == '.')
458c752998bSGaetan Rivet continue;
459c752998bSGaetan Rivet
460c752998bSGaetan Rivet if (parse_pci_addr_format(e->d_name, sizeof(e->d_name), &addr) != 0)
461c752998bSGaetan Rivet continue;
462c752998bSGaetan Rivet
463463a5245SSunil Kumar Kori if (rte_pci_ignore_device(&addr))
464463a5245SSunil Kumar Kori continue;
465463a5245SSunil Kumar Kori
466c752998bSGaetan Rivet snprintf(dirname, sizeof(dirname), "%s/%s",
467c52dd394SThomas Monjalon rte_pci_get_sysfs_path(), e->d_name);
468c752998bSGaetan Rivet
469c752998bSGaetan Rivet if (pci_scan_one(dirname, &addr) < 0)
470c752998bSGaetan Rivet goto error;
471c752998bSGaetan Rivet }
472c752998bSGaetan Rivet closedir(dir);
473c752998bSGaetan Rivet return 0;
474c752998bSGaetan Rivet
475c752998bSGaetan Rivet error:
476c752998bSGaetan Rivet closedir(dir);
477c752998bSGaetan Rivet return -1;
478c752998bSGaetan Rivet }
479c752998bSGaetan Rivet
48054a328f5SMaxime Coquelin #if defined(RTE_ARCH_X86)
48166d3724bSDavid Marchand bool
pci_device_iommu_support_va(const struct rte_pci_device * dev)48266d3724bSDavid Marchand pci_device_iommu_support_va(const struct rte_pci_device *dev)
48354a328f5SMaxime Coquelin {
48454a328f5SMaxime Coquelin #define VTD_CAP_MGAW_SHIFT 16
48554a328f5SMaxime Coquelin #define VTD_CAP_MGAW_MASK (0x3fULL << VTD_CAP_MGAW_SHIFT)
486703458e1SBen Walker const struct rte_pci_addr *addr = &dev->addr;
48754a328f5SMaxime Coquelin char filename[PATH_MAX];
48854a328f5SMaxime Coquelin FILE *fp;
48954a328f5SMaxime Coquelin uint64_t mgaw, vtd_cap_reg = 0;
49054a328f5SMaxime Coquelin
49154a328f5SMaxime Coquelin snprintf(filename, sizeof(filename),
49254a328f5SMaxime Coquelin "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap",
49354a328f5SMaxime Coquelin rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid,
49454a328f5SMaxime Coquelin addr->function);
49554a328f5SMaxime Coquelin
49654a328f5SMaxime Coquelin fp = fopen(filename, "r");
49754a328f5SMaxime Coquelin if (fp == NULL) {
4982e8d5cf7SStephen Hemminger /* We don't have an Intel IOMMU, assume VA supported */
4992e8d5cf7SStephen Hemminger if (errno == ENOENT)
5002e8d5cf7SStephen Hemminger return true;
5012e8d5cf7SStephen Hemminger
502*849f773bSDavid Marchand PCI_LOG(ERR, "%s(): can't open %s: %s",
5032e8d5cf7SStephen Hemminger __func__, filename, strerror(errno));
50454a328f5SMaxime Coquelin return false;
50554a328f5SMaxime Coquelin }
50654a328f5SMaxime Coquelin
5072e8d5cf7SStephen Hemminger /* We have an Intel IOMMU */
50854a328f5SMaxime Coquelin if (fscanf(fp, "%" PRIx64, &vtd_cap_reg) != 1) {
509*849f773bSDavid Marchand PCI_LOG(ERR, "%s(): can't read %s", __func__, filename);
51054a328f5SMaxime Coquelin fclose(fp);
51154a328f5SMaxime Coquelin return false;
51254a328f5SMaxime Coquelin }
51354a328f5SMaxime Coquelin
51454a328f5SMaxime Coquelin fclose(fp);
51554a328f5SMaxime Coquelin
51654a328f5SMaxime Coquelin mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1;
51754a328f5SMaxime Coquelin
518ec200687SAlejandro Lucero /*
519ec200687SAlejandro Lucero * Assuming there is no limitation by now. We can not know at this point
520ec200687SAlejandro Lucero * because the memory has not been initialized yet. Setting the dma mask
521ec200687SAlejandro Lucero * will force a check once memory initialization is done. We can not do
522ec200687SAlejandro Lucero * a fallback to IOVA PA now, but if the dma check fails, the error
523ec200687SAlejandro Lucero * message should advice for using '--iova-mode pa' if IOVA VA is the
524ec200687SAlejandro Lucero * current mode.
525ec200687SAlejandro Lucero */
526ec200687SAlejandro Lucero rte_mem_set_dma_mask(mgaw);
527ec200687SAlejandro Lucero return true;
52854a328f5SMaxime Coquelin }
52954a328f5SMaxime Coquelin #elif defined(RTE_ARCH_PPC_64)
53066d3724bSDavid Marchand bool
pci_device_iommu_support_va(__rte_unused const struct rte_pci_device * dev)53166d3724bSDavid Marchand pci_device_iommu_support_va(__rte_unused const struct rte_pci_device *dev)
53254a328f5SMaxime Coquelin {
53390521573SDavid Christensen /*
534fc5bffb8SDavid Christensen * All POWER systems support an IOMMU, but only IOMMUv2 supports
535fc5bffb8SDavid Christensen * IOVA = VA in DPDK. Check contents of /proc/cpuinfo to find the
536fc5bffb8SDavid Christensen * system.
537fc5bffb8SDavid Christensen *
538fc5bffb8SDavid Christensen * Platform | Model | IOMMU | VA? | Comment
539fc5bffb8SDavid Christensen * ---------+-------+---------+-----+---------------------------------
540fc5bffb8SDavid Christensen * PowerNV | N/A | IOMMUv2 | Yes | OpenPOWER (Bare Metal)
541fc5bffb8SDavid Christensen * pSeries | ~qemu | IOMMUv2 | Yes | PowerVM Logical Partition (LPAR)
542fc5bffb8SDavid Christensen * pSeries | qemu | IOMMUv1 | No | QEMU Virtual Machine
54390521573SDavid Christensen */
54490521573SDavid Christensen
54590521573SDavid Christensen char *line = NULL;
54690521573SDavid Christensen size_t len = 0;
54790521573SDavid Christensen char filename[PATH_MAX] = "/proc/cpuinfo";
54890521573SDavid Christensen FILE *fp = fopen(filename, "r");
549fc5bffb8SDavid Christensen bool pseries = false, powernv = false, qemu = false;
55090521573SDavid Christensen bool ret = false;
55190521573SDavid Christensen
55290521573SDavid Christensen if (fp == NULL) {
553*849f773bSDavid Marchand PCI_LOG(ERR, "%s(): can't open %s: %s",
55490521573SDavid Christensen __func__, filename, strerror(errno));
55590521573SDavid Christensen return ret;
55690521573SDavid Christensen }
55790521573SDavid Christensen
558fc5bffb8SDavid Christensen /* Check the "platform" and "model" fields */
55990521573SDavid Christensen while (getline(&line, &len, fp) != -1) {
560fc5bffb8SDavid Christensen if (strstr(line, "platform") != NULL) {
56190521573SDavid Christensen if (strstr(line, "PowerNV") != NULL) {
562*849f773bSDavid Marchand PCI_LOG(DEBUG, "Running on a PowerNV platform");
563fc5bffb8SDavid Christensen powernv = true;
564fc5bffb8SDavid Christensen } else if (strstr(line, "pSeries") != NULL) {
565*849f773bSDavid Marchand PCI_LOG(DEBUG, "Running on a pSeries platform");
566fc5bffb8SDavid Christensen pseries = true;
567fc5bffb8SDavid Christensen }
568fc5bffb8SDavid Christensen } else if (strstr(line, "model") != NULL) {
569fc5bffb8SDavid Christensen if (strstr(line, "qemu") != NULL) {
570*849f773bSDavid Marchand PCI_LOG(DEBUG, "Found qemu emulation");
571fc5bffb8SDavid Christensen qemu = true;
572fc5bffb8SDavid Christensen }
57390521573SDavid Christensen }
57490521573SDavid Christensen }
57590521573SDavid Christensen
57690521573SDavid Christensen free(line);
57790521573SDavid Christensen fclose(fp);
578fc5bffb8SDavid Christensen
579fc5bffb8SDavid Christensen if (powernv || (pseries && !qemu))
580fc5bffb8SDavid Christensen ret = true;
58190521573SDavid Christensen return ret;
58254a328f5SMaxime Coquelin }
58354a328f5SMaxime Coquelin #else
58466d3724bSDavid Marchand bool
pci_device_iommu_support_va(__rte_unused const struct rte_pci_device * dev)58566d3724bSDavid Marchand pci_device_iommu_support_va(__rte_unused const struct rte_pci_device *dev)
58654a328f5SMaxime Coquelin {
58754a328f5SMaxime Coquelin return true;
58854a328f5SMaxime Coquelin }
58954a328f5SMaxime Coquelin #endif
59054a328f5SMaxime Coquelin
591c752998bSGaetan Rivet enum rte_iova_mode
pci_device_iova_mode(const struct rte_pci_driver * pdrv,const struct rte_pci_device * pdev)592703458e1SBen Walker pci_device_iova_mode(const struct rte_pci_driver *pdrv,
593703458e1SBen Walker const struct rte_pci_device *pdev)
594c752998bSGaetan Rivet {
595703458e1SBen Walker enum rte_iova_mode iova_mode = RTE_IOVA_DC;
596c752998bSGaetan Rivet
597703458e1SBen Walker switch (pdev->kdrv) {
5987c0d798aSDavid Marchand case RTE_PCI_KDRV_VFIO: {
599c752998bSGaetan Rivet #ifdef VFIO_PRESENT
600703458e1SBen Walker static int is_vfio_noiommu_enabled = -1;
601703458e1SBen Walker
602703458e1SBen Walker if (is_vfio_noiommu_enabled == -1) {
603703458e1SBen Walker if (rte_vfio_noiommu_is_enabled() == 1)
604703458e1SBen Walker is_vfio_noiommu_enabled = 1;
605703458e1SBen Walker else
606703458e1SBen Walker is_vfio_noiommu_enabled = 0;
607703458e1SBen Walker }
608b76fafb1SDavid Marchand if (is_vfio_noiommu_enabled != 0)
609703458e1SBen Walker iova_mode = RTE_IOVA_PA;
610d622cad8SJerin Jacob else if ((pdrv->drv_flags & RTE_PCI_DRV_NEED_IOVA_AS_VA) != 0)
611b76fafb1SDavid Marchand iova_mode = RTE_IOVA_VA;
612c752998bSGaetan Rivet #endif
613703458e1SBen Walker break;
614c752998bSGaetan Rivet }
615c752998bSGaetan Rivet
6167c0d798aSDavid Marchand case RTE_PCI_KDRV_IGB_UIO:
6177c0d798aSDavid Marchand case RTE_PCI_KDRV_UIO_GENERIC:
618703458e1SBen Walker iova_mode = RTE_IOVA_PA;
619703458e1SBen Walker break;
620703458e1SBen Walker
621703458e1SBen Walker default:
622d622cad8SJerin Jacob if ((pdrv->drv_flags & RTE_PCI_DRV_NEED_IOVA_AS_VA) != 0)
623b76fafb1SDavid Marchand iova_mode = RTE_IOVA_VA;
624703458e1SBen Walker break;
625703458e1SBen Walker }
626703458e1SBen Walker return iova_mode;
627c752998bSGaetan Rivet }
628c752998bSGaetan Rivet
629c752998bSGaetan Rivet /* Read PCI config space. */
rte_pci_read_config(const struct rte_pci_device * device,void * buf,size_t len,off_t offset)630c752998bSGaetan Rivet int rte_pci_read_config(const struct rte_pci_device *device,
631c752998bSGaetan Rivet void *buf, size_t len, off_t offset)
632c752998bSGaetan Rivet {
633630deed6SAlejandro Lucero char devname[RTE_DEV_NAME_MAX_LEN] = "";
634d61138d4SHarman Kalra const struct rte_intr_handle *intr_handle = device->intr_handle;
635c752998bSGaetan Rivet
636630deed6SAlejandro Lucero switch (device->kdrv) {
6377c0d798aSDavid Marchand case RTE_PCI_KDRV_IGB_UIO:
6387c0d798aSDavid Marchand case RTE_PCI_KDRV_UIO_GENERIC:
639c752998bSGaetan Rivet return pci_uio_read_config(intr_handle, buf, len, offset);
640c752998bSGaetan Rivet #ifdef VFIO_PRESENT
6417c0d798aSDavid Marchand case RTE_PCI_KDRV_VFIO:
6424b741542SChenbo Xia return pci_vfio_read_config(device, buf, len, offset);
643c752998bSGaetan Rivet #endif
644c752998bSGaetan Rivet default:
645630deed6SAlejandro Lucero rte_pci_device_name(&device->addr, devname,
646630deed6SAlejandro Lucero RTE_DEV_NAME_MAX_LEN);
647*849f773bSDavid Marchand PCI_LOG(ERR, "Unknown driver type for %s", devname);
648c752998bSGaetan Rivet return -1;
649c752998bSGaetan Rivet }
650c752998bSGaetan Rivet }
651c752998bSGaetan Rivet
652c752998bSGaetan Rivet /* Write PCI config space. */
rte_pci_write_config(const struct rte_pci_device * device,const void * buf,size_t len,off_t offset)653c752998bSGaetan Rivet int rte_pci_write_config(const struct rte_pci_device *device,
654c752998bSGaetan Rivet const void *buf, size_t len, off_t offset)
655c752998bSGaetan Rivet {
656630deed6SAlejandro Lucero char devname[RTE_DEV_NAME_MAX_LEN] = "";
657d61138d4SHarman Kalra const struct rte_intr_handle *intr_handle = device->intr_handle;
658c752998bSGaetan Rivet
659630deed6SAlejandro Lucero switch (device->kdrv) {
6607c0d798aSDavid Marchand case RTE_PCI_KDRV_IGB_UIO:
6617c0d798aSDavid Marchand case RTE_PCI_KDRV_UIO_GENERIC:
662c752998bSGaetan Rivet return pci_uio_write_config(intr_handle, buf, len, offset);
663c752998bSGaetan Rivet #ifdef VFIO_PRESENT
6647c0d798aSDavid Marchand case RTE_PCI_KDRV_VFIO:
6654b741542SChenbo Xia return pci_vfio_write_config(device, buf, len, offset);
666c752998bSGaetan Rivet #endif
667c752998bSGaetan Rivet default:
668630deed6SAlejandro Lucero rte_pci_device_name(&device->addr, devname,
669630deed6SAlejandro Lucero RTE_DEV_NAME_MAX_LEN);
670*849f773bSDavid Marchand PCI_LOG(ERR, "Unknown driver type for %s", devname);
671c752998bSGaetan Rivet return -1;
672c752998bSGaetan Rivet }
673c752998bSGaetan Rivet }
674c752998bSGaetan Rivet
675095cf6e6SChenbo Xia /* Read PCI MMIO space. */
rte_pci_mmio_read(const struct rte_pci_device * device,int bar,void * buf,size_t len,off_t offset)676095cf6e6SChenbo Xia int rte_pci_mmio_read(const struct rte_pci_device *device, int bar,
677095cf6e6SChenbo Xia void *buf, size_t len, off_t offset)
678095cf6e6SChenbo Xia {
679095cf6e6SChenbo Xia char devname[RTE_DEV_NAME_MAX_LEN] = "";
680095cf6e6SChenbo Xia
681095cf6e6SChenbo Xia switch (device->kdrv) {
682095cf6e6SChenbo Xia case RTE_PCI_KDRV_IGB_UIO:
683095cf6e6SChenbo Xia case RTE_PCI_KDRV_UIO_GENERIC:
684095cf6e6SChenbo Xia return pci_uio_mmio_read(device, bar, buf, len, offset);
685095cf6e6SChenbo Xia #ifdef VFIO_PRESENT
686095cf6e6SChenbo Xia case RTE_PCI_KDRV_VFIO:
687095cf6e6SChenbo Xia return pci_vfio_mmio_read(device, bar, buf, len, offset);
688095cf6e6SChenbo Xia #endif
689095cf6e6SChenbo Xia default:
690095cf6e6SChenbo Xia rte_pci_device_name(&device->addr, devname,
691095cf6e6SChenbo Xia RTE_DEV_NAME_MAX_LEN);
692*849f773bSDavid Marchand PCI_LOG(ERR, "Unknown driver type for %s", devname);
693095cf6e6SChenbo Xia return -1;
694095cf6e6SChenbo Xia }
695095cf6e6SChenbo Xia }
696095cf6e6SChenbo Xia
697095cf6e6SChenbo Xia /* Write PCI MMIO space. */
rte_pci_mmio_write(const struct rte_pci_device * device,int bar,const void * buf,size_t len,off_t offset)698095cf6e6SChenbo Xia int rte_pci_mmio_write(const struct rte_pci_device *device, int bar,
699095cf6e6SChenbo Xia const void *buf, size_t len, off_t offset)
700095cf6e6SChenbo Xia {
701095cf6e6SChenbo Xia char devname[RTE_DEV_NAME_MAX_LEN] = "";
702095cf6e6SChenbo Xia
703095cf6e6SChenbo Xia switch (device->kdrv) {
704095cf6e6SChenbo Xia case RTE_PCI_KDRV_IGB_UIO:
705095cf6e6SChenbo Xia case RTE_PCI_KDRV_UIO_GENERIC:
706095cf6e6SChenbo Xia return pci_uio_mmio_write(device, bar, buf, len, offset);
707095cf6e6SChenbo Xia #ifdef VFIO_PRESENT
708095cf6e6SChenbo Xia case RTE_PCI_KDRV_VFIO:
709095cf6e6SChenbo Xia return pci_vfio_mmio_write(device, bar, buf, len, offset);
710095cf6e6SChenbo Xia #endif
711095cf6e6SChenbo Xia default:
712095cf6e6SChenbo Xia rte_pci_device_name(&device->addr, devname,
713095cf6e6SChenbo Xia RTE_DEV_NAME_MAX_LEN);
714*849f773bSDavid Marchand PCI_LOG(ERR, "Unknown driver type for %s", devname);
715095cf6e6SChenbo Xia return -1;
716095cf6e6SChenbo Xia }
717095cf6e6SChenbo Xia }
718095cf6e6SChenbo Xia
719c752998bSGaetan Rivet int
rte_pci_ioport_map(struct rte_pci_device * dev,int bar,struct rte_pci_ioport * p)720c752998bSGaetan Rivet rte_pci_ioport_map(struct rte_pci_device *dev, int bar,
721c752998bSGaetan Rivet struct rte_pci_ioport *p)
722c752998bSGaetan Rivet {
723c752998bSGaetan Rivet int ret = -1;
724c752998bSGaetan Rivet
725c752998bSGaetan Rivet switch (dev->kdrv) {
726c752998bSGaetan Rivet #ifdef VFIO_PRESENT
7277c0d798aSDavid Marchand case RTE_PCI_KDRV_VFIO:
728c752998bSGaetan Rivet if (pci_vfio_is_enabled())
729c752998bSGaetan Rivet ret = pci_vfio_ioport_map(dev, bar, p);
730c752998bSGaetan Rivet break;
731c752998bSGaetan Rivet #endif
7327c0d798aSDavid Marchand case RTE_PCI_KDRV_IGB_UIO:
7337c0d798aSDavid Marchand case RTE_PCI_KDRV_UIO_GENERIC:
734c752998bSGaetan Rivet ret = pci_uio_ioport_map(dev, bar, p);
735c752998bSGaetan Rivet break;
736c752998bSGaetan Rivet default:
737c752998bSGaetan Rivet break;
738c752998bSGaetan Rivet }
739c752998bSGaetan Rivet
740c752998bSGaetan Rivet if (!ret)
741c752998bSGaetan Rivet p->dev = dev;
742c752998bSGaetan Rivet
743c752998bSGaetan Rivet return ret;
744c752998bSGaetan Rivet }
745c752998bSGaetan Rivet
746c752998bSGaetan Rivet void
rte_pci_ioport_read(struct rte_pci_ioport * p,void * data,size_t len,off_t offset)747c752998bSGaetan Rivet rte_pci_ioport_read(struct rte_pci_ioport *p,
748c752998bSGaetan Rivet void *data, size_t len, off_t offset)
749c752998bSGaetan Rivet {
750c752998bSGaetan Rivet switch (p->dev->kdrv) {
751c752998bSGaetan Rivet #ifdef VFIO_PRESENT
7527c0d798aSDavid Marchand case RTE_PCI_KDRV_VFIO:
753c752998bSGaetan Rivet pci_vfio_ioport_read(p, data, len, offset);
754c752998bSGaetan Rivet break;
755c752998bSGaetan Rivet #endif
7567c0d798aSDavid Marchand case RTE_PCI_KDRV_IGB_UIO:
7577c0d798aSDavid Marchand case RTE_PCI_KDRV_UIO_GENERIC:
758c752998bSGaetan Rivet pci_uio_ioport_read(p, data, len, offset);
759c752998bSGaetan Rivet break;
760c752998bSGaetan Rivet default:
761c752998bSGaetan Rivet break;
762c752998bSGaetan Rivet }
763c752998bSGaetan Rivet }
764c752998bSGaetan Rivet
765c752998bSGaetan Rivet void
rte_pci_ioport_write(struct rte_pci_ioport * p,const void * data,size_t len,off_t offset)766c752998bSGaetan Rivet rte_pci_ioport_write(struct rte_pci_ioport *p,
767c752998bSGaetan Rivet const void *data, size_t len, off_t offset)
768c752998bSGaetan Rivet {
769c752998bSGaetan Rivet switch (p->dev->kdrv) {
770c752998bSGaetan Rivet #ifdef VFIO_PRESENT
7717c0d798aSDavid Marchand case RTE_PCI_KDRV_VFIO:
772c752998bSGaetan Rivet pci_vfio_ioport_write(p, data, len, offset);
773c752998bSGaetan Rivet break;
774c752998bSGaetan Rivet #endif
7757c0d798aSDavid Marchand case RTE_PCI_KDRV_IGB_UIO:
7767c0d798aSDavid Marchand case RTE_PCI_KDRV_UIO_GENERIC:
777c752998bSGaetan Rivet pci_uio_ioport_write(p, data, len, offset);
778c752998bSGaetan Rivet break;
779c752998bSGaetan Rivet default:
780c752998bSGaetan Rivet break;
781c752998bSGaetan Rivet }
782c752998bSGaetan Rivet }
783c752998bSGaetan Rivet
784c752998bSGaetan Rivet int
rte_pci_ioport_unmap(struct rte_pci_ioport * p)785c752998bSGaetan Rivet rte_pci_ioport_unmap(struct rte_pci_ioport *p)
786c752998bSGaetan Rivet {
787c752998bSGaetan Rivet int ret = -1;
788c752998bSGaetan Rivet
789c752998bSGaetan Rivet switch (p->dev->kdrv) {
790c752998bSGaetan Rivet #ifdef VFIO_PRESENT
7917c0d798aSDavid Marchand case RTE_PCI_KDRV_VFIO:
792c752998bSGaetan Rivet if (pci_vfio_is_enabled())
793c752998bSGaetan Rivet ret = pci_vfio_ioport_unmap(p);
794c752998bSGaetan Rivet break;
795c752998bSGaetan Rivet #endif
7967c0d798aSDavid Marchand case RTE_PCI_KDRV_IGB_UIO:
7977c0d798aSDavid Marchand case RTE_PCI_KDRV_UIO_GENERIC:
798c752998bSGaetan Rivet ret = pci_uio_ioport_unmap(p);
799c752998bSGaetan Rivet break;
800c752998bSGaetan Rivet default:
801c752998bSGaetan Rivet break;
802c752998bSGaetan Rivet }
803c752998bSGaetan Rivet
804c752998bSGaetan Rivet return ret;
805c752998bSGaetan Rivet }
806