xref: /dpdk/drivers/bus/fslmc/qbman/qbman_portal.h (revision b3bd7a50d100f2328d349277745d012563f0ac93)
1131a75b6SHemant Agrawal /* SPDX-License-Identifier: BSD-3-Clause
2531b17a7SHemant Agrawal  *
3531b17a7SHemant Agrawal  * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
4*b3bd7a50SNipun Gupta  * Copyright 2018-2020 NXP
5531b17a7SHemant Agrawal  *
6531b17a7SHemant Agrawal  */
7531b17a7SHemant Agrawal 
8293c0ca9SNipun Gupta #ifndef _QBMAN_PORTAL_H_
9293c0ca9SNipun Gupta #define _QBMAN_PORTAL_H_
10293c0ca9SNipun Gupta 
11d95bdc09SHemant Agrawal #include "qbman_sys.h"
12531b17a7SHemant Agrawal #include <fsl_qbman_portal.h>
13531b17a7SHemant Agrawal 
14dc111b5eSFerruh Yigit extern uint32_t qman_version;
15d95bdc09SHemant Agrawal #define QMAN_REV_4000   0x04000000
16d95bdc09SHemant Agrawal #define QMAN_REV_4100   0x04010000
17d95bdc09SHemant Agrawal #define QMAN_REV_4101   0x04010001
18d95bdc09SHemant Agrawal 
19531b17a7SHemant Agrawal /* All QBMan command and result structures use this "valid bit" encoding */
20531b17a7SHemant Agrawal #define QB_VALID_BIT ((uint32_t)0x80)
21531b17a7SHemant Agrawal 
22293c0ca9SNipun Gupta /* All QBMan command use this "Read trigger bit" encoding */
23293c0ca9SNipun Gupta #define QB_RT_BIT ((uint32_t)0x100)
24293c0ca9SNipun Gupta 
25531b17a7SHemant Agrawal /* Management command result codes */
26531b17a7SHemant Agrawal #define QBMAN_MC_RSLT_OK      0xf0
27531b17a7SHemant Agrawal 
28531b17a7SHemant Agrawal /* QBMan DQRR size is set at runtime in qbman_portal.c */
29531b17a7SHemant Agrawal 
qm_cyc_diff(uint8_t ringsize,uint8_t first,uint8_t last)30d95bdc09SHemant Agrawal static inline uint8_t qm_cyc_diff(uint8_t ringsize, uint8_t first,
31d95bdc09SHemant Agrawal 				  uint8_t last)
32531b17a7SHemant Agrawal {
33531b17a7SHemant Agrawal 	/* 'first' is included, 'last' is excluded */
34531b17a7SHemant Agrawal 	if (first <= last)
35531b17a7SHemant Agrawal 		return last - first;
36531b17a7SHemant Agrawal 	return (2 * ringsize) + last - first;
37531b17a7SHemant Agrawal }
38531b17a7SHemant Agrawal 
39531b17a7SHemant Agrawal /* --------------------- */
40531b17a7SHemant Agrawal /* portal data structure */
41531b17a7SHemant Agrawal /* --------------------- */
42531b17a7SHemant Agrawal 
43531b17a7SHemant Agrawal struct qbman_swp {
44531b17a7SHemant Agrawal 	struct qbman_swp_desc desc;
45531b17a7SHemant Agrawal 	/* The qbman_sys (ie. arch/OS-specific) support code can put anything it
46531b17a7SHemant Agrawal 	 * needs in here.
47531b17a7SHemant Agrawal 	 */
48531b17a7SHemant Agrawal 	struct qbman_swp_sys sys;
49531b17a7SHemant Agrawal 	/* Management commands */
50531b17a7SHemant Agrawal 	struct {
51531b17a7SHemant Agrawal #ifdef QBMAN_CHECKING
52531b17a7SHemant Agrawal 		enum swp_mc_check {
53531b17a7SHemant Agrawal 			swp_mc_can_start, /* call __qbman_swp_mc_start() */
54531b17a7SHemant Agrawal 			swp_mc_can_submit, /* call __qbman_swp_mc_submit() */
55531b17a7SHemant Agrawal 			swp_mc_can_poll, /* call __qbman_swp_mc_result() */
56531b17a7SHemant Agrawal 		} check;
57531b17a7SHemant Agrawal #endif
58531b17a7SHemant Agrawal 		uint32_t valid_bit; /* 0x00 or 0x80 */
59531b17a7SHemant Agrawal 	} mc;
60293c0ca9SNipun Gupta 	/* Management response */
61293c0ca9SNipun Gupta 	struct {
62293c0ca9SNipun Gupta 		uint32_t valid_bit; /* 0x00 or 0x80 */
63293c0ca9SNipun Gupta 	} mr;
64531b17a7SHemant Agrawal 	/* Push dequeues */
65531b17a7SHemant Agrawal 	uint32_t sdq;
66531b17a7SHemant Agrawal 	/* Volatile dequeues */
67531b17a7SHemant Agrawal 	struct {
68531b17a7SHemant Agrawal 		/* VDQCR supports a "1 deep pipeline", meaning that if you know
69531b17a7SHemant Agrawal 		 * the last-submitted command is already executing in the
70531b17a7SHemant Agrawal 		 * hardware (as evidenced by at least 1 valid dequeue result),
71531b17a7SHemant Agrawal 		 * you can write another dequeue command to the register, the
72531b17a7SHemant Agrawal 		 * hardware will start executing it as soon as the
73531b17a7SHemant Agrawal 		 * already-executing command terminates. (This minimises latency
74531b17a7SHemant Agrawal 		 * and stalls.) With that in mind, this "busy" variable refers
75531b17a7SHemant Agrawal 		 * to whether or not a command can be submitted, not whether or
76531b17a7SHemant Agrawal 		 * not a previously-submitted command is still executing. In
77531b17a7SHemant Agrawal 		 * other words, once proof is seen that the previously-submitted
78531b17a7SHemant Agrawal 		 * command is executing, "vdq" is no longer "busy".
79531b17a7SHemant Agrawal 		 */
80531b17a7SHemant Agrawal 		atomic_t busy;
81531b17a7SHemant Agrawal 		uint32_t valid_bit; /* 0x00 or 0x80 */
82531b17a7SHemant Agrawal 		/* We need to determine when vdq is no longer busy. This depends
83531b17a7SHemant Agrawal 		 * on whether the "busy" (last-submitted) dequeue command is
84531b17a7SHemant Agrawal 		 * targeting DQRR or main-memory, and detected is based on the
85531b17a7SHemant Agrawal 		 * presence of the dequeue command's "token" showing up in
86531b17a7SHemant Agrawal 		 * dequeue entries in DQRR or main-memory (respectively).
87531b17a7SHemant Agrawal 		 */
88531b17a7SHemant Agrawal 		struct qbman_result *storage; /* NULL if DQRR */
89531b17a7SHemant Agrawal 	} vdq;
90531b17a7SHemant Agrawal 	/* DQRR */
91531b17a7SHemant Agrawal 	struct {
92531b17a7SHemant Agrawal 		uint32_t next_idx;
93531b17a7SHemant Agrawal 		uint32_t valid_bit;
94531b17a7SHemant Agrawal 		uint8_t dqrr_size;
95531b17a7SHemant Agrawal 		int reset_bug;
96531b17a7SHemant Agrawal 	} dqrr;
97531b17a7SHemant Agrawal 	struct {
98531b17a7SHemant Agrawal 		uint32_t pi;
99531b17a7SHemant Agrawal 		uint32_t pi_vb;
100293c0ca9SNipun Gupta 		uint32_t pi_ring_size;
1011b49352fSHemant Agrawal 		uint32_t pi_ci_mask;
102531b17a7SHemant Agrawal 		uint32_t ci;
103531b17a7SHemant Agrawal 		int available;
104531b17a7SHemant Agrawal 	} eqcr;
105*b3bd7a50SNipun Gupta 	uint8_t stash_off;
106531b17a7SHemant Agrawal };
107531b17a7SHemant Agrawal 
108531b17a7SHemant Agrawal /* -------------------------- */
109531b17a7SHemant Agrawal /* portal management commands */
110531b17a7SHemant Agrawal /* -------------------------- */
111531b17a7SHemant Agrawal 
112531b17a7SHemant Agrawal /* Different management commands all use this common base layer of code to issue
113531b17a7SHemant Agrawal  * commands and poll for results. The first function returns a pointer to where
114531b17a7SHemant Agrawal  * the caller should fill in their MC command (though they should ignore the
115531b17a7SHemant Agrawal  * verb byte), the second function commits merges in the caller-supplied command
116531b17a7SHemant Agrawal  * verb (which should not include the valid-bit) and submits the command to
117531b17a7SHemant Agrawal  * hardware, and the third function checks for a completed response (returns
118531b17a7SHemant Agrawal  * non-NULL if only if the response is complete).
119531b17a7SHemant Agrawal  */
120531b17a7SHemant Agrawal void *qbman_swp_mc_start(struct qbman_swp *p);
12169293c77SHemant Agrawal void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint8_t cmd_verb);
122*b3bd7a50SNipun Gupta void qbman_swp_mc_submit_cinh(struct qbman_swp *p, void *cmd, uint8_t cmd_verb);
123531b17a7SHemant Agrawal void *qbman_swp_mc_result(struct qbman_swp *p);
124*b3bd7a50SNipun Gupta void *qbman_swp_mc_result_cinh(struct qbman_swp *p);
125531b17a7SHemant Agrawal 
126531b17a7SHemant Agrawal /* Wraps up submit + poll-for-result */
qbman_swp_mc_complete(struct qbman_swp * swp,void * cmd,uint8_t cmd_verb)127531b17a7SHemant Agrawal static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
12869293c77SHemant Agrawal 					  uint8_t cmd_verb)
129531b17a7SHemant Agrawal {
130d95bdc09SHemant Agrawal 	int loopvar = 1000;
131531b17a7SHemant Agrawal 
132531b17a7SHemant Agrawal 	qbman_swp_mc_submit(swp, cmd, cmd_verb);
133531b17a7SHemant Agrawal 	do {
134531b17a7SHemant Agrawal 		cmd = qbman_swp_mc_result(swp);
135d95bdc09SHemant Agrawal 	} while (!cmd && loopvar--);
136d95bdc09SHemant Agrawal 	QBMAN_BUG_ON(!loopvar);
137d95bdc09SHemant Agrawal 
138531b17a7SHemant Agrawal 	return cmd;
139531b17a7SHemant Agrawal }
140531b17a7SHemant Agrawal 
qbman_swp_mc_complete_cinh(struct qbman_swp * swp,void * cmd,uint8_t cmd_verb)141*b3bd7a50SNipun Gupta static inline void *qbman_swp_mc_complete_cinh(struct qbman_swp *swp, void *cmd,
142*b3bd7a50SNipun Gupta 					  uint8_t cmd_verb)
143*b3bd7a50SNipun Gupta {
144*b3bd7a50SNipun Gupta 	int loopvar = 1000;
145*b3bd7a50SNipun Gupta 
146*b3bd7a50SNipun Gupta 	qbman_swp_mc_submit_cinh(swp, cmd, cmd_verb);
147*b3bd7a50SNipun Gupta 	do {
148*b3bd7a50SNipun Gupta 		cmd = qbman_swp_mc_result_cinh(swp);
149*b3bd7a50SNipun Gupta 	} while (!cmd && loopvar--);
150*b3bd7a50SNipun Gupta 	QBMAN_BUG_ON(!loopvar);
151*b3bd7a50SNipun Gupta 
152*b3bd7a50SNipun Gupta 	return cmd;
153*b3bd7a50SNipun Gupta }
154*b3bd7a50SNipun Gupta 
155531b17a7SHemant Agrawal /* ---------------------- */
156531b17a7SHemant Agrawal /* Descriptors/cachelines */
157531b17a7SHemant Agrawal /* ---------------------- */
158531b17a7SHemant Agrawal 
159531b17a7SHemant Agrawal /* To avoid needless dynamic allocation, the driver API often gives the caller
160531b17a7SHemant Agrawal  * a "descriptor" type that the caller can instantiate however they like.
161531b17a7SHemant Agrawal  * Ultimately though, it is just a cacheline of binary storage (or something
162531b17a7SHemant Agrawal  * smaller when it is known that the descriptor doesn't need all 64 bytes) for
163531b17a7SHemant Agrawal  * holding pre-formatted pieces of hardware commands. The performance-critical
164531b17a7SHemant Agrawal  * code can then copy these descriptors directly into hardware command
165531b17a7SHemant Agrawal  * registers more efficiently than trying to construct/format commands
166531b17a7SHemant Agrawal  * on-the-fly. The API user sees the descriptor as an array of 32-bit words in
167531b17a7SHemant Agrawal  * order for the compiler to know its size, but the internal details are not
168531b17a7SHemant Agrawal  * exposed. The following macro is used within the driver for converting *any*
169531b17a7SHemant Agrawal  * descriptor pointer to a usable array pointer. The use of a macro (instead of
170531b17a7SHemant Agrawal  * an inline) is necessary to work with different descriptor types and to work
171531b17a7SHemant Agrawal  * correctly with const and non-const inputs (and similarly-qualified outputs).
172531b17a7SHemant Agrawal  */
173293c0ca9SNipun Gupta #define qb_cl(d) (&(d)->dont_manipulate_directly[0])
174293c0ca9SNipun Gupta 
175293c0ca9SNipun Gupta #ifdef RTE_ARCH_ARM64
176293c0ca9SNipun Gupta 	#define clean(p) \
177293c0ca9SNipun Gupta 			{ asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); }
178293c0ca9SNipun Gupta 	#define invalidate(p) \
179293c0ca9SNipun Gupta 			{ asm volatile("dc ivac, %0" : : "r"(p) : "memory"); }
180293c0ca9SNipun Gupta #else
181293c0ca9SNipun Gupta 	#define clean(p)
182293c0ca9SNipun Gupta 	#define invalidate(p)
183293c0ca9SNipun Gupta #endif
184293c0ca9SNipun Gupta 
185293c0ca9SNipun Gupta #endif
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