1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * 3 * Copyright 2008-2016 Freescale Semiconductor Inc. 4 * Copyright 2017,2019 NXP 5 * 6 */ 7 8 #ifndef __QMAN_PRIV_H 9 #define __QMAN_PRIV_H 10 11 #include "dpaa_sys.h" 12 #include <fsl_qman.h> 13 14 /* Congestion Groups */ 15 /* 16 * This wrapper represents a bit-array for the state of the 256 QMan congestion 17 * groups. Is also used as a *mask* for congestion groups, eg. so we ignore 18 * those that don't concern us. We harness the structure and accessor details 19 * already used in the management command to query congestion groups. 20 */ 21 struct qman_cgrs { 22 struct __qm_mcr_querycongestion q; 23 }; 24 25 static inline void qman_cgrs_init(struct qman_cgrs *c) 26 { 27 memset(c, 0, sizeof(*c)); 28 } 29 30 static inline void qman_cgrs_fill(struct qman_cgrs *c) 31 { 32 memset(c, 0xff, sizeof(*c)); 33 } 34 35 static inline int qman_cgrs_get(struct qman_cgrs *c, int num) 36 { 37 return QM_MCR_QUERYCONGESTION(&c->q, num); 38 } 39 40 static inline void qman_cgrs_set(struct qman_cgrs *c, int num) 41 { 42 c->q.state[__CGR_WORD(num)] |= (0x80000000 >> __CGR_SHIFT(num)); 43 } 44 45 static inline void qman_cgrs_unset(struct qman_cgrs *c, int num) 46 { 47 c->q.state[__CGR_WORD(num)] &= ~(0x80000000 >> __CGR_SHIFT(num)); 48 } 49 50 static inline int qman_cgrs_next(struct qman_cgrs *c, int num) 51 { 52 while ((++num < (int)__CGR_NUM) && !qman_cgrs_get(c, num)) 53 ; 54 return num; 55 } 56 57 static inline void qman_cgrs_cp(struct qman_cgrs *dest, 58 const struct qman_cgrs *src) 59 { 60 memcpy(dest, src, sizeof(*dest)); 61 } 62 63 static inline void qman_cgrs_and(struct qman_cgrs *dest, 64 const struct qman_cgrs *a, 65 const struct qman_cgrs *b) 66 { 67 int ret; 68 u32 *_d = dest->q.state; 69 const u32 *_a = a->q.state; 70 const u32 *_b = b->q.state; 71 72 for (ret = 0; ret < 8; ret++) 73 *(_d++) = *(_a++) & *(_b++); 74 } 75 76 static inline void qman_cgrs_xor(struct qman_cgrs *dest, 77 const struct qman_cgrs *a, 78 const struct qman_cgrs *b) 79 { 80 int ret; 81 u32 *_d = dest->q.state; 82 const u32 *_a = a->q.state; 83 const u32 *_b = b->q.state; 84 85 for (ret = 0; ret < 8; ret++) 86 *(_d++) = *(_a++) ^ *(_b++); 87 } 88 89 /* used by CCSR and portal interrupt code */ 90 enum qm_isr_reg { 91 qm_isr_status = 0, 92 qm_isr_enable = 1, 93 qm_isr_disable = 2, 94 qm_isr_inhibit = 3 95 }; 96 97 struct qm_portal_config { 98 /* 99 * Corenet portal addresses; 100 * [0]==cache-enabled, [1]==cache-inhibited. 101 */ 102 void __iomem *addr_virt[2]; 103 struct device_node *node; 104 /* Allow these to be joined in lists */ 105 struct list_head list; 106 /* User-visible portal configuration settings */ 107 /* If the caller enables DQRR stashing (and thus wishes to operate the 108 * portal from only one cpu), this is the logical CPU that the portal 109 * will stash to. Whether stashing is enabled or not, this setting is 110 * also used for any "core-affine" portals, ie. default portals 111 * associated to the corresponding cpu. -1 implies that there is no 112 * core affinity configured. 113 */ 114 int cpu; 115 /* portal interrupt line */ 116 int irq; 117 /* the unique index of this portal */ 118 u32 index; 119 /* Is this portal shared? (If so, it has coarser locking and demuxes 120 * processing on behalf of other CPUs.). 121 */ 122 int is_shared; 123 /* The portal's dedicated channel id, use this value for initialising 124 * frame queues to target this portal when scheduled. 125 */ 126 u16 channel; 127 /* A mask of which pool channels this portal has dequeue access to 128 * (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask). 129 */ 130 u32 pools; 131 132 }; 133 134 /* Revision info (for errata and feature handling) */ 135 #define QMAN_REV11 0x0101 136 #define QMAN_REV12 0x0102 137 #define QMAN_REV20 0x0200 138 #define QMAN_REV30 0x0300 139 #define QMAN_REV31 0x0301 140 #define QMAN_REV32 0x0302 141 extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */ 142 143 int qm_set_wpm(int wpm); 144 int qm_get_wpm(int *wpm); 145 146 struct qman_portal *qman_create_affine_portal( 147 const struct qm_portal_config *config, 148 const struct qman_cgrs *cgrs); 149 const struct qm_portal_config * 150 qman_destroy_affine_portal(struct qman_portal *q); 151 152 struct qman_portal * 153 qman_init_portal(struct qman_portal *portal, 154 const struct qm_portal_config *c, 155 const struct qman_cgrs *cgrs); 156 157 struct qman_portal *qman_alloc_global_portal(struct qm_portal_config *q_pcfg); 158 int qman_free_global_portal(struct qman_portal *portal); 159 160 void qman_portal_uninhibit_isr(struct qman_portal *portal); 161 162 struct qm_portal_config *qm_get_unused_portal(void); 163 struct qm_portal_config *qm_get_unused_portal_idx(uint32_t idx); 164 165 void qm_put_unused_portal(struct qm_portal_config *pcfg); 166 void qm_set_liodns(struct qm_portal_config *pcfg); 167 168 /* This CGR feature is supported by h/w and required by unit-tests and the 169 * debugfs hooks, so is implemented in the driver. However it allows an explicit 170 * corruption of h/w fields by s/w that are usually incorruptible (because the 171 * counters are usually maintained entirely within h/w). As such, we declare 172 * this API internally. 173 */ 174 int qman_testwrite_cgr(struct qman_cgr *cgr, u64 i_bcnt, 175 struct qm_mcr_cgrtestwrite *result); 176 177 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 178 /* If the fq object pointer is greater than the size of context_b field, 179 * than a lookup table is required. 180 */ 181 int qman_setup_fq_lookup_table(size_t num_entries); 182 #endif 183 184 /* QMan s/w corenet portal, low-level i/face */ 185 186 /* 187 * For Choose one SOURCE. Choose one COUNT. Choose one 188 * dequeue TYPE. Choose TOKEN (8-bit). 189 * If SOURCE == CHANNELS, 190 * Choose CHANNELS_DEDICATED and/or CHANNELS_POOL(n). 191 * You can choose DEDICATED_PRECEDENCE if the portal channel should have 192 * priority. 193 * If SOURCE == SPECIFICWQ, 194 * Either select the work-queue ID with SPECIFICWQ_WQ(), or select the 195 * channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the 196 * work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the 197 * same value. 198 */ 199 #define QM_SDQCR_SOURCE_CHANNELS 0x0 200 #define QM_SDQCR_SOURCE_SPECIFICWQ 0x40000000 201 #define QM_SDQCR_COUNT_EXACT1 0x0 202 #define QM_SDQCR_COUNT_UPTO3 0x20000000 203 #define QM_SDQCR_DEDICATED_PRECEDENCE 0x10000000 204 #define QM_SDQCR_TYPE_MASK 0x03000000 205 #define QM_SDQCR_TYPE_NULL 0x0 206 #define QM_SDQCR_TYPE_PRIO_QOS 0x01000000 207 #define QM_SDQCR_TYPE_ACTIVE_QOS 0x02000000 208 #define QM_SDQCR_TYPE_ACTIVE 0x03000000 209 #define QM_SDQCR_TOKEN_MASK 0x00ff0000 210 #define QM_SDQCR_TOKEN_SET(v) (((v) & 0xff) << 16) 211 #define QM_SDQCR_TOKEN_GET(v) (((v) >> 16) & 0xff) 212 #define QM_SDQCR_CHANNELS_DEDICATED 0x00008000 213 #define QM_SDQCR_SPECIFICWQ_MASK 0x000000f7 214 #define QM_SDQCR_SPECIFICWQ_DEDICATED 0x00000000 215 #define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4) 216 #define QM_SDQCR_SPECIFICWQ_WQ(n) (n) 217 218 #define QM_VDQCR_FQID_MASK 0x00ffffff 219 #define QM_VDQCR_FQID(n) ((n) & QM_VDQCR_FQID_MASK) 220 221 #define QM_EQCR_VERB_VBIT 0x80 222 #define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */ 223 #define QM_EQCR_VERB_CMD_ENQUEUE 0x01 224 #define QM_EQCR_VERB_COLOUR_MASK 0x18 /* 4 possible values; */ 225 #define QM_EQCR_VERB_COLOUR_GREEN 0x00 226 #define QM_EQCR_VERB_COLOUR_YELLOW 0x08 227 #define QM_EQCR_VERB_COLOUR_RED 0x10 228 #define QM_EQCR_VERB_COLOUR_OVERRIDE 0x18 229 #define QM_EQCR_VERB_INTERRUPT 0x04 /* on command consumption */ 230 #define QM_EQCR_VERB_ORP 0x02 /* enable order restoration */ 231 #define QM_EQCR_DCA_ENABLE 0x80 232 #define QM_EQCR_DCA_PARK 0x40 233 #define QM_EQCR_DCA_IDXMASK 0x0f /* "DQRR::idx" goes here */ 234 #define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */ 235 #define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */ 236 #define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */ 237 #define QM_EQCR_FQID_NULL 0 /* eg. for an ORP seqnum hole */ 238 239 #define QM_MCC_VERB_VBIT 0x80 240 #define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */ 241 #define QM_MCC_VERB_INITFQ_PARKED 0x40 242 #define QM_MCC_VERB_INITFQ_SCHED 0x41 243 #define QM_MCC_VERB_QUERYFQ 0x44 244 #define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */ 245 #define QM_MCC_VERB_QUERYWQ 0x46 246 #define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47 247 #define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */ 248 #define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */ 249 #define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */ 250 #define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */ 251 #define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */ 252 #define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */ 253 #define QM_MCC_VERB_INITCGR 0x50 254 #define QM_MCC_VERB_MODIFYCGR 0x51 255 #define QM_MCC_VERB_CGRTESTWRITE 0x52 256 #define QM_MCC_VERB_QUERYCGR 0x58 257 #define QM_MCC_VERB_QUERYCONGESTION 0x59 258 259 /* 260 * Used by all portal interrupt registers except 'inhibit' 261 * Channels with frame availability 262 */ 263 #define QM_PIRQ_DQAVAIL 0x0000ffff 264 265 /* The DQAVAIL interrupt fields break down into these bits; */ 266 #define QM_DQAVAIL_PORTAL 0x8000 /* Portal channel */ 267 #define QM_DQAVAIL_POOL(n) (0x8000 >> (n)) /* Pool channel, n==[1..15] */ 268 #define QM_DQAVAIL_MASK 0xffff 269 /* This mask contains all the "irqsource" bits visible to API users */ 270 #define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI) 271 272 /* These are qm_<reg>_<verb>(). So for example, qm_disable_write() means "write 273 * the disable register" rather than "disable the ability to write". 274 */ 275 #define qm_isr_status_read(qm) __qm_isr_read(qm, qm_isr_status) 276 #define qm_isr_status_clear(qm, m) __qm_isr_write(qm, qm_isr_status, m) 277 #define qm_isr_enable_read(qm) __qm_isr_read(qm, qm_isr_enable) 278 #define qm_isr_enable_write(qm, v) __qm_isr_write(qm, qm_isr_enable, v) 279 #define qm_isr_disable_read(qm) __qm_isr_read(qm, qm_isr_disable) 280 #define qm_isr_disable_write(qm, v) __qm_isr_write(qm, qm_isr_disable, v) 281 /* TODO: unfortunate name-clash here, reword? */ 282 #define qm_isr_inhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 1) 283 #define qm_isr_uninhibit(qm) __qm_isr_write(qm, qm_isr_inhibit, 0) 284 285 #define QMAN_PORTAL_IRQ_PATH "/dev/fsl-usdpaa-irq" 286 287 #endif /* _QMAN_PRIV_H */ 288