1*dcf43d24SNicolas Chautru /* SPDX-License-Identifier: BSD-3-Clause 2*dcf43d24SNicolas Chautru * Copyright(c) 2017 Intel Corporation 3*dcf43d24SNicolas Chautru */ 4*dcf43d24SNicolas Chautru 5*dcf43d24SNicolas Chautru #ifndef ACC100_VF_ENUM_H 6*dcf43d24SNicolas Chautru #define ACC100_VF_ENUM_H 7*dcf43d24SNicolas Chautru 8*dcf43d24SNicolas Chautru /* 9*dcf43d24SNicolas Chautru * ACC100 Register mapping on VF BAR0 10*dcf43d24SNicolas Chautru * This is automatically generated from RDL, format may change with new RDL 11*dcf43d24SNicolas Chautru */ 12*dcf43d24SNicolas Chautru enum { 13*dcf43d24SNicolas Chautru HWVfQmgrIngressAq = 0x00000000, 14*dcf43d24SNicolas Chautru HWVfHiVfToPfDbellVf = 0x00000800, 15*dcf43d24SNicolas Chautru HWVfHiPfToVfDbellVf = 0x00000808, 16*dcf43d24SNicolas Chautru HWVfHiInfoRingBaseLoVf = 0x00000810, 17*dcf43d24SNicolas Chautru HWVfHiInfoRingBaseHiVf = 0x00000814, 18*dcf43d24SNicolas Chautru HWVfHiInfoRingPointerVf = 0x00000818, 19*dcf43d24SNicolas Chautru HWVfHiInfoRingIntWrEnVf = 0x00000820, 20*dcf43d24SNicolas Chautru HWVfHiInfoRingPf2VfWrEnVf = 0x00000824, 21*dcf43d24SNicolas Chautru HWVfHiMsixVectorMapperVf = 0x00000860, 22*dcf43d24SNicolas Chautru HWVfDmaFec5GulDescBaseLoRegVf = 0x00000920, 23*dcf43d24SNicolas Chautru HWVfDmaFec5GulDescBaseHiRegVf = 0x00000924, 24*dcf43d24SNicolas Chautru HWVfDmaFec5GulRespPtrLoRegVf = 0x00000928, 25*dcf43d24SNicolas Chautru HWVfDmaFec5GulRespPtrHiRegVf = 0x0000092C, 26*dcf43d24SNicolas Chautru HWVfDmaFec5GdlDescBaseLoRegVf = 0x00000940, 27*dcf43d24SNicolas Chautru HWVfDmaFec5GdlDescBaseHiRegVf = 0x00000944, 28*dcf43d24SNicolas Chautru HWVfDmaFec5GdlRespPtrLoRegVf = 0x00000948, 29*dcf43d24SNicolas Chautru HWVfDmaFec5GdlRespPtrHiRegVf = 0x0000094C, 30*dcf43d24SNicolas Chautru HWVfDmaFec4GulDescBaseLoRegVf = 0x00000960, 31*dcf43d24SNicolas Chautru HWVfDmaFec4GulDescBaseHiRegVf = 0x00000964, 32*dcf43d24SNicolas Chautru HWVfDmaFec4GulRespPtrLoRegVf = 0x00000968, 33*dcf43d24SNicolas Chautru HWVfDmaFec4GulRespPtrHiRegVf = 0x0000096C, 34*dcf43d24SNicolas Chautru HWVfDmaFec4GdlDescBaseLoRegVf = 0x00000980, 35*dcf43d24SNicolas Chautru HWVfDmaFec4GdlDescBaseHiRegVf = 0x00000984, 36*dcf43d24SNicolas Chautru HWVfDmaFec4GdlRespPtrLoRegVf = 0x00000988, 37*dcf43d24SNicolas Chautru HWVfDmaFec4GdlRespPtrHiRegVf = 0x0000098C, 38*dcf43d24SNicolas Chautru HWVfDmaDdrBaseRangeRoVf = 0x000009A0, 39*dcf43d24SNicolas Chautru HWVfQmgrAqResetVf = 0x00000E00, 40*dcf43d24SNicolas Chautru HWVfQmgrRingSizeVf = 0x00000E04, 41*dcf43d24SNicolas Chautru HWVfQmgrGrpDepthLog20Vf = 0x00000E08, 42*dcf43d24SNicolas Chautru HWVfQmgrGrpDepthLog21Vf = 0x00000E0C, 43*dcf43d24SNicolas Chautru HWVfQmgrGrpFunction0Vf = 0x00000E10, 44*dcf43d24SNicolas Chautru HWVfQmgrGrpFunction1Vf = 0x00000E14, 45*dcf43d24SNicolas Chautru HWVfPmACntrlRegVf = 0x00000F40, 46*dcf43d24SNicolas Chautru HWVfPmACountVf = 0x00000F48, 47*dcf43d24SNicolas Chautru HWVfPmAKCntLoVf = 0x00000F50, 48*dcf43d24SNicolas Chautru HWVfPmAKCntHiVf = 0x00000F54, 49*dcf43d24SNicolas Chautru HWVfPmADeltaCntLoVf = 0x00000F60, 50*dcf43d24SNicolas Chautru HWVfPmADeltaCntHiVf = 0x00000F64, 51*dcf43d24SNicolas Chautru HWVfPmBCntrlRegVf = 0x00000F80, 52*dcf43d24SNicolas Chautru HWVfPmBCountVf = 0x00000F88, 53*dcf43d24SNicolas Chautru HWVfPmBKCntLoVf = 0x00000F90, 54*dcf43d24SNicolas Chautru HWVfPmBKCntHiVf = 0x00000F94, 55*dcf43d24SNicolas Chautru HWVfPmBDeltaCntLoVf = 0x00000FA0, 56*dcf43d24SNicolas Chautru HWVfPmBDeltaCntHiVf = 0x00000FA4 57*dcf43d24SNicolas Chautru }; 58*dcf43d24SNicolas Chautru 59*dcf43d24SNicolas Chautru /* TIP VF Interrupt numbers */ 60*dcf43d24SNicolas Chautru enum { 61*dcf43d24SNicolas Chautru ACC100_VF_INT_QMGR_AQ_OVERFLOW = 0, 62*dcf43d24SNicolas Chautru ACC100_VF_INT_DOORBELL_VF_2_PF = 1, 63*dcf43d24SNicolas Chautru ACC100_VF_INT_DMA_DL_DESC_IRQ = 2, 64*dcf43d24SNicolas Chautru ACC100_VF_INT_DMA_UL_DESC_IRQ = 3, 65*dcf43d24SNicolas Chautru ACC100_VF_INT_DMA_MLD_DESC_IRQ = 4, 66*dcf43d24SNicolas Chautru ACC100_VF_INT_DMA_UL5G_DESC_IRQ = 5, 67*dcf43d24SNicolas Chautru ACC100_VF_INT_DMA_DL5G_DESC_IRQ = 6, 68*dcf43d24SNicolas Chautru ACC100_VF_INT_ILLEGAL_FORMAT = 7, 69*dcf43d24SNicolas Chautru ACC100_VF_INT_QMGR_DISABLED_ACCESS = 8, 70*dcf43d24SNicolas Chautru ACC100_VF_INT_QMGR_AQ_OVERTHRESHOLD = 9, 71*dcf43d24SNicolas Chautru }; 72*dcf43d24SNicolas Chautru 73*dcf43d24SNicolas Chautru #endif /* ACC100_VF_ENUM_H */ 74