1.. SPDX-License-Identifier: BSD-3-Clause 2 Copyright(c) 2018 Intel Corporation. 3 4IFPGA Rawdev Driver 5====================== 6 7FPGA is used more and more widely in Cloud and NFV, one primary reason is 8that FPGA not only provides ASIC performance but also it's more flexible 9than ASIC. 10 11FPGA uses Partial Reconfigure (PR) Parts of Bit Stream to achieve its 12flexibility. That means one FPGA Device Bit Stream is divided into many Parts 13of Bit Stream(each Part of Bit Stream is defined as AFU-Accelerated Function 14Unit), and each AFU is a hardware acceleration unit which can be dynamically 15reloaded respectively. 16 17By PR (Partial Reconfiguration) AFUs, one FPGA resources can be time-shared by 18different users. FPGA hot upgrade and fault tolerance can be provided easily. 19 20The SW IFPGA Rawdev Driver (**ifpga_rawdev**) provides a Rawdev driver 21that utilizes Intel FPGA Software Stack OPAE(Open Programmable Acceleration 22Engine) for FPGA management. 23 24Implementation details 25---------------------- 26 27Each instance of IFPGA Rawdev Driver is probed by Intel FpgaDev. In coordination 28with OPAE share code IFPGA Rawdev Driver provides common FPGA management ops 29for FPGA operation, OPAE provides all following operations: 30- FPGA PR (Partial Reconfiguration) management 31- FPGA AFUs Identifying 32- FPGA Thermal Management 33- FPGA Power Management 34- FPGA Performance reporting 35- FPGA Remote Debug 36 37All configuration parameters are taken by vdev_ifpga_cfg driver. Besides 38configuration, vdev_ifpga_cfg driver also hot plugs in IFPGA Bus. 39 40All of the AFUs of one FPGA may share same PCI BDF and AFUs scan depend on 41IFPGA Rawdev Driver so IFPGA Bus takes AFU device scan and AFU drivers probe. 42All AFU device driver bind to AFU device by its UUID (Universally Unique 43Identifier). 44 45To avoid unnecessary code duplication and ensure maximum performance, 46handling of AFU devices is left to different PMDs; all the design as 47summarized by the following block diagram:: 48 49 +---------------------------------------------------------------+ 50 | Application(s) | 51 +----------------------------.----------------------------------+ 52 | 53 | 54 +----------------------------'----------------------------------+ 55 | DPDK Framework (APIs) | 56 +----------|------------|--------.---------------------|--------+ 57 / \ | 58 / \ | 59 +-------'-------+ +-------'-------+ +--------'--------+ 60 | Eth PMD | | Crypto PMD | | | 61 +-------.-------+ +-------.-------+ | | 62 | | | | 63 | | | | 64 +-------'-------+ +-------'-------+ | IFPGA | 65 | Eth AFU Dev | |Crypto AFU Dev | | Rawdev Driver | 66 +-------.-------+ +-------.-------+ |(OPAE Share Code)| 67 | | | | 68 | | Rawdev | | 69 +-------'------------------'-------+ Ops | | 70 | IFPGA Bus | -------->| | 71 +-----------------.----------------+ +--------.--------+ 72 | | 73 Hot-plugin -->| | 74 | | 75 +-----------------'------------------+ +--------'--------+ 76 | vdev_ifpga_cfg driver | | Intel FpgaDev | 77 +------------------------------------+ +-----------------+ 78 79 80Run-time parameters 81------------------- 82 83This driver is invoked automatically in systems added with Intel FPGA, 84but PR and IFPGA Bus scan is triggered by command line using 85``--vdev 'ifpga_rawdev_cfg`` EAL option. 86 87The following device parameters are supported: 88 89- ``ifpga`` [string] 90 91 Provide a specific Intel FPGA device PCI BDF. Can be provided multiple 92 times for additional instances. 93 94- ``port`` [int] 95 96 Each FPGA can provide many channels to PR AFU by software, each channels 97 is identified by this parameter. 98 99- ``afu_bts`` [string] 100 101 If null, the AFU Bit Stream has been PR in FPGA, if not forces PR and 102 identifies AFU Bit Stream file. 103