1.. SPDX-License-Identifier: BSD-3-Clause 2 Copyright(c) 2019 Intel Corporation. 3 4IPN3KE Poll Mode Driver 5======================= 6 7The ipn3ke PMD (**librte_net_ipn3ke**) provides poll mode driver support 8for Intel® FPGA PAC(Programmable Acceleration Card) N3000 based on 9the Intel Ethernet Controller X710/XXV710 and Intel Arria 10 FPGA. 10 11In this card, FPGA is an acceleration bridge between network interface 12and the Intel Ethernet Controller. Although both FPGA and Ethernet 13Controllers are connected to CPU with PCIe Gen3x16 Switch, all the 14packet RX/TX is handled by Intel Ethernet Controller. So from application 15point of view the data path is still the legacy Intel Ethernet Controller 16X710/XXV710 PMD. Besides this, users can enable more acceleration 17features by FPGA IP. 18 19Prerequisites 20------------- 21 22- Identifying your adapter using `Intel Support 23 <http://www.intel.com/support>`_ and get the latest NVM/FW images. 24 25- Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment. 26 27- To get better performance on Intel platforms, please follow the "How to get best performance with NICs on Intel platforms" 28 section of the :ref:`Getting Started Guide for Linux <linux_gsg>`. 29 30 31Pre-Installation Configuration 32------------------------------ 33 34 35Runtime Config Options 36~~~~~~~~~~~~~~~~~~~~~~ 37 38- ``AFU name`` 39 40 AFU name identifies which AFU is used by IPN3KE. The AFU name format is "Port|BDF", 41 Each FPGA can be divided into four blocks at most. "Port" identifies which FPGA block 42 the AFU bitstream belongs to, but currently only 0 IPN3KE support. "BDF" means FPGA PCIe BDF. 43 For example:: 44 45 --vdev 'ipn3ke_cfg0,afu=0|b3:00.0' 46 47- ``FPGA Acceleration list`` 48 49 For IPN3KE FPGA can provide different bitstream, different bitstream includes different 50 Acceleration, so users need to identify which Acceleration is used. Current IPN3KE can 51 support TM and Flow Acceleration, for example:: 52 53 --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,fpga_acc={tm|flow}' 54 55- ``I40e PF name list`` 56 57 Users need to bind FPGA LineSidePort to FVL PF. So I40e PF name list should be involved in 58 startup command. For example:: 59 60 --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,fpga_acc={tm|flow},i40e_pf={0000:b1:00.0|0000:b1:00.1|0000:b1:00.2|0000:b1:00.3|0000:b5:00.0|0000:b5:00.1|0000:b5:00.2|0000:b5:00.3}' 61 62Driver compilation and testing 63------------------------------ 64 65Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>` 66for details. 67 68Sample Application Notes 69------------------------ 70 71Packet TX/RX with FPGA Pass-through image 72~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 73 74FPGA Pass-through bitstream is original FPGA Image. 75 76To start ``testpmd``, and add I40e PF to FPGA network port: 77 78.. code-block:: console 79 80 ./<build_dir>/app/dpdk-testpmd -l 0-15 -n 4 --vdev 'ifpga_rawdev_cfg0,ifpga=b3:00.0,port=0' --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,i40e_pf={0000:b1:00.0|0000:b1:00.1|0000:b1:00.2|0000:b1:00.3|0000:b5:00.0|0000:b5:00.1|0000:b5:00.2|0000:b5:00.3}' -- -i --no-numa --port-topology=loop 81 82HQoS and flow acceleration 83~~~~~~~~~~~~~~~~~~~~~~~~~~ 84 85HQoS and flow acceleration bitstream is used to offloading HQoS and flow classifier. 86 87To start ``testpmd``, and add I40e PF to FPGA network port, enable FPGA HQoS and Flow Acceleration: 88 89.. code-block:: console 90 91 ./<build_dir>/app/dpdk-testpmd -l 0-15 -n 4 --vdev 'ifpga_rawdev_cfg0,ifpga=b3:00.0,port=0' --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,fpga_acc={tm|flow},i40e_pf={0000:b1:00.0|0000:b1:00.1|0000:b1:00.2|0000:b1:00.3|0000:b5:00.0|0000:b5:00.1|0000:b5:00.2|0000:b5:00.3}' -- -i --no-numa --forward-mode=macswap 92 93Limitations or Known issues 94--------------------------- 95 9619.05 limitation 97~~~~~~~~~~~~~~~~ 98 99Ipn3ke code released in 19.05 is for evaluation only. 100