xref: /dpdk/doc/guides/nics/ipn3ke.rst (revision b583b9a1bb49e86aa0937d55415713282000c536)
1c01c748eSRosen Xu..  SPDX-License-Identifier: BSD-3-Clause
2c01c748eSRosen Xu    Copyright(c) 2019 Intel Corporation.
3c01c748eSRosen Xu
4c01c748eSRosen XuIPN3KE Poll Mode Driver
5c01c748eSRosen Xu=======================
6c01c748eSRosen Xu
78809f78cSBruce RichardsonThe ipn3ke PMD (**librte_net_ipn3ke**) provides poll mode driver support
8c01c748eSRosen Xufor Intel® FPGA PAC(Programmable Acceleration Card) N3000 based on
9c01c748eSRosen Xuthe Intel Ethernet Controller X710/XXV710 and Intel Arria 10 FPGA.
10c01c748eSRosen Xu
11c01c748eSRosen XuIn this card, FPGA is an acceleration bridge between network interface
12c01c748eSRosen Xuand the Intel Ethernet Controller. Although both FPGA and Ethernet
13c01c748eSRosen XuControllers are connected to CPU with PCIe Gen3x16 Switch, all the
14c01c748eSRosen Xupacket RX/TX is handled by Intel Ethernet Controller. So from application
15c01c748eSRosen Xupoint of view the data path is still the legacy Intel Ethernet Controller
16c01c748eSRosen XuX710/XXV710 PMD. Besides this, users can enable more acceleration
17c01c748eSRosen Xufeatures by FPGA IP.
18c01c748eSRosen Xu
19c01c748eSRosen XuPrerequisites
20c01c748eSRosen Xu-------------
21c01c748eSRosen Xu
22c01c748eSRosen Xu- Identifying your adapter using `Intel Support
23c01c748eSRosen Xu  <http://www.intel.com/support>`_ and get the latest NVM/FW images.
24c01c748eSRosen Xu
25c01c748eSRosen Xu- Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment.
26c01c748eSRosen Xu
27c01c748eSRosen Xu- To get better performance on Intel platforms, please follow the "How to get best performance with NICs on Intel platforms"
28c01c748eSRosen Xu  section of the :ref:`Getting Started Guide for Linux <linux_gsg>`.
29c01c748eSRosen Xu
30c01c748eSRosen Xu
31*b583b9a1SFerruh YigitConfiguration
32*b583b9a1SFerruh Yigit-------------
33c01c748eSRosen Xu
34*b583b9a1SFerruh YigitRuntime Configuration
35*b583b9a1SFerruh Yigit~~~~~~~~~~~~~~~~~~~~~
36c01c748eSRosen Xu
37c01c748eSRosen Xu- ``AFU name``
38c01c748eSRosen Xu
39c01c748eSRosen Xu  AFU name identifies which AFU is used by IPN3KE. The AFU name format is "Port|BDF",
40c01c748eSRosen Xu  Each FPGA can be divided into four blocks at most. "Port" identifies which FPGA block
41c01c748eSRosen Xu  the AFU bitstream belongs to, but currently only 0 IPN3KE support. "BDF" means FPGA PCIe BDF.
42c01c748eSRosen Xu  For example::
43c01c748eSRosen Xu
44c01c748eSRosen Xu    --vdev 'ipn3ke_cfg0,afu=0|b3:00.0'
45c01c748eSRosen Xu
46c01c748eSRosen Xu- ``FPGA Acceleration list``
47c01c748eSRosen Xu
48c01c748eSRosen Xu  For IPN3KE FPGA can provide different bitstream, different bitstream includes different
49c01c748eSRosen Xu  Acceleration, so users need to identify which Acceleration is used. Current IPN3KE can
50c01c748eSRosen Xu  support TM and Flow Acceleration, for example::
51c01c748eSRosen Xu
52c01c748eSRosen Xu    --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,fpga_acc={tm|flow}'
53c01c748eSRosen Xu
54c01c748eSRosen Xu- ``I40e PF name list``
55c01c748eSRosen Xu
56c01c748eSRosen Xu  Users need to bind FPGA LineSidePort to FVL PF. So I40e PF name list should be involved in
57c01c748eSRosen Xu  startup command. For example::
58c01c748eSRosen Xu
59c01c748eSRosen Xu    --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,fpga_acc={tm|flow},i40e_pf={0000:b1:00.0|0000:b1:00.1|0000:b1:00.2|0000:b1:00.3|0000:b5:00.0|0000:b5:00.1|0000:b5:00.2|0000:b5:00.3}'
60c01c748eSRosen Xu
61c01c748eSRosen XuDriver compilation and testing
62c01c748eSRosen Xu------------------------------
63c01c748eSRosen Xu
64c01c748eSRosen XuRefer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`
65c01c748eSRosen Xufor details.
66c01c748eSRosen Xu
67c01c748eSRosen XuSample Application Notes
68c01c748eSRosen Xu------------------------
69c01c748eSRosen Xu
70c01c748eSRosen XuPacket TX/RX with FPGA Pass-through image
71c01c748eSRosen Xu~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
72c01c748eSRosen Xu
73c01c748eSRosen XuFPGA Pass-through bitstream is original FPGA Image.
74c01c748eSRosen Xu
75c01c748eSRosen XuTo start ``testpmd``, and add I40e PF to FPGA network port:
76c01c748eSRosen Xu
77c01c748eSRosen Xu.. code-block:: console
78c01c748eSRosen Xu
7968d99d00SCiara Power    ./<build_dir>/app/dpdk-testpmd -l 0-15 -n 4 --vdev 'ifpga_rawdev_cfg0,ifpga=b3:00.0,port=0' --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,i40e_pf={0000:b1:00.0|0000:b1:00.1|0000:b1:00.2|0000:b1:00.3|0000:b5:00.0|0000:b5:00.1|0000:b5:00.2|0000:b5:00.3}' -- -i --no-numa --port-topology=loop
80c01c748eSRosen Xu
81c01c748eSRosen XuHQoS and flow acceleration
82c01c748eSRosen Xu~~~~~~~~~~~~~~~~~~~~~~~~~~
83c01c748eSRosen Xu
84c01c748eSRosen XuHQoS and flow acceleration bitstream is used to offloading HQoS and flow classifier.
85c01c748eSRosen Xu
86c01c748eSRosen XuTo start ``testpmd``, and add I40e PF to FPGA network port, enable FPGA HQoS and Flow Acceleration:
87c01c748eSRosen Xu
88c01c748eSRosen Xu.. code-block:: console
89c01c748eSRosen Xu
9068d99d00SCiara Power    ./<build_dir>/app/dpdk-testpmd -l 0-15 -n 4 --vdev 'ifpga_rawdev_cfg0,ifpga=b3:00.0,port=0' --vdev 'ipn3ke_cfg0,afu=0|b3:00.0,fpga_acc={tm|flow},i40e_pf={0000:b1:00.0|0000:b1:00.1|0000:b1:00.2|0000:b1:00.3|0000:b5:00.0|0000:b5:00.1|0000:b5:00.2|0000:b5:00.3}' -- -i --no-numa --forward-mode=macswap
91c01c748eSRosen Xu
92c01c748eSRosen XuLimitations or Known issues
93c01c748eSRosen Xu---------------------------
94c01c748eSRosen Xu
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