1.. SPDX-License-Identifier: BSD-3-Clause 2 Copyright(c) 2015-2019 Intel Corporation. 3 4Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver 5================================================== 6 7QAT documentation consists of three parts: 8 9* Details of the symmetric and asymmetric crypto services below. 10* Details of the :doc:`compression service <../compressdevs/qat_comp>` 11 in the compressdev drivers section. 12* Details of building the common QAT infrastructure and the PMDs to support the 13 above services. See :ref:`building_qat` below. 14 15 16Symmetric Crypto Service on QAT 17------------------------------- 18 19The QAT symmetric crypto PMD (hereafter referred to as `QAT SYM [PMD]`) provides 20poll mode crypto driver support for the following hardware accelerator devices: 21 22* ``Intel QuickAssist Technology DH895xCC`` 23* ``Intel QuickAssist Technology C62x`` 24* ``Intel QuickAssist Technology C3xxx`` 25* ``Intel QuickAssist Technology D15xx`` 26* ``Intel QuickAssist Technology P5xxx`` 27 28 29Features 30~~~~~~~~ 31 32The QAT SYM PMD has support for: 33 34Cipher algorithms: 35 36* ``RTE_CRYPTO_CIPHER_3DES_CBC`` 37* ``RTE_CRYPTO_CIPHER_3DES_CTR`` 38* ``RTE_CRYPTO_CIPHER_AES128_CBC`` 39* ``RTE_CRYPTO_CIPHER_AES192_CBC`` 40* ``RTE_CRYPTO_CIPHER_AES256_CBC`` 41* ``RTE_CRYPTO_CIPHER_AES128_CTR`` 42* ``RTE_CRYPTO_CIPHER_AES192_CTR`` 43* ``RTE_CRYPTO_CIPHER_AES256_CTR`` 44* ``RTE_CRYPTO_CIPHER_AES_XTS`` 45* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2`` 46* ``RTE_CRYPTO_CIPHER_NULL`` 47* ``RTE_CRYPTO_CIPHER_KASUMI_F8`` 48* ``RTE_CRYPTO_CIPHER_DES_CBC`` 49* ``RTE_CRYPTO_CIPHER_AES_DOCSISBPI`` 50* ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI`` 51* ``RTE_CRYPTO_CIPHER_ZUC_EEA3`` 52 53Hash algorithms: 54 55* ``RTE_CRYPTO_AUTH_SHA1_HMAC`` 56* ``RTE_CRYPTO_AUTH_SHA224_HMAC`` 57* ``RTE_CRYPTO_AUTH_SHA256_HMAC`` 58* ``RTE_CRYPTO_AUTH_SHA384_HMAC`` 59* ``RTE_CRYPTO_AUTH_SHA512_HMAC`` 60* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC`` 61* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` 62* ``RTE_CRYPTO_AUTH_MD5_HMAC`` 63* ``RTE_CRYPTO_AUTH_NULL`` 64* ``RTE_CRYPTO_AUTH_KASUMI_F9`` 65* ``RTE_CRYPTO_AUTH_AES_GMAC`` 66* ``RTE_CRYPTO_AUTH_ZUC_EIA3`` 67* ``RTE_CRYPTO_AUTH_AES_CMAC`` 68 69Supported AEAD algorithms: 70 71* ``RTE_CRYPTO_AEAD_AES_GCM`` 72* ``RTE_CRYPTO_AEAD_AES_CCM`` 73 74 75Supported Chains 76~~~~~~~~~~~~~~~~ 77 78All the usual chains are supported and also some mixed chains: 79 80.. table:: Supported hash-cipher chains for wireless digest-encrypted cases 81 82 +------------------+-----------+-------------+----------+----------+ 83 | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC | 84 +==================+===========+=============+==========+==========+ 85 | NULL CIPHER | Y | 2&3 | 2&3 | Y | 86 +------------------+-----------+-------------+----------+----------+ 87 | SNOW3G UEA2 | 2&3 | Y | 2&3 | 2&3 | 88 +------------------+-----------+-------------+----------+----------+ 89 | ZUC EEA3 | 2&3 | 2&3 | 2&3 | 2&3 | 90 +------------------+-----------+-------------+----------+----------+ 91 | AES CTR | Y | 2&3 | 2&3 | Y | 92 +------------------+-----------+-------------+----------+----------+ 93 94* The combinations marked as "Y" are supported on all QAT hardware versions. 95* The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only. 96 97 98Limitations 99~~~~~~~~~~~ 100 101* Only supports the session-oriented API implementation (session-less APIs are not supported). 102* SNOW 3G (UEA2), KASUMI (F8) and ZUC (EEA3) supported only if cipher length and offset fields are byte-multiple. 103* SNOW 3G (UIA2) and ZUC (EIA3) supported only if hash length and offset fields are byte-multiple. 104* No BSD support as BSD QAT kernel driver not available. 105* ZUC EEA3/EIA3 is not supported by dh895xcc devices 106* Maximum additional authenticated data (AAD) for GCM is 240 bytes long and must be passed to the device in a buffer rounded up to the nearest block-size multiple (x16) and padded with zeros. 107* Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single 108 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues 109 from the RX queue must be done from one thread, but enqueues and dequeues may be done 110 in different threads.) 111* A GCM limitation exists, but only in the case where there are multiple 112 generations of QAT devices on a single platform. 113 To optimise performance, the GCM crypto session should be initialised for the 114 device generation to which the ops will be enqueued. Specifically if a GCM 115 session is initialised on a GEN2 device, but then attached to an op enqueued 116 to a GEN3 device, it will work but cannot take advantage of hardware 117 optimisations in the GEN3 device. And if a GCM session is initialised on a 118 GEN3 device, then attached to an op sent to a GEN1/GEN2 device, it will not be 119 enqueued to the device and will be marked as failed. The simplest way to 120 mitigate this is to use the bdf whitelist to avoid mixing devices of different 121 generations in the same process if planning to use for GCM. 122* The mixed algo feature on GEN2 is not supported by all kernel drivers. Check 123 the notes under the Available Kernel Drivers table below for specific details. 124 125Extra notes on KASUMI F9 126~~~~~~~~~~~~~~~~~~~~~~~~ 127 128When using KASUMI F9 authentication algorithm, the input buffer must be 129constructed according to the 130`3GPP KASUMI specification <http://cryptome.org/3gpp/35201-900.pdf>`_ 131(section 4.4, page 13). The input buffer has to have COUNT (4 bytes), 132FRESH (4 bytes), MESSAGE and DIRECTION (1 bit) concatenated. After the DIRECTION 133bit, a single '1' bit is appended, followed by between 0 and 7 '0' bits, so that 134the total length of the buffer is multiple of 8 bits. Note that the actual 135message can be any length, specified in bits. 136 137Once this buffer is passed this way, when creating the crypto operation, 138length of data to authenticate "op.sym.auth.data.length" must be the length 139of all the items described above, including the padding at the end. 140Also, offset of data to authenticate "op.sym.auth.data.offset" 141must be such that points at the start of the COUNT bytes. 142 143Asymmetric Crypto Service on QAT 144-------------------------------- 145 146The QAT asymmetric crypto PMD (hereafter referred to as `QAT ASYM [PMD]`) provides 147poll mode crypto driver support for the following hardware accelerator devices: 148 149* ``Intel QuickAssist Technology DH895xCC`` 150* ``Intel QuickAssist Technology C62x`` 151* ``Intel QuickAssist Technology C3xxx`` 152* ``Intel QuickAssist Technology D15xx`` 153* ``Intel QuickAssist Technology P5xxx`` 154 155The QAT ASYM PMD has support for: 156 157* ``RTE_CRYPTO_ASYM_XFORM_MODEX`` 158* ``RTE_CRYPTO_ASYM_XFORM_MODINV`` 159 160Limitations 161~~~~~~~~~~~ 162 163* Big integers longer than 4096 bits are not supported. 164* Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single 165 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues 166 from the RX queue must be done from one thread, but enqueues and dequeues may be done 167 in different threads.) 168* RSA-2560, RSA-3584 are not supported 169 170.. _building_qat: 171 172Building PMDs on QAT 173-------------------- 174 175A QAT device can host multiple acceleration services: 176 177* symmetric cryptography 178* data compression 179* asymmetric cryptography 180 181These services are provided to DPDK applications via PMDs which register to 182implement the corresponding cryptodev and compressdev APIs. The PMDs use 183common QAT driver code which manages the QAT PCI device. They also depend on a 184QAT kernel driver being installed on the platform, see :ref:`qat_kernel` below. 185 186 187Configuring and Building the DPDK QAT PMDs 188~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 189 190 191Further information on configuring, building and installing DPDK is described 192:doc:`here <../linux_gsg/build_dpdk>`. 193 194 195Quick instructions for QAT cryptodev PMD are as follows: 196 197.. code-block:: console 198 199 cd to the top-level DPDK directory 200 make defconfig 201 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config 202 or/and 203 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM\)=n,\1=y,' build/.config 204 make 205 206Quick instructions for QAT compressdev PMD are as follows: 207 208.. code-block:: console 209 210 cd to the top-level DPDK directory 211 make defconfig 212 make 213 214 215.. _building_qat_config: 216 217Build Configuration 218~~~~~~~~~~~~~~~~~~~ 219 220These are the build configuration options affecting QAT, and their default values: 221 222.. code-block:: console 223 224 CONFIG_RTE_LIBRTE_PMD_QAT=y 225 CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n 226 CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n 227 CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48 228 CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536 229 230CONFIG_RTE_LIBRTE_PMD_QAT must be enabled for any QAT PMD to be built. 231 232Both QAT SYM PMD and QAT ASYM PMD have an external dependency on libcrypto, so are not 233built by default. CONFIG_RTE_LIBRTE_PMD_QAT_SYM/ASYM should be enabled to build them. 234 235The QAT compressdev PMD has no external dependencies, so needs no configuration 236options and is built by default. 237 238The number of VFs per PF varies - see table below. If multiple QAT packages are 239installed on a platform then CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES should be 240adjusted to the number of VFs which the QAT common code will need to handle. 241 242.. Note:: 243 244 There are separate config items (not QAT-specific) for max cryptodevs 245 CONFIG_RTE_CRYPTO_MAX_DEVS and max compressdevs CONFIG_RTE_COMPRESS_MAX_DEVS, 246 if necessary these should be adjusted to handle the total of QAT and other 247 devices which the process will use. In particular for crypto, where each 248 QAT VF may expose two crypto devices, sym and asym, it may happen that the 249 number of devices will be bigger than MAX_DEVS and the process will show an error 250 during PMD initialisation. To avoid this problem CONFIG_RTE_CRYPTO_MAX_DEVS may be 251 increased or -w, pci-whitelist domain:bus:devid:func option may be used. 252 253 254QAT compression PMD needs intermediate buffers to support Deflate compression 255with Dynamic Huffman encoding. CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 256specifies the size of a single buffer, the PMD will allocate a multiple of these, 257plus some extra space for associated meta-data. For GEN2 devices, 20 buffers are 258allocated while for GEN1 devices, 12 buffers are allocated, plus 1472 bytes overhead. 259 260.. Note:: 261 262 If the compressed output of a Deflate operation using Dynamic Huffman 263 Encoding is too big to fit in an intermediate buffer, then the 264 operation will be split into smaller operations and their results will 265 be merged afterwards. 266 This is not possible if any checksum calculation was requested - in such 267 case the code falls back to fixed compression. 268 To avoid this less performant case, applications should configure 269 the intermediate buffer size to be larger than the expected input data size 270 (compressed output size is usually unknown, so the only option is to make 271 larger than the input size). 272 273 274Running QAT PMD with minimum threshold for burst size 275~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 276 277If only a small number or packets can be enqueued. Each enqueue causes an expensive MMIO write. 278These MMIO write occurrences can be optimised by setting any of the following parameters: 279 280- qat_sym_enq_threshold 281- qat_asym_enq_threshold 282- qat_comp_enq_threshold 283 284When any of these parameters is set rte_cryptodev_enqueue_burst function will 285return 0 (thereby avoiding an MMIO) if the device is congested and number of packets 286possible to enqueue is smaller. 287To use this feature the user must set the parameter on process start as a device additional parameter:: 288 289 -w 03:01.1,qat_sym_enq_threshold=32,qat_comp_enq_threshold=16 290 291All parameters can be used with the same device regardless of order. Parameters are separated 292by comma. When the same parameter is used more than once first occurrence of the parameter 293is used. 294Maximum threshold that can be set is 32. 295 296 297Device and driver naming 298~~~~~~~~~~~~~~~~~~~~~~~~ 299 300* The qat cryptodev symmetric crypto driver name is "crypto_qat". 301* The qat cryptodev asymmetric crypto driver name is "crypto_qat_asym". 302 303The "rte_cryptodev_devices_get()" returns the devices exposed by either of these drivers. 304 305* Each qat sym crypto device has a unique name, in format 306 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_sym". 307* Each qat asym crypto device has a unique name, in format 308 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_asym". 309 This name can be passed to "rte_cryptodev_get_dev_id()" to get the device_id. 310 311.. Note:: 312 313 The cryptodev driver name is passed to the dpdk-test-crypto-perf tool in the "-devtype" parameter. 314 315 The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler. 316 317* The qat compressdev driver name is "compress_qat". 318 The rte_compressdev_devices_get() returns the devices exposed by this driver. 319 320* Each qat compression device has a unique name, in format 321 <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp". 322 This name can be passed to rte_compressdev_get_dev_id() to get the device_id. 323 324.. _qat_kernel: 325 326Dependency on the QAT kernel driver 327~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 328 329To use QAT an SRIOV-enabled QAT kernel driver is required. The VF 330devices created and initialised by this driver will be used by the QAT PMDs. 331 332Instructions for installation are below, but first an explanation of the 333relationships between the PF/VF devices and the PMDs visible to 334DPDK applications. 335 336Each QuickAssist PF device exposes a number of VF devices. Each VF device can 337enable one symmetric cryptodev PMD and/or one asymmetric cryptodev PMD and/or 338one compressdev PMD. 339These QAT PMDs share the same underlying device and pci-mgmt code, but are 340enumerated independently on their respective APIs and appear as independent 341devices to applications. 342 343.. Note:: 344 345 Each VF can only be used by one DPDK process. It is not possible to share 346 the same VF across multiple processes, even if these processes are using 347 different acceleration services. 348 349 Conversely one DPDK process can use one or more QAT VFs and can expose both 350 cryptodev and compressdev instances on each of those VFs. 351 352 353Available kernel drivers 354~~~~~~~~~~~~~~~~~~~~~~~~ 355 356Kernel drivers for each device for each service are listed in the following table. (Scroll right 357to see the full table) 358 359 360.. _table_qat_pmds_drivers: 361 362.. table:: QAT device generations, devices and drivers 363 364 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 365 | S | A | C | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF | 366 +=====+=====+=====+=====+==========+===============+===============+============+========+======+========+========+ 367 | Yes | No | No | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 | 368 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 369 | Yes | Yes | No | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | 370 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 371 | Yes | Yes | Yes | " | " | 01.org/4.3.0+ | " | " | " | " | " | " | 372 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 373 | Yes | No | No | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 | 374 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 375 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | 376 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 377 | Yes | No | No | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 | 378 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 379 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | 380 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 381 | Yes | No | No | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | 382 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 383 | Yes | No | No | 3 | P5xxx | p | qat_p5xxx | p5xxx | 18a0 | 1 | 18a1 | 128 | 384 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 385 386* Note: Symmetric mixed crypto algorithms feature on Gen 2 works only with 01.org driver version 4.9.0+ 387 388The first 3 columns indicate the service: 389 390* S = Symmetric crypto service (via cryptodev API) 391* A = Asymmetric crypto service (via cryptodev API) 392* C = Compression service (via compressdev API) 393 394The ``Driver`` column indicates either the Linux kernel version in which 395support for this device was introduced or a driver available on Intel's 01.org 396website. There are both linux in-tree and 01.org kernel drivers available for some 397devices. p = release pending. 398 399If you are running on a kernel which includes a driver for your device, see 400`Installation using kernel.org driver`_ below. Otherwise see 401`Installation using 01.org QAT driver`_. 402 403 404Installation using kernel.org driver 405~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 406 407The examples below are based on the C62x device, if you have a different device 408use the corresponding values in the above table. 409 410In BIOS ensure that SRIOV is enabled and either: 411 412* Disable VT-d or 413* Enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file. 414 415Check that the QAT driver is loaded on your system, by executing:: 416 417 lsmod | grep qa 418 419You should see the kernel module for your device listed, e.g.:: 420 421 qat_c62x 5626 0 422 intel_qat 82336 1 qat_c62x 423 424Next, you need to expose the Virtual Functions (VFs) using the sysfs file system. 425 426First find the BDFs (Bus-Device-Function) of the physical functions (PFs) of 427your device, e.g.:: 428 429 lspci -d:37c8 430 431You should see output similar to:: 432 433 1a:00.0 Co-processor: Intel Corporation Device 37c8 434 3d:00.0 Co-processor: Intel Corporation Device 37c8 435 3f:00.0 Co-processor: Intel Corporation Device 37c8 436 437Enable the VFs for each PF by echoing the number of VFs per PF to the pci driver:: 438 439 echo 16 > /sys/bus/pci/drivers/c6xx/0000:1a:00.0/sriov_numvfs 440 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3d:00.0/sriov_numvfs 441 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3f:00.0/sriov_numvfs 442 443Check that the VFs are available for use. For example ``lspci -d:37c9`` should 444list 48 VF devices available for a ``C62x`` device. 445 446To complete the installation follow the instructions in 447`Binding the available VFs to the DPDK UIO driver`_. 448 449.. Note:: 450 451 If the QAT kernel modules are not loaded and you see an error like ``Failed 452 to load MMP firmware qat_895xcc_mmp.bin`` in kernel logs, this may be as a 453 result of not using a distribution, but just updating the kernel directly. 454 455 Download firmware from the `kernel firmware repo 456 <http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/>`_. 457 458 Copy qat binaries to ``/lib/firmware``:: 459 460 cp qat_895xcc.bin /lib/firmware 461 cp qat_895xcc_mmp.bin /lib/firmware 462 463 Change to your linux source root directory and start the qat kernel modules:: 464 465 insmod ./drivers/crypto/qat/qat_common/intel_qat.ko 466 insmod ./drivers/crypto/qat/qat_dh895xcc/qat_dh895xcc.ko 467 468 469.. Note:: 470 471 If you see the following warning in ``/var/log/messages`` it can be ignored: 472 ``IOMMU should be enabled for SR-IOV to work correctly``. 473 474 475Installation using 01.org QAT driver 476~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 477 478Download the latest QuickAssist Technology Driver from `01.org 479<https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_. 480Consult the *Getting Started Guide* at the same URL for further information. 481 482The steps below assume you are: 483 484* Building on a platform with one ``C62x`` device. 485* Using package ``qat1.7.l.4.2.0-000xx.tar.gz``. 486* On Fedora26 kernel ``4.11.11-300.fc26.x86_64``. 487 488In the BIOS ensure that SRIOV is enabled and VT-d is disabled. 489 490Uninstall any existing QAT driver, for example by running: 491 492* ``./installer.sh uninstall`` in the directory where originally installed. 493 494 495Build and install the SRIOV-enabled QAT driver:: 496 497 mkdir /QAT 498 cd /QAT 499 500 # Copy the package to this location and unpack 501 tar zxof qat1.7.l.4.2.0-000xx.tar.gz 502 503 ./configure --enable-icp-sriov=host 504 make install 505 506You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0. 507You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF. 508 509Confirm the driver is correctly installed and is using firmware version 4.2.0:: 510 511 cat /sys/kernel/debug/qat<your device type and bdf>/version/fw 512 513 514Confirm the presence of 48 VF devices - 16 per PF:: 515 516 lspci -d:37c9 517 518 519To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. 520 521.. Note:: 522 523 If using a later kernel and the build fails with an error relating to 524 ``strict_stroul`` not being available apply the following patch: 525 526 .. code-block:: diff 527 528 /QAT/QAT1.6/quickassist/utilities/downloader/Target_CoreLibs/uclo/include/linux/uclo_platform.h 529 + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,5) 530 + #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (kstrtoul((str), (base), (num))) printk("Error strtoull convert %s\n", str); } 531 + #else 532 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) 533 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (strict_strtoull((str), (base), (num))) printk("Error strtoull convert %s\n", str); } 534 #else 535 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25) 536 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; strict_strtoll((str), (base), (num));} 537 #else 538 #define STR_TO_64(str, base, num, endPtr) \ 539 do { \ 540 if (str[0] == '-') \ 541 { \ 542 *(num) = -(simple_strtoull((str+1), &(endPtr), (base))); \ 543 }else { \ 544 *(num) = simple_strtoull((str), &(endPtr), (base)); \ 545 } \ 546 } while(0) 547 + #endif 548 #endif 549 #endif 550 551 552.. Note:: 553 554 If the build fails due to missing header files you may need to do following:: 555 556 sudo yum install zlib-devel 557 sudo yum install openssl-devel 558 sudo yum install libudev-devel 559 560.. Note:: 561 562 If the build or install fails due to mismatching kernel sources you may need to do the following:: 563 564 sudo yum install kernel-headers-`uname -r` 565 sudo yum install kernel-src-`uname -r` 566 sudo yum install kernel-devel-`uname -r` 567 568 569Binding the available VFs to the DPDK UIO driver 570~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 571 572Unbind the VFs from the stock driver so they can be bound to the uio driver. 573 574For an Intel(R) QuickAssist Technology DH895xCC device 575^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 576 577The unbind command below assumes ``BDFs`` of ``03:01.00-03:04.07``, if your 578VFs are different adjust the unbind command below:: 579 580 for device in $(seq 1 4); do \ 581 for fn in $(seq 0 7); do \ 582 echo -n 0000:03:0${device}.${fn} > \ 583 /sys/bus/pci/devices/0000\:03\:0${device}.${fn}/driver/unbind; \ 584 done; \ 585 done 586 587For an Intel(R) QuickAssist Technology C62x device 588^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 589 590The unbind command below assumes ``BDFs`` of ``1a:01.00-1a:02.07``, 591``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, if your VFs are different 592adjust the unbind command below:: 593 594 for device in $(seq 1 2); do \ 595 for fn in $(seq 0 7); do \ 596 echo -n 0000:1a:0${device}.${fn} > \ 597 /sys/bus/pci/devices/0000\:1a\:0${device}.${fn}/driver/unbind; \ 598 599 echo -n 0000:3d:0${device}.${fn} > \ 600 /sys/bus/pci/devices/0000\:3d\:0${device}.${fn}/driver/unbind; \ 601 602 echo -n 0000:3f:0${device}.${fn} > \ 603 /sys/bus/pci/devices/0000\:3f\:0${device}.${fn}/driver/unbind; \ 604 done; \ 605 done 606 607For Intel(R) QuickAssist Technology C3xxx or D15xx device 608^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 609 610The unbind command below assumes ``BDFs`` of ``01:01.00-01:02.07``, if your 611VFs are different adjust the unbind command below:: 612 613 for device in $(seq 1 2); do \ 614 for fn in $(seq 0 7); do \ 615 echo -n 0000:01:0${device}.${fn} > \ 616 /sys/bus/pci/devices/0000\:01\:0${device}.${fn}/driver/unbind; \ 617 done; \ 618 done 619 620Bind to the DPDK uio driver 621^^^^^^^^^^^^^^^^^^^^^^^^^^^ 622 623Install the DPDK igb_uio driver, bind the VF PCI Device id to it and use lspci 624to confirm the VF devices are now in use by igb_uio kernel driver, 625e.g. for the C62x device:: 626 627 cd to the top-level DPDK directory 628 modprobe uio 629 insmod ./build/kmod/igb_uio.ko 630 echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id 631 lspci -vvd:37c9 632 633 634Another way to bind the VFs to the DPDK UIO driver is by using the 635``dpdk-devbind.py`` script:: 636 637 cd to the top-level DPDK directory 638 ./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1 639 640Testing 641~~~~~~~ 642 643QAT SYM crypto PMD can be tested by running the test application:: 644 645 make defconfig 646 make -j 647 cd ./build/app 648 ./test -l1 -n1 -w <your qat bdf> 649 RTE>>cryptodev_qat_autotest 650 651QAT ASYM crypto PMD can be tested by running the test application:: 652 653 make defconfig 654 make -j 655 cd ./build/app 656 ./test -l1 -n1 -w <your qat bdf> 657 RTE>>cryptodev_qat_asym_autotest 658 659QAT compression PMD can be tested by running the test application:: 660 661 make defconfig 662 sed -i 's,\(CONFIG_RTE_COMPRESSDEV_TEST\)=n,\1=y,' build/.config 663 make -j 664 cd ./build/app 665 ./test -l1 -n1 -w <your qat bdf> 666 RTE>>compressdev_autotest 667 668 669Debugging 670~~~~~~~~~ 671 672There are 2 sets of trace available via the dynamic logging feature: 673 674* pmd.qat_dp exposes trace on the data-path. 675* pmd.qat_general exposes all other trace. 676 677pmd.qat exposes both sets of traces. 678They can be enabled using the log-level option (where 8=maximum log level) on 679the process cmdline, e.g. using any of the following:: 680 681 --log-level="pmd.qat_general,8" 682 --log-level="pmd.qat_dp,8" 683 --log-level="pmd.qat,8" 684 685.. Note:: 686 687 The global RTE_LOG_DP_LEVEL overrides data-path trace so must be set to 688 RTE_LOG_DEBUG to see all the trace. This variable is in config/rte_config.h 689 for meson build and config/common_base for gnu make. 690 Also the dynamic global log level overrides both sets of trace, so e.g. no 691 QAT trace would display in this case:: 692 693 --log-level="7" --log-level="pmd.qat_general,8" 694