1.. SPDX-License-Identifier: BSD-3-Clause 2 Copyright(c) 2015-2019 Intel Corporation. 3 4Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver 5================================================== 6 7QAT documentation consists of three parts: 8 9* Details of the symmetric and asymmetric crypto services below. 10* Details of the :doc:`compression service <../compressdevs/qat_comp>` 11 in the compressdev drivers section. 12* Details of building the common QAT infrastructure and the PMDs to support the 13 above services. See :ref:`building_qat` below. 14 15 16Symmetric Crypto Service on QAT 17------------------------------- 18 19The QAT symmetric crypto PMD (hereafter referred to as `QAT SYM [PMD]`) provides 20poll mode crypto driver support for the following hardware accelerator devices: 21 22* ``Intel QuickAssist Technology DH895xCC`` 23* ``Intel QuickAssist Technology C62x`` 24* ``Intel QuickAssist Technology C3xxx`` 25* ``Intel QuickAssist Technology D15xx`` 26* ``Intel QuickAssist Technology C4xxx`` 27 28 29Features 30~~~~~~~~ 31 32The QAT SYM PMD has support for: 33 34Cipher algorithms: 35 36* ``RTE_CRYPTO_CIPHER_3DES_CBC`` 37* ``RTE_CRYPTO_CIPHER_3DES_CTR`` 38* ``RTE_CRYPTO_CIPHER_AES128_CBC`` 39* ``RTE_CRYPTO_CIPHER_AES192_CBC`` 40* ``RTE_CRYPTO_CIPHER_AES256_CBC`` 41* ``RTE_CRYPTO_CIPHER_AES128_CTR`` 42* ``RTE_CRYPTO_CIPHER_AES192_CTR`` 43* ``RTE_CRYPTO_CIPHER_AES256_CTR`` 44* ``RTE_CRYPTO_CIPHER_AES_XTS`` 45* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2`` 46* ``RTE_CRYPTO_CIPHER_NULL`` 47* ``RTE_CRYPTO_CIPHER_KASUMI_F8`` 48* ``RTE_CRYPTO_CIPHER_DES_CBC`` 49* ``RTE_CRYPTO_CIPHER_AES_DOCSISBPI`` 50* ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI`` 51* ``RTE_CRYPTO_CIPHER_ZUC_EEA3`` 52 53Hash algorithms: 54 55* ``RTE_CRYPTO_AUTH_SHA1_HMAC`` 56* ``RTE_CRYPTO_AUTH_SHA224_HMAC`` 57* ``RTE_CRYPTO_AUTH_SHA256_HMAC`` 58* ``RTE_CRYPTO_AUTH_SHA384_HMAC`` 59* ``RTE_CRYPTO_AUTH_SHA512_HMAC`` 60* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC`` 61* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` 62* ``RTE_CRYPTO_AUTH_MD5_HMAC`` 63* ``RTE_CRYPTO_AUTH_NULL`` 64* ``RTE_CRYPTO_AUTH_KASUMI_F9`` 65* ``RTE_CRYPTO_AUTH_AES_GMAC`` 66* ``RTE_CRYPTO_AUTH_ZUC_EIA3`` 67* ``RTE_CRYPTO_AUTH_AES_CMAC`` 68 69Supported AEAD algorithms: 70 71* ``RTE_CRYPTO_AEAD_AES_GCM`` 72* ``RTE_CRYPTO_AEAD_AES_CCM`` 73* ``RTE_CRYPTO_AEAD_CHACHA20_POLY1305`` 74 75 76Supported Chains 77~~~~~~~~~~~~~~~~ 78 79All the usual chains are supported and also some mixed chains: 80 81.. table:: Supported hash-cipher chains for wireless digest-encrypted cases 82 83 +------------------+-----------+-------------+----------+----------+ 84 | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC | 85 +==================+===========+=============+==========+==========+ 86 | NULL CIPHER | Y | 3 | 3 | Y | 87 +------------------+-----------+-------------+----------+----------+ 88 | SNOW3G UEA2 | 3 | Y | 3 | 3 | 89 +------------------+-----------+-------------+----------+----------+ 90 | ZUC EEA3 | 3 | 3 | 2&3 | 3 | 91 +------------------+-----------+-------------+----------+----------+ 92 | AES CTR | Y | 3 | 3 | Y | 93 +------------------+-----------+-------------+----------+----------+ 94 95* The combinations marked as "Y" are supported on all QAT hardware versions. 96* The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only. 97* The combinations marked as "3" are supported on GEN3 QAT hardware only. 98 99 100Limitations 101~~~~~~~~~~~ 102 103* Only supports the session-oriented API implementation (session-less APIs are not supported). 104* SNOW 3G (UEA2), KASUMI (F8) and ZUC (EEA3) supported only if cipher length and offset fields are byte-multiple. 105* SNOW 3G (UIA2) and ZUC (EIA3) supported only if hash length and offset fields are byte-multiple. 106* No BSD support as BSD QAT kernel driver not available. 107* ZUC EEA3/EIA3 is not supported by dh895xcc devices 108* Maximum additional authenticated data (AAD) for GCM is 240 bytes long and must be passed to the device in a buffer rounded up to the nearest block-size multiple (x16) and padded with zeros. 109* Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single 110 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues 111 from the RX queue must be done from one thread, but enqueues and dequeues may be done 112 in different threads.) 113* A GCM limitation exists, but only in the case where there are multiple 114 generations of QAT devices on a single platform. 115 To optimise performance, the GCM crypto session should be initialised for the 116 device generation to which the ops will be enqueued. Specifically if a GCM 117 session is initialised on a GEN2 device, but then attached to an op enqueued 118 to a GEN3 device, it will work but cannot take advantage of hardware 119 optimisations in the GEN3 device. And if a GCM session is initialised on a 120 GEN3 device, then attached to an op sent to a GEN1/GEN2 device, it will not be 121 enqueued to the device and will be marked as failed. The simplest way to 122 mitigate this is to use the bdf whitelist to avoid mixing devices of different 123 generations in the same process if planning to use for GCM. 124 125Extra notes on KASUMI F9 126~~~~~~~~~~~~~~~~~~~~~~~~ 127 128When using KASUMI F9 authentication algorithm, the input buffer must be 129constructed according to the 130`3GPP KASUMI specification <http://cryptome.org/3gpp/35201-900.pdf>`_ 131(section 4.4, page 13). The input buffer has to have COUNT (4 bytes), 132FRESH (4 bytes), MESSAGE and DIRECTION (1 bit) concatenated. After the DIRECTION 133bit, a single '1' bit is appended, followed by between 0 and 7 '0' bits, so that 134the total length of the buffer is multiple of 8 bits. Note that the actual 135message can be any length, specified in bits. 136 137Once this buffer is passed this way, when creating the crypto operation, 138length of data to authenticate "op.sym.auth.data.length" must be the length 139of all the items described above, including the padding at the end. 140Also, offset of data to authenticate "op.sym.auth.data.offset" 141must be such that points at the start of the COUNT bytes. 142 143Asymmetric Crypto Service on QAT 144-------------------------------- 145 146The QAT asymmetric crypto PMD (hereafter referred to as `QAT ASYM [PMD]`) provides 147poll mode crypto driver support for the following hardware accelerator devices: 148 149* ``Intel QuickAssist Technology DH895xCC`` 150* ``Intel QuickAssist Technology C62x`` 151* ``Intel QuickAssist Technology C3xxx`` 152* ``Intel QuickAssist Technology D15xx`` 153* ``Intel QuickAssist Technology C4xxx`` 154 155The QAT ASYM PMD has support for: 156 157* ``RTE_CRYPTO_ASYM_XFORM_MODEX`` 158* ``RTE_CRYPTO_ASYM_XFORM_MODINV`` 159 160Limitations 161~~~~~~~~~~~ 162 163* Big integers longer than 4096 bits are not supported. 164* Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single 165 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues 166 from the RX queue must be done from one thread, but enqueues and dequeues may be done 167 in different threads.) 168* RSA-2560, RSA-3584 are not supported 169 170.. _building_qat: 171 172Building PMDs on QAT 173-------------------- 174 175A QAT device can host multiple acceleration services: 176 177* symmetric cryptography 178* data compression 179* asymmetric cryptography 180 181These services are provided to DPDK applications via PMDs which register to 182implement the corresponding cryptodev and compressdev APIs. The PMDs use 183common QAT driver code which manages the QAT PCI device. They also depend on a 184QAT kernel driver being installed on the platform, see :ref:`qat_kernel` below. 185 186 187Configuring and Building the DPDK QAT PMDs 188~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 189 190 191Further information on configuring, building and installing DPDK is described 192:doc:`here <../linux_gsg/build_dpdk>`. 193 194 195Quick instructions for QAT cryptodev PMD are as follows: 196 197.. code-block:: console 198 199 cd to the top-level DPDK directory 200 make defconfig 201 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config 202 or/and 203 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM\)=n,\1=y,' build/.config 204 make 205 206Quick instructions for QAT compressdev PMD are as follows: 207 208.. code-block:: console 209 210 cd to the top-level DPDK directory 211 make defconfig 212 make 213 214 215.. _building_qat_config: 216 217Build Configuration 218~~~~~~~~~~~~~~~~~~~ 219 220These are the build configuration options affecting QAT, and their default values: 221 222.. code-block:: console 223 224 CONFIG_RTE_LIBRTE_PMD_QAT=y 225 CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n 226 CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n 227 CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48 228 CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536 229 230CONFIG_RTE_LIBRTE_PMD_QAT must be enabled for any QAT PMD to be built. 231 232Both QAT SYM PMD and QAT ASYM PMD have an external dependency on libcrypto, so are not 233built by default. CONFIG_RTE_LIBRTE_PMD_QAT_SYM/ASYM should be enabled to build them. 234 235The QAT compressdev PMD has no external dependencies, so needs no configuration 236options and is built by default. 237 238The number of VFs per PF varies - see table below. If multiple QAT packages are 239installed on a platform then CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES should be 240adjusted to the number of VFs which the QAT common code will need to handle. 241 242.. Note:: 243 244 There are separate config items (not QAT-specific) for max cryptodevs 245 CONFIG_RTE_CRYPTO_MAX_DEVS and max compressdevs CONFIG_RTE_COMPRESS_MAX_DEVS, 246 if necessary these should be adjusted to handle the total of QAT and other 247 devices which the process will use. In particular for crypto, where each 248 QAT VF may expose two crypto devices, sym and asym, it may happen that the 249 number of devices will be bigger than MAX_DEVS and the process will show an error 250 during PMD initialisation. To avoid this problem CONFIG_RTE_CRYPTO_MAX_DEVS may be 251 increased or -w, pci-whitelist domain:bus:devid:func option may be used. 252 253 254QAT compression PMD needs intermediate buffers to support Deflate compression 255with Dynamic Huffman encoding. CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 256specifies the size of a single buffer, the PMD will allocate a multiple of these, 257plus some extra space for associated meta-data. For GEN2 devices, 20 buffers are 258allocated while for GEN1 devices, 12 buffers are allocated, plus 1472 bytes overhead. 259 260.. Note:: 261 262 If the compressed output of a Deflate operation using Dynamic Huffman 263 Encoding is too big to fit in an intermediate buffer, then the 264 operation will fall back to fixed compression rather than failing the operation. 265 To avoid this less performant case, applications should configure 266 the intermediate buffer size to be larger than the expected input data size 267 (compressed output size is usually unknown, so the only option is to make 268 larger than the input size). 269 270 271Running QAT PMD with minimum threshold for burst size 272~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 273 274If only a small number or packets can be enqueued. Each enqueue causes an expensive MMIO write. 275These MMIO write occurrences can be optimised by setting any of the following parameters: 276 277- qat_sym_enq_threshold 278- qat_asym_enq_threshold 279- qat_comp_enq_threshold 280 281When any of these parameters is set rte_cryptodev_enqueue_burst function will 282return 0 (thereby avoiding an MMIO) if the device is congested and number of packets 283possible to enqueue is smaller. 284To use this feature the user must set the parameter on process start as a device additional parameter:: 285 286 -w 03:01.1,qat_sym_enq_threshold=32,qat_comp_enq_threshold=16 287 288All parameters can be used with the same device regardless of order. Parameters are separated 289by comma. When the same parameter is used more than once first occurrence of the parameter 290is used. 291Maximum threshold that can be set is 32. 292 293 294Device and driver naming 295~~~~~~~~~~~~~~~~~~~~~~~~ 296 297* The qat cryptodev symmetric crypto driver name is "crypto_qat". 298* The qat cryptodev asymmetric crypto driver name is "crypto_qat_asym". 299 300The "rte_cryptodev_devices_get()" returns the devices exposed by either of these drivers. 301 302* Each qat sym crypto device has a unique name, in format 303 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_sym". 304* Each qat asym crypto device has a unique name, in format 305 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_asym". 306 This name can be passed to "rte_cryptodev_get_dev_id()" to get the device_id. 307 308.. Note:: 309 310 The cryptodev driver name is passed to the dpdk-test-crypto-perf tool in the "-devtype" parameter. 311 312 The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler. 313 314* The qat compressdev driver name is "compress_qat". 315 The rte_compressdev_devices_get() returns the devices exposed by this driver. 316 317* Each qat compression device has a unique name, in format 318 <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp". 319 This name can be passed to rte_compressdev_get_dev_id() to get the device_id. 320 321.. _qat_kernel: 322 323Dependency on the QAT kernel driver 324~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 325 326To use QAT an SRIOV-enabled QAT kernel driver is required. The VF 327devices created and initialised by this driver will be used by the QAT PMDs. 328 329Instructions for installation are below, but first an explanation of the 330relationships between the PF/VF devices and the PMDs visible to 331DPDK applications. 332 333Each QuickAssist PF device exposes a number of VF devices. Each VF device can 334enable one symmetric cryptodev PMD and/or one asymmetric cryptodev PMD and/or 335one compressdev PMD. 336These QAT PMDs share the same underlying device and pci-mgmt code, but are 337enumerated independently on their respective APIs and appear as independent 338devices to applications. 339 340.. Note:: 341 342 Each VF can only be used by one DPDK process. It is not possible to share 343 the same VF across multiple processes, even if these processes are using 344 different acceleration services. 345 346 Conversely one DPDK process can use one or more QAT VFs and can expose both 347 cryptodev and compressdev instances on each of those VFs. 348 349 350Available kernel drivers 351~~~~~~~~~~~~~~~~~~~~~~~~ 352 353Kernel drivers for each device for each service are listed in the following table. (Scroll right 354to see the full table) 355 356 357.. _table_qat_pmds_drivers: 358 359.. table:: QAT device generations, devices and drivers 360 361 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 362 | S | A | C | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF | 363 +=====+=====+=====+=====+==========+===============+===============+============+========+======+========+========+ 364 | Yes | No | No | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 | 365 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 366 | Yes | Yes | No | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | 367 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 368 | Yes | Yes | Yes | " | " | 01.org/4.3.0+ | " | " | " | " | " | " | 369 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 370 | Yes | No | No | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 | 371 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 372 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | 373 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 374 | Yes | No | No | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 | 375 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 376 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | 377 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 378 | Yes | No | No | 2 | D15xx | p | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | 379 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 380 | Yes | No | No | 3 | C4xxx | p | qat_c4xxx | c4xxx | 18a0 | 1 | 18a1 | 128 | 381 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 382 383The first 3 columns indicate the service: 384 385* S = Symmetric crypto service (via cryptodev API) 386* A = Asymmetric crypto service (via cryptodev API) 387* C = Compression service (via compressdev API) 388 389The ``Driver`` column indicates either the Linux kernel version in which 390support for this device was introduced or a driver available on Intel's 01.org 391website. There are both linux in-tree and 01.org kernel drivers available for some 392devices. p = release pending. 393 394If you are running on a kernel which includes a driver for your device, see 395`Installation using kernel.org driver`_ below. Otherwise see 396`Installation using 01.org QAT driver`_. 397 398 399Installation using kernel.org driver 400~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 401 402The examples below are based on the C62x device, if you have a different device 403use the corresponding values in the above table. 404 405In BIOS ensure that SRIOV is enabled and either: 406 407* Disable VT-d or 408* Enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file. 409 410Check that the QAT driver is loaded on your system, by executing:: 411 412 lsmod | grep qa 413 414You should see the kernel module for your device listed, e.g.:: 415 416 qat_c62x 5626 0 417 intel_qat 82336 1 qat_c62x 418 419Next, you need to expose the Virtual Functions (VFs) using the sysfs file system. 420 421First find the BDFs (Bus-Device-Function) of the physical functions (PFs) of 422your device, e.g.:: 423 424 lspci -d:37c8 425 426You should see output similar to:: 427 428 1a:00.0 Co-processor: Intel Corporation Device 37c8 429 3d:00.0 Co-processor: Intel Corporation Device 37c8 430 3f:00.0 Co-processor: Intel Corporation Device 37c8 431 432Enable the VFs for each PF by echoing the number of VFs per PF to the pci driver:: 433 434 echo 16 > /sys/bus/pci/drivers/c6xx/0000:1a:00.0/sriov_numvfs 435 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3d:00.0/sriov_numvfs 436 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3f:00.0/sriov_numvfs 437 438Check that the VFs are available for use. For example ``lspci -d:37c9`` should 439list 48 VF devices available for a ``C62x`` device. 440 441To complete the installation follow the instructions in 442`Binding the available VFs to the DPDK UIO driver`_. 443 444.. Note:: 445 446 If the QAT kernel modules are not loaded and you see an error like ``Failed 447 to load MMP firmware qat_895xcc_mmp.bin`` in kernel logs, this may be as a 448 result of not using a distribution, but just updating the kernel directly. 449 450 Download firmware from the `kernel firmware repo 451 <http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/>`_. 452 453 Copy qat binaries to ``/lib/firmware``:: 454 455 cp qat_895xcc.bin /lib/firmware 456 cp qat_895xcc_mmp.bin /lib/firmware 457 458 Change to your linux source root directory and start the qat kernel modules:: 459 460 insmod ./drivers/crypto/qat/qat_common/intel_qat.ko 461 insmod ./drivers/crypto/qat/qat_dh895xcc/qat_dh895xcc.ko 462 463 464.. Note:: 465 466 If you see the following warning in ``/var/log/messages`` it can be ignored: 467 ``IOMMU should be enabled for SR-IOV to work correctly``. 468 469 470Installation using 01.org QAT driver 471~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 472 473Download the latest QuickAssist Technology Driver from `01.org 474<https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_. 475Consult the *Getting Started Guide* at the same URL for further information. 476 477The steps below assume you are: 478 479* Building on a platform with one ``C62x`` device. 480* Using package ``qat1.7.l.4.2.0-000xx.tar.gz``. 481* On Fedora26 kernel ``4.11.11-300.fc26.x86_64``. 482 483In the BIOS ensure that SRIOV is enabled and VT-d is disabled. 484 485Uninstall any existing QAT driver, for example by running: 486 487* ``./installer.sh uninstall`` in the directory where originally installed. 488 489 490Build and install the SRIOV-enabled QAT driver:: 491 492 mkdir /QAT 493 cd /QAT 494 495 # Copy the package to this location and unpack 496 tar zxof qat1.7.l.4.2.0-000xx.tar.gz 497 498 ./configure --enable-icp-sriov=host 499 make install 500 501You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0. 502You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF. 503 504Confirm the driver is correctly installed and is using firmware version 4.2.0:: 505 506 cat /sys/kernel/debug/qat<your device type and bdf>/version/fw 507 508 509Confirm the presence of 48 VF devices - 16 per PF:: 510 511 lspci -d:37c9 512 513 514To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. 515 516.. Note:: 517 518 If using a later kernel and the build fails with an error relating to 519 ``strict_stroul`` not being available apply the following patch: 520 521 .. code-block:: diff 522 523 /QAT/QAT1.6/quickassist/utilities/downloader/Target_CoreLibs/uclo/include/linux/uclo_platform.h 524 + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,5) 525 + #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (kstrtoul((str), (base), (num))) printk("Error strtoull convert %s\n", str); } 526 + #else 527 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) 528 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (strict_strtoull((str), (base), (num))) printk("Error strtoull convert %s\n", str); } 529 #else 530 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25) 531 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; strict_strtoll((str), (base), (num));} 532 #else 533 #define STR_TO_64(str, base, num, endPtr) \ 534 do { \ 535 if (str[0] == '-') \ 536 { \ 537 *(num) = -(simple_strtoull((str+1), &(endPtr), (base))); \ 538 }else { \ 539 *(num) = simple_strtoull((str), &(endPtr), (base)); \ 540 } \ 541 } while(0) 542 + #endif 543 #endif 544 #endif 545 546 547.. Note:: 548 549 If the build fails due to missing header files you may need to do following:: 550 551 sudo yum install zlib-devel 552 sudo yum install openssl-devel 553 sudo yum install libudev-devel 554 555.. Note:: 556 557 If the build or install fails due to mismatching kernel sources you may need to do the following:: 558 559 sudo yum install kernel-headers-`uname -r` 560 sudo yum install kernel-src-`uname -r` 561 sudo yum install kernel-devel-`uname -r` 562 563 564Binding the available VFs to the DPDK UIO driver 565~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 566 567Unbind the VFs from the stock driver so they can be bound to the uio driver. 568 569For an Intel(R) QuickAssist Technology DH895xCC device 570^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 571 572The unbind command below assumes ``BDFs`` of ``03:01.00-03:04.07``, if your 573VFs are different adjust the unbind command below:: 574 575 for device in $(seq 1 4); do \ 576 for fn in $(seq 0 7); do \ 577 echo -n 0000:03:0${device}.${fn} > \ 578 /sys/bus/pci/devices/0000\:03\:0${device}.${fn}/driver/unbind; \ 579 done; \ 580 done 581 582For an Intel(R) QuickAssist Technology C62x device 583^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 584 585The unbind command below assumes ``BDFs`` of ``1a:01.00-1a:02.07``, 586``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, if your VFs are different 587adjust the unbind command below:: 588 589 for device in $(seq 1 2); do \ 590 for fn in $(seq 0 7); do \ 591 echo -n 0000:1a:0${device}.${fn} > \ 592 /sys/bus/pci/devices/0000\:1a\:0${device}.${fn}/driver/unbind; \ 593 594 echo -n 0000:3d:0${device}.${fn} > \ 595 /sys/bus/pci/devices/0000\:3d\:0${device}.${fn}/driver/unbind; \ 596 597 echo -n 0000:3f:0${device}.${fn} > \ 598 /sys/bus/pci/devices/0000\:3f\:0${device}.${fn}/driver/unbind; \ 599 done; \ 600 done 601 602For Intel(R) QuickAssist Technology C3xxx or D15xx device 603^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 604 605The unbind command below assumes ``BDFs`` of ``01:01.00-01:02.07``, if your 606VFs are different adjust the unbind command below:: 607 608 for device in $(seq 1 2); do \ 609 for fn in $(seq 0 7); do \ 610 echo -n 0000:01:0${device}.${fn} > \ 611 /sys/bus/pci/devices/0000\:01\:0${device}.${fn}/driver/unbind; \ 612 done; \ 613 done 614 615Bind to the DPDK uio driver 616^^^^^^^^^^^^^^^^^^^^^^^^^^^ 617 618Install the DPDK igb_uio driver, bind the VF PCI Device id to it and use lspci 619to confirm the VF devices are now in use by igb_uio kernel driver, 620e.g. for the C62x device:: 621 622 cd to the top-level DPDK directory 623 modprobe uio 624 insmod ./build/kmod/igb_uio.ko 625 echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id 626 lspci -vvd:37c9 627 628 629Another way to bind the VFs to the DPDK UIO driver is by using the 630``dpdk-devbind.py`` script:: 631 632 cd to the top-level DPDK directory 633 ./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1 634 635Testing 636~~~~~~~ 637 638QAT SYM crypto PMD can be tested by running the test application:: 639 640 make defconfig 641 make -j 642 cd ./build/app 643 ./test -l1 -n1 -w <your qat bdf> 644 RTE>>cryptodev_qat_autotest 645 646QAT ASYM crypto PMD can be tested by running the test application:: 647 648 make defconfig 649 make -j 650 cd ./build/app 651 ./test -l1 -n1 -w <your qat bdf> 652 RTE>>cryptodev_qat_asym_autotest 653 654QAT compression PMD can be tested by running the test application:: 655 656 make defconfig 657 sed -i 's,\(CONFIG_RTE_COMPRESSDEV_TEST\)=n,\1=y,' build/.config 658 make -j 659 cd ./build/app 660 ./test -l1 -n1 -w <your qat bdf> 661 RTE>>compressdev_autotest 662 663 664Debugging 665~~~~~~~~~ 666 667There are 2 sets of trace available via the dynamic logging feature: 668 669* pmd.qat_dp exposes trace on the data-path. 670* pmd.qat_general exposes all other trace. 671 672pmd.qat exposes both sets of traces. 673They can be enabled using the log-level option (where 8=maximum log level) on 674the process cmdline, e.g. using any of the following:: 675 676 --log-level="pmd.qat_general,8" 677 --log-level="pmd.qat_dp,8" 678 --log-level="pmd.qat,8" 679 680.. Note:: 681 682 The global RTE_LOG_DP_LEVEL overrides data-path trace so must be set to 683 RTE_LOG_DEBUG to see all the trace. This variable is in config/rte_config.h 684 for meson build and config/common_base for gnu make. 685 Also the dynamic global log level overrides both sets of trace, so e.g. no 686 QAT trace would display in this case:: 687 688 --log-level="7" --log-level="pmd.qat_general,8" 689