1.. SPDX-License-Identifier: BSD-3-Clause 2 Copyright(c) 2015-2019 Intel Corporation. 3 4Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver 5================================================== 6 7QAT documentation consists of three parts: 8 9* Details of the symmetric and asymmetric crypto services below. 10* Details of the :doc:`compression service <../compressdevs/qat_comp>` 11 in the compressdev drivers section. 12* Details of building the common QAT infrastructure and the PMDs to support the 13 above services. See :ref:`building_qat` below. 14 15 16Symmetric Crypto Service on QAT 17------------------------------- 18 19The QAT symmetric crypto PMD (hereafter referred to as `QAT SYM [PMD]`) provides 20poll mode crypto driver support for the following hardware accelerator devices: 21 22* ``Intel QuickAssist Technology DH895xCC`` 23* ``Intel QuickAssist Technology C62x`` 24* ``Intel QuickAssist Technology C3xxx`` 25* ``Intel QuickAssist Technology 200xx`` 26* ``Intel QuickAssist Technology D15xx`` 27* ``Intel QuickAssist Technology C4xxx`` 28 29 30Features 31~~~~~~~~ 32 33The QAT SYM PMD has support for: 34 35Cipher algorithms: 36 37* ``RTE_CRYPTO_CIPHER_3DES_CBC`` 38* ``RTE_CRYPTO_CIPHER_3DES_CTR`` 39* ``RTE_CRYPTO_CIPHER_AES128_CBC`` 40* ``RTE_CRYPTO_CIPHER_AES192_CBC`` 41* ``RTE_CRYPTO_CIPHER_AES256_CBC`` 42* ``RTE_CRYPTO_CIPHER_AES128_CTR`` 43* ``RTE_CRYPTO_CIPHER_AES192_CTR`` 44* ``RTE_CRYPTO_CIPHER_AES256_CTR`` 45* ``RTE_CRYPTO_CIPHER_AES_XTS`` 46* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2`` 47* ``RTE_CRYPTO_CIPHER_NULL`` 48* ``RTE_CRYPTO_CIPHER_KASUMI_F8`` 49* ``RTE_CRYPTO_CIPHER_DES_CBC`` 50* ``RTE_CRYPTO_CIPHER_AES_DOCSISBPI`` 51* ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI`` 52* ``RTE_CRYPTO_CIPHER_ZUC_EEA3`` 53 54Hash algorithms: 55 56* ``RTE_CRYPTO_AUTH_SHA1`` 57* ``RTE_CRYPTO_AUTH_SHA1_HMAC`` 58* ``RTE_CRYPTO_AUTH_SHA224`` 59* ``RTE_CRYPTO_AUTH_SHA224_HMAC`` 60* ``RTE_CRYPTO_AUTH_SHA256`` 61* ``RTE_CRYPTO_AUTH_SHA256_HMAC`` 62* ``RTE_CRYPTO_AUTH_SHA384`` 63* ``RTE_CRYPTO_AUTH_SHA384_HMAC`` 64* ``RTE_CRYPTO_AUTH_SHA512`` 65* ``RTE_CRYPTO_AUTH_SHA512_HMAC`` 66* ``RTE_CRYPTO_AUTH_AES_XCBC_MAC`` 67* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` 68* ``RTE_CRYPTO_AUTH_MD5_HMAC`` 69* ``RTE_CRYPTO_AUTH_NULL`` 70* ``RTE_CRYPTO_AUTH_KASUMI_F9`` 71* ``RTE_CRYPTO_AUTH_AES_GMAC`` 72* ``RTE_CRYPTO_AUTH_ZUC_EIA3`` 73* ``RTE_CRYPTO_AUTH_AES_CMAC`` 74 75Supported AEAD algorithms: 76 77* ``RTE_CRYPTO_AEAD_AES_GCM`` 78* ``RTE_CRYPTO_AEAD_AES_CCM`` 79* ``RTE_CRYPTO_AEAD_CHACHA20_POLY1305`` 80 81Protocol offloads: 82 83* ``RTE_SECURITY_PROTOCOL_DOCSIS`` 84 85Supported Chains 86~~~~~~~~~~~~~~~~ 87 88All the usual chains are supported and also some mixed chains: 89 90.. table:: Supported hash-cipher chains for wireless digest-encrypted cases 91 92 +------------------+-----------+-------------+----------+----------+ 93 | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC | 94 +==================+===========+=============+==========+==========+ 95 | NULL CIPHER | Y | 2&3 | 2&3 | Y | 96 +------------------+-----------+-------------+----------+----------+ 97 | SNOW3G UEA2 | 2&3 | Y | 2&3 | 2&3 | 98 +------------------+-----------+-------------+----------+----------+ 99 | ZUC EEA3 | 2&3 | 2&3 | 2&3 | 2&3 | 100 +------------------+-----------+-------------+----------+----------+ 101 | AES CTR | Y | 2&3 | 2&3 | Y | 102 +------------------+-----------+-------------+----------+----------+ 103 104* The combinations marked as "Y" are supported on all QAT hardware versions. 105* The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only. 106 107 108Limitations 109~~~~~~~~~~~ 110 111* Only supports the session-oriented API implementation (session-less APIs are not supported). 112* SNOW 3G (UEA2), KASUMI (F8) and ZUC (EEA3) supported only if cipher length and offset fields are byte-multiple. 113* SNOW 3G (UIA2) and ZUC (EIA3) supported only if hash length and offset fields are byte-multiple. 114* No BSD support as BSD QAT kernel driver not available. 115* ZUC EEA3/EIA3 is not supported by dh895xcc devices 116* Maximum additional authenticated data (AAD) for GCM is 240 bytes long and must be passed to the device in a buffer rounded up to the nearest block-size multiple (x16) and padded with zeros. 117* Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single 118 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues 119 from the RX queue must be done from one thread, but enqueues and dequeues may be done 120 in different threads.) 121* A GCM limitation exists, but only in the case where there are multiple 122 generations of QAT devices on a single platform. 123 To optimise performance, the GCM crypto session should be initialised for the 124 device generation to which the ops will be enqueued. Specifically if a GCM 125 session is initialised on a GEN2 device, but then attached to an op enqueued 126 to a GEN3 device, it will work but cannot take advantage of hardware 127 optimisations in the GEN3 device. And if a GCM session is initialised on a 128 GEN3 device, then attached to an op sent to a GEN1/GEN2 device, it will not be 129 enqueued to the device and will be marked as failed. The simplest way to 130 mitigate this is to use the bdf whitelist to avoid mixing devices of different 131 generations in the same process if planning to use for GCM. 132* The mixed algo feature on GEN2 is not supported by all kernel drivers. Check 133 the notes under the Available Kernel Drivers table below for specific details. 134* Out-of-place is not supported for combined Crypto-CRC DOCSIS security 135 protocol. 136* ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI`` is not supported for combined Crypto-CRC 137 DOCSIS security protocol. 138* Multi-segment buffers are not supported for combined Crypto-CRC DOCSIS 139 security protocol. 140 141Extra notes on KASUMI F9 142~~~~~~~~~~~~~~~~~~~~~~~~ 143 144When using KASUMI F9 authentication algorithm, the input buffer must be 145constructed according to the 146`3GPP KASUMI specification <http://cryptome.org/3gpp/35201-900.pdf>`_ 147(section 4.4, page 13). The input buffer has to have COUNT (4 bytes), 148FRESH (4 bytes), MESSAGE and DIRECTION (1 bit) concatenated. After the DIRECTION 149bit, a single '1' bit is appended, followed by between 0 and 7 '0' bits, so that 150the total length of the buffer is multiple of 8 bits. Note that the actual 151message can be any length, specified in bits. 152 153Once this buffer is passed this way, when creating the crypto operation, 154length of data to authenticate "op.sym.auth.data.length" must be the length 155of all the items described above, including the padding at the end. 156Also, offset of data to authenticate "op.sym.auth.data.offset" 157must be such that points at the start of the COUNT bytes. 158 159Asymmetric Crypto Service on QAT 160-------------------------------- 161 162The QAT asymmetric crypto PMD (hereafter referred to as `QAT ASYM [PMD]`) provides 163poll mode crypto driver support for the following hardware accelerator devices: 164 165* ``Intel QuickAssist Technology DH895xCC`` 166* ``Intel QuickAssist Technology C62x`` 167* ``Intel QuickAssist Technology C3xxx`` 168* ``Intel QuickAssist Technology D15xx`` 169* ``Intel QuickAssist Technology C4xxx`` 170 171The QAT ASYM PMD has support for: 172 173* ``RTE_CRYPTO_ASYM_XFORM_MODEX`` 174* ``RTE_CRYPTO_ASYM_XFORM_MODINV`` 175 176Limitations 177~~~~~~~~~~~ 178 179* Big integers longer than 4096 bits are not supported. 180* Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single 181 queue-pair all enqueues to the TX queue must be done from one thread and all dequeues 182 from the RX queue must be done from one thread, but enqueues and dequeues may be done 183 in different threads.) 184* RSA-2560, RSA-3584 are not supported 185 186.. _building_qat: 187 188Building PMDs on QAT 189-------------------- 190 191A QAT device can host multiple acceleration services: 192 193* symmetric cryptography 194* data compression 195* asymmetric cryptography 196 197These services are provided to DPDK applications via PMDs which register to 198implement the corresponding cryptodev and compressdev APIs. The PMDs use 199common QAT driver code which manages the QAT PCI device. They also depend on a 200QAT kernel driver being installed on the platform, see :ref:`qat_kernel` below. 201 202 203Configuring and Building the DPDK QAT PMDs 204~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 205 206 207Further information on configuring, building and installing DPDK is described 208:doc:`here <../linux_gsg/build_dpdk>`. 209 210 211Quick instructions for QAT cryptodev PMD are as follows: 212 213.. code-block:: console 214 215 cd to the top-level DPDK directory 216 make defconfig 217 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config 218 or/and 219 sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM\)=n,\1=y,' build/.config 220 make 221 222Quick instructions for QAT compressdev PMD are as follows: 223 224.. code-block:: console 225 226 cd to the top-level DPDK directory 227 make defconfig 228 make 229 230 231.. _building_qat_config: 232 233Build Configuration 234~~~~~~~~~~~~~~~~~~~ 235 236These are the build configuration options affecting QAT, and their default values: 237 238.. code-block:: console 239 240 CONFIG_RTE_LIBRTE_PMD_QAT=y 241 CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n 242 CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n 243 CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48 244 CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536 245 246CONFIG_RTE_LIBRTE_PMD_QAT must be enabled for any QAT PMD to be built. 247 248Both QAT SYM PMD and QAT ASYM PMD have an external dependency on libcrypto, so are not 249built by default. CONFIG_RTE_LIBRTE_PMD_QAT_SYM/ASYM should be enabled to build them. 250 251The QAT compressdev PMD has no external dependencies, so needs no configuration 252options and is built by default. 253 254The number of VFs per PF varies - see table below. If multiple QAT packages are 255installed on a platform then CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES should be 256adjusted to the number of VFs which the QAT common code will need to handle. 257 258.. Note:: 259 260 There are separate config items (not QAT-specific) for max cryptodevs 261 CONFIG_RTE_CRYPTO_MAX_DEVS and max compressdevs CONFIG_RTE_COMPRESS_MAX_DEVS, 262 if necessary these should be adjusted to handle the total of QAT and other 263 devices which the process will use. In particular for crypto, where each 264 QAT VF may expose two crypto devices, sym and asym, it may happen that the 265 number of devices will be bigger than MAX_DEVS and the process will show an error 266 during PMD initialisation. To avoid this problem CONFIG_RTE_CRYPTO_MAX_DEVS may be 267 increased or -w, pci-whitelist domain:bus:devid:func option may be used. 268 269 270QAT compression PMD needs intermediate buffers to support Deflate compression 271with Dynamic Huffman encoding. CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 272specifies the size of a single buffer, the PMD will allocate a multiple of these, 273plus some extra space for associated meta-data. For GEN2 devices, 20 buffers are 274allocated while for GEN1 devices, 12 buffers are allocated, plus 1472 bytes overhead. 275 276.. Note:: 277 278 If the compressed output of a Deflate operation using Dynamic Huffman 279 Encoding is too big to fit in an intermediate buffer, then the 280 operation will be split into smaller operations and their results will 281 be merged afterwards. 282 This is not possible if any checksum calculation was requested - in such 283 case the code falls back to fixed compression. 284 To avoid this less performant case, applications should configure 285 the intermediate buffer size to be larger than the expected input data size 286 (compressed output size is usually unknown, so the only option is to make 287 larger than the input size). 288 289 290Running QAT PMD with minimum threshold for burst size 291~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 292 293If only a small number or packets can be enqueued. Each enqueue causes an expensive MMIO write. 294These MMIO write occurrences can be optimised by setting any of the following parameters: 295 296- qat_sym_enq_threshold 297- qat_asym_enq_threshold 298- qat_comp_enq_threshold 299 300When any of these parameters is set rte_cryptodev_enqueue_burst function will 301return 0 (thereby avoiding an MMIO) if the device is congested and number of packets 302possible to enqueue is smaller. 303To use this feature the user must set the parameter on process start as a device additional parameter:: 304 305 -w 03:01.1,qat_sym_enq_threshold=32,qat_comp_enq_threshold=16 306 307All parameters can be used with the same device regardless of order. Parameters are separated 308by comma. When the same parameter is used more than once first occurrence of the parameter 309is used. 310Maximum threshold that can be set is 32. 311 312 313Device and driver naming 314~~~~~~~~~~~~~~~~~~~~~~~~ 315 316* The qat cryptodev symmetric crypto driver name is "crypto_qat". 317* The qat cryptodev asymmetric crypto driver name is "crypto_qat_asym". 318 319The "rte_cryptodev_devices_get()" returns the devices exposed by either of these drivers. 320 321* Each qat sym crypto device has a unique name, in format 322 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_sym". 323* Each qat asym crypto device has a unique name, in format 324 "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_asym". 325 This name can be passed to "rte_cryptodev_get_dev_id()" to get the device_id. 326 327.. Note:: 328 329 The cryptodev driver name is passed to the dpdk-test-crypto-perf tool in the "-devtype" parameter. 330 331 The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler. 332 333* The qat compressdev driver name is "compress_qat". 334 The rte_compressdev_devices_get() returns the devices exposed by this driver. 335 336* Each qat compression device has a unique name, in format 337 <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp". 338 This name can be passed to rte_compressdev_get_dev_id() to get the device_id. 339 340.. _qat_kernel: 341 342Dependency on the QAT kernel driver 343~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 344 345To use QAT an SRIOV-enabled QAT kernel driver is required. The VF 346devices created and initialised by this driver will be used by the QAT PMDs. 347 348Instructions for installation are below, but first an explanation of the 349relationships between the PF/VF devices and the PMDs visible to 350DPDK applications. 351 352Each QuickAssist PF device exposes a number of VF devices. Each VF device can 353enable one symmetric cryptodev PMD and/or one asymmetric cryptodev PMD and/or 354one compressdev PMD. 355These QAT PMDs share the same underlying device and pci-mgmt code, but are 356enumerated independently on their respective APIs and appear as independent 357devices to applications. 358 359.. Note:: 360 361 Each VF can only be used by one DPDK process. It is not possible to share 362 the same VF across multiple processes, even if these processes are using 363 different acceleration services. 364 365 Conversely one DPDK process can use one or more QAT VFs and can expose both 366 cryptodev and compressdev instances on each of those VFs. 367 368 369Available kernel drivers 370~~~~~~~~~~~~~~~~~~~~~~~~ 371 372Kernel drivers for each device for each service are listed in the following table. (Scroll right 373to see the full table) 374 375 376.. _table_qat_pmds_drivers: 377 378.. table:: QAT device generations, devices and drivers 379 380 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 381 | S | A | C | Gen | Device | Driver/ver | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF | 382 +=====+=====+=====+=====+==========+===============+===============+============+========+======+========+========+ 383 | Yes | No | No | 1 | DH895xCC | linux/4.4+ | qat_dh895xcc | dh895xcc | 435 | 1 | 443 | 32 | 384 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 385 | Yes | Yes | No | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | 386 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 387 | Yes | Yes | Yes | " | " | 01.org/4.3.0+ | " | " | " | " | " | " | 388 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 389 | Yes | No | No | 2 | C62x | linux/4.5+ | qat_c62x | c6xx | 37c8 | 3 | 37c9 | 16 | 390 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 391 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | 392 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 393 | Yes | No | No | 2 | C3xxx | linux/4.5+ | qat_c3xxx | c3xxx | 19e2 | 1 | 19e3 | 16 | 394 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 395 | Yes | Yes | Yes | " | " | 01.org/4.2.0+ | " | " | " | " | " | " | 396 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 397 | Yes | No | No | 2 | 200xx | p | qat_200xx | 200xx | 18ee | 1 | 18ef | 16 | 398 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 399 | Yes | No | No | 2 | D15xx | 01.org/4.2.0+ | qat_d15xx | d15xx | 6f54 | 1 | 6f55 | 16 | 400 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 401 | Yes | No | No | 3 | C4xxx | p | qat_c4xxx | c4xxx | 18a0 | 1 | 18a1 | 128 | 402 +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+ 403 404* Note: Symmetric mixed crypto algorithms feature on Gen 2 works only with 01.org driver version 4.9.0+ 405 406The first 3 columns indicate the service: 407 408* S = Symmetric crypto service (via cryptodev API) 409* A = Asymmetric crypto service (via cryptodev API) 410* C = Compression service (via compressdev API) 411 412The ``Driver`` column indicates either the Linux kernel version in which 413support for this device was introduced or a driver available on Intel's 01.org 414website. There are both linux in-tree and 01.org kernel drivers available for some 415devices. p = release pending. 416 417If you are running on a kernel which includes a driver for your device, see 418`Installation using kernel.org driver`_ below. Otherwise see 419`Installation using 01.org QAT driver`_. 420 421 422Installation using kernel.org driver 423~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 424 425The examples below are based on the C62x device, if you have a different device 426use the corresponding values in the above table. 427 428In BIOS ensure that SRIOV is enabled and either: 429 430* Disable VT-d or 431* Enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file. 432 433Check that the QAT driver is loaded on your system, by executing:: 434 435 lsmod | grep qa 436 437You should see the kernel module for your device listed, e.g.:: 438 439 qat_c62x 5626 0 440 intel_qat 82336 1 qat_c62x 441 442Next, you need to expose the Virtual Functions (VFs) using the sysfs file system. 443 444First find the BDFs (Bus-Device-Function) of the physical functions (PFs) of 445your device, e.g.:: 446 447 lspci -d:37c8 448 449You should see output similar to:: 450 451 1a:00.0 Co-processor: Intel Corporation Device 37c8 452 3d:00.0 Co-processor: Intel Corporation Device 37c8 453 3f:00.0 Co-processor: Intel Corporation Device 37c8 454 455Enable the VFs for each PF by echoing the number of VFs per PF to the pci driver:: 456 457 echo 16 > /sys/bus/pci/drivers/c6xx/0000:1a:00.0/sriov_numvfs 458 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3d:00.0/sriov_numvfs 459 echo 16 > /sys/bus/pci/drivers/c6xx/0000:3f:00.0/sriov_numvfs 460 461Check that the VFs are available for use. For example ``lspci -d:37c9`` should 462list 48 VF devices available for a ``C62x`` device. 463 464To complete the installation follow the instructions in 465`Binding the available VFs to the DPDK UIO driver`_. 466 467.. Note:: 468 469 If the QAT kernel modules are not loaded and you see an error like ``Failed 470 to load MMP firmware qat_895xcc_mmp.bin`` in kernel logs, this may be as a 471 result of not using a distribution, but just updating the kernel directly. 472 473 Download firmware from the `kernel firmware repo 474 <http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/>`_. 475 476 Copy qat binaries to ``/lib/firmware``:: 477 478 cp qat_895xcc.bin /lib/firmware 479 cp qat_895xcc_mmp.bin /lib/firmware 480 481 Change to your linux source root directory and start the qat kernel modules:: 482 483 insmod ./drivers/crypto/qat/qat_common/intel_qat.ko 484 insmod ./drivers/crypto/qat/qat_dh895xcc/qat_dh895xcc.ko 485 486 487.. Note:: 488 489 If you see the following warning in ``/var/log/messages`` it can be ignored: 490 ``IOMMU should be enabled for SR-IOV to work correctly``. 491 492 493Installation using 01.org QAT driver 494~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 495 496Download the latest QuickAssist Technology Driver from `01.org 497<https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_. 498Consult the *Getting Started Guide* at the same URL for further information. 499 500The steps below assume you are: 501 502* Building on a platform with one ``C62x`` device. 503* Using package ``qat1.7.l.4.2.0-000xx.tar.gz``. 504* On Fedora26 kernel ``4.11.11-300.fc26.x86_64``. 505 506In the BIOS ensure that SRIOV is enabled and VT-d is disabled. 507 508Uninstall any existing QAT driver, for example by running: 509 510* ``./installer.sh uninstall`` in the directory where originally installed. 511 512 513Build and install the SRIOV-enabled QAT driver:: 514 515 mkdir /QAT 516 cd /QAT 517 518 # Copy the package to this location and unpack 519 tar zxof qat1.7.l.4.2.0-000xx.tar.gz 520 521 ./configure --enable-icp-sriov=host 522 make install 523 524You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0. 525You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF. 526 527Confirm the driver is correctly installed and is using firmware version 4.2.0:: 528 529 cat /sys/kernel/debug/qat<your device type and bdf>/version/fw 530 531 532Confirm the presence of 48 VF devices - 16 per PF:: 533 534 lspci -d:37c9 535 536 537To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_. 538 539.. Note:: 540 541 If using a later kernel and the build fails with an error relating to 542 ``strict_stroul`` not being available apply the following patch: 543 544 .. code-block:: diff 545 546 /QAT/QAT1.6/quickassist/utilities/downloader/Target_CoreLibs/uclo/include/linux/uclo_platform.h 547 + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,5) 548 + #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (kstrtoul((str), (base), (num))) printk("Error strtoull convert %s\n", str); } 549 + #else 550 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) 551 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (strict_strtoull((str), (base), (num))) printk("Error strtoull convert %s\n", str); } 552 #else 553 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25) 554 #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; strict_strtoll((str), (base), (num));} 555 #else 556 #define STR_TO_64(str, base, num, endPtr) \ 557 do { \ 558 if (str[0] == '-') \ 559 { \ 560 *(num) = -(simple_strtoull((str+1), &(endPtr), (base))); \ 561 }else { \ 562 *(num) = simple_strtoull((str), &(endPtr), (base)); \ 563 } \ 564 } while(0) 565 + #endif 566 #endif 567 #endif 568 569 570.. Note:: 571 572 If the build fails due to missing header files you may need to do following:: 573 574 sudo yum install zlib-devel 575 sudo yum install openssl-devel 576 sudo yum install libudev-devel 577 578.. Note:: 579 580 If the build or install fails due to mismatching kernel sources you may need to do the following:: 581 582 sudo yum install kernel-headers-`uname -r` 583 sudo yum install kernel-src-`uname -r` 584 sudo yum install kernel-devel-`uname -r` 585 586 587Binding the available VFs to the DPDK UIO driver 588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 589 590Unbind the VFs from the stock driver so they can be bound to the uio driver. 591 592For an Intel(R) QuickAssist Technology DH895xCC device 593^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 594 595The unbind command below assumes ``BDFs`` of ``03:01.00-03:04.07``, if your 596VFs are different adjust the unbind command below:: 597 598 for device in $(seq 1 4); do \ 599 for fn in $(seq 0 7); do \ 600 echo -n 0000:03:0${device}.${fn} > \ 601 /sys/bus/pci/devices/0000\:03\:0${device}.${fn}/driver/unbind; \ 602 done; \ 603 done 604 605For an Intel(R) QuickAssist Technology C62x device 606^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 607 608The unbind command below assumes ``BDFs`` of ``1a:01.00-1a:02.07``, 609``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, if your VFs are different 610adjust the unbind command below:: 611 612 for device in $(seq 1 2); do \ 613 for fn in $(seq 0 7); do \ 614 echo -n 0000:1a:0${device}.${fn} > \ 615 /sys/bus/pci/devices/0000\:1a\:0${device}.${fn}/driver/unbind; \ 616 617 echo -n 0000:3d:0${device}.${fn} > \ 618 /sys/bus/pci/devices/0000\:3d\:0${device}.${fn}/driver/unbind; \ 619 620 echo -n 0000:3f:0${device}.${fn} > \ 621 /sys/bus/pci/devices/0000\:3f\:0${device}.${fn}/driver/unbind; \ 622 done; \ 623 done 624 625For Intel(R) QuickAssist Technology C3xxx or 200xx or D15xx device 626^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 627 628The unbind command below assumes ``BDFs`` of ``01:01.00-01:02.07``, if your 629VFs are different adjust the unbind command below:: 630 631 for device in $(seq 1 2); do \ 632 for fn in $(seq 0 7); do \ 633 echo -n 0000:01:0${device}.${fn} > \ 634 /sys/bus/pci/devices/0000\:01\:0${device}.${fn}/driver/unbind; \ 635 done; \ 636 done 637 638Bind to the DPDK uio driver 639^^^^^^^^^^^^^^^^^^^^^^^^^^^ 640 641Install the DPDK igb_uio driver, bind the VF PCI Device id to it and use lspci 642to confirm the VF devices are now in use by igb_uio kernel driver, 643e.g. for the C62x device:: 644 645 cd to the top-level DPDK directory 646 modprobe uio 647 insmod ./build/kmod/igb_uio.ko 648 echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id 649 lspci -vvd:37c9 650 651 652Another way to bind the VFs to the DPDK UIO driver is by using the 653``dpdk-devbind.py`` script:: 654 655 cd to the top-level DPDK directory 656 ./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1 657 658Testing 659~~~~~~~ 660 661QAT SYM crypto PMD can be tested by running the test application:: 662 663 make defconfig 664 make -j 665 cd ./build/app 666 ./test -l1 -n1 -w <your qat bdf> 667 RTE>>cryptodev_qat_autotest 668 669QAT ASYM crypto PMD can be tested by running the test application:: 670 671 make defconfig 672 make -j 673 cd ./build/app 674 ./test -l1 -n1 -w <your qat bdf> 675 RTE>>cryptodev_qat_asym_autotest 676 677QAT compression PMD can be tested by running the test application:: 678 679 make defconfig 680 sed -i 's,\(CONFIG_RTE_COMPRESSDEV_TEST\)=n,\1=y,' build/.config 681 make -j 682 cd ./build/app 683 ./test -l1 -n1 -w <your qat bdf> 684 RTE>>compressdev_autotest 685 686 687Debugging 688~~~~~~~~~ 689 690There are 2 sets of trace available via the dynamic logging feature: 691 692* pmd.qat_dp exposes trace on the data-path. 693* pmd.qat_general exposes all other trace. 694 695pmd.qat exposes both sets of traces. 696They can be enabled using the log-level option (where 8=maximum log level) on 697the process cmdline, e.g. using any of the following:: 698 699 --log-level="pmd.qat_general,8" 700 --log-level="pmd.qat_dp,8" 701 --log-level="pmd.qat,8" 702 703.. Note:: 704 705 The global RTE_LOG_DP_LEVEL overrides data-path trace so must be set to 706 RTE_LOG_DEBUG to see all the trace. This variable is in config/rte_config.h 707 for meson build and config/common_base for gnu make. 708 Also the dynamic global log level overrides both sets of trace, so e.g. no 709 QAT trace would display in this case:: 710 711 --log-level="7" --log-level="pmd.qat_general,8" 712