1.. SPDX-License-Identifier: BSD-3-Clause 2 Copyright(c) 2019 Intel Corporation 3 4Intel(R) FPGA LTE FEC Poll Mode Driver 5====================================== 6 7The BBDEV FPGA LTE FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN 8Turbo Encode / Decode LTE wireless acceleration function, using Intel's PCI-e and FPGA 9based Vista Creek device. 10 11Features 12-------- 13 14FPGA LTE FEC PMD supports the following features: 15 16- Turbo Encode in the DL with total throughput of 4.5 Gbits/s 17- Turbo Decode in the UL with total throughput of 1.5 Gbits/s assuming 8 decoder iterations 18- 8 VFs per PF (physical device) 19- Maximum of 32 UL queues per VF 20- Maximum of 32 DL queues per VF 21- PCIe Gen-3 x8 Interface 22- MSI-X 23- SR-IOV 24 25 26FPGA LTE FEC PMD supports the following BBDEV capabilities: 27 28* For the turbo encode operation: 29 - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s) 30 - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass 31 - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts 32 33 34* For the turbo decode operation: 35 - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s) 36 - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave 37 - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts 38 - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR encoder i/p is supported 39 - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding 40 41 42Limitations 43----------- 44 45FPGA LTE FEC does not support the following: 46 47- Scatter-Gather function 48 49 50Installation 51-------------- 52 53Section 3 of the DPDK manual provides instructions on installing and compiling DPDK. The 54default set of bbdev compile flags may be found in config/common_base, where for example 55the flag to build the FPGA LTE FEC device, ``CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC``, is already 56set. 57 58DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual. 59The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The 60hugepage configuration of a server may be examined using: 61 62.. code-block:: console 63 64 grep Huge* /proc/meminfo 65 66 67Initialization 68-------------- 69 70When the device first powers up, its PCI Physical Functions (PF) can be listed through this command: 71 72.. code-block:: console 73 74 sudo lspci -vd1172:5052 75 76The physical and virtual functions are compatible with Linux UIO drivers: 77``vfio`` and ``igb_uio``. However, in order to work the FPGA LTE FEC device firstly needs 78to be bound to one of these linux drivers through DPDK. 79 80 81Bind PF UIO driver(s) 82~~~~~~~~~~~~~~~~~~~~~ 83 84Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use 85``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver. 86 87The igb_uio driver may be bound to the PF PCI device using one of three methods: 88 89 901. PCI functions (physical or virtual, depending on the use case) can be bound to 91the UIO driver by repeating this command for every function. 92 93.. code-block:: console 94 95 cd <dpdk-top-level-directory> 96 insmod ./build/kmod/igb_uio.ko 97 echo "1172 5052" > /sys/bus/pci/drivers/igb_uio/new_id 98 lspci -vd1172: 99 100 1012. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool 102 103.. code-block:: console 104 105 cd <dpdk-top-level-directory> 106 ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0 107 108where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd1172: 109 110 1113. A third way to bind is to use ``dpdk-setup.sh`` tool 112 113.. code-block:: console 114 115 cd <dpdk-top-level-directory> 116 ./usertools/dpdk-setup.sh 117 118 select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module' 119 or 120 select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required 121 enter PCI device ID 122 select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding 123 124 125In the same way the FPGA LTE FEC PF can be bound with vfio, but vfio driver does not 126support SR-IOV configuration right out of the box, so it will need to be patched. 127 128 129Enable Virtual Functions 130~~~~~~~~~~~~~~~~~~~~~~~~ 131 132Now, it should be visible in the printouts that PCI PF is under igb_uio control 133"``Kernel driver in use: igb_uio``" 134 135To show the number of available VFs on the device, read ``sriov_totalvfs`` file.. 136 137.. code-block:: console 138 139 cat /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_totalvfs 140 141 where 0000\:<b>\:<d>.<f> is the PCI device ID 142 143 144To enable VFs via igb_uio, echo the number of virtual functions intended to 145enable to ``max_vfs`` file.. 146 147.. code-block:: console 148 149 echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/max_vfs 150 151 152Afterwards, all VFs must be bound to appropriate UIO drivers as required, same 153way it was done with the physical function previously. 154 155Enabling SR-IOV via vfio driver is pretty much the same, except that the file 156name is different: 157 158.. code-block:: console 159 160 echo <num-of-vfs> > /sys/bus/pci/devices/0000\:<b>\:<d>.<f>/sriov_numvfs 161 162 163Configure the VFs through PF 164~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 165 166The PCI virtual functions must be configured before working or getting assigned 167to VMs/Containers. The configuration involves allocating the number of hardware 168queues, priorities, load balance, bandwidth and other settings necessary for the 169device to perform FEC functions. 170 171This configuration needs to be executed at least once after reboot or PCI FLR and can 172be achieved by using the function ``fpga_lte_fec_configure()``, which sets up the 173parameters defined in ``fpga_lte_fec_conf`` structure: 174 175.. code-block:: c 176 177 struct fpga_lte_fec_conf { 178 bool pf_mode_en; 179 uint8_t vf_ul_queues_number[FPGA_LTE_FEC_NUM_VFS]; 180 uint8_t vf_dl_queues_number[FPGA_LTE_FEC_NUM_VFS]; 181 uint8_t ul_bandwidth; 182 uint8_t dl_bandwidth; 183 uint8_t ul_load_balance; 184 uint8_t dl_load_balance; 185 uint16_t flr_time_out; 186 }; 187 188- ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and 189 VFs are mutually exclusive and cannot run simultaneously. 190 Set to 1 for PF mode enabled. 191 If PF mode is enabled all queues available in the device are assigned 192 exclusively to PF and 0 queues given to VFs. 193 194- ``vf_*l_queues_number``: defines the hardware queue mapping for every VF. 195 196- ``*l_bandwidth``: in case of congestion on PCIe interface. The device 197 allocates different bandwidth to UL and DL. The weight is configured by this 198 setting. The unit of weight is 3 code blocks. For example, if the code block 199 cbps (code block per second) ratio between UL and DL is 12:1, then the 200 configuration value should be set to 36:3. The schedule algorithm is based 201 on code block regardless the length of each block. 202 203- ``*l_load_balance``: hardware queues are load-balanced in a round-robin 204 fashion. Queues get filled first-in first-out until they reach a pre-defined 205 watermark level, if exceeded, they won't get assigned new code blocks.. 206 This watermark is defined by this setting. 207 208 If all hardware queues exceeds the watermark, no code blocks will be 209 streamed in from UL/DL code block FIFO. 210 211- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The 212 time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for 213 the FLR time out then set this setting to 0x262=610. 214 215 216An example configuration code calling the function ``fpga_lte_fec_configure()`` is shown 217below: 218 219.. code-block:: c 220 221 struct fpga_lte_fec_conf conf; 222 unsigned int i; 223 224 memset(&conf, 0, sizeof(struct fpga_lte_fec_conf)); 225 conf.pf_mode_en = 1; 226 227 for (i = 0; i < FPGA_LTE_FEC_NUM_VFS; ++i) { 228 conf.vf_ul_queues_number[i] = 4; 229 conf.vf_dl_queues_number[i] = 4; 230 } 231 conf.ul_bandwidth = 12; 232 conf.dl_bandwidth = 5; 233 conf.dl_load_balance = 64; 234 conf.ul_load_balance = 64; 235 236 /* setup FPGA PF */ 237 ret = fpga_lte_fec_configure(info->dev_name, &conf); 238 TEST_ASSERT_SUCCESS(ret, 239 "Failed to configure 4G FPGA PF for bbdev %s", 240 info->dev_name); 241 242 243Test Application 244---------------- 245 246BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing 247the functionality of FPGA LTE FEC turbo encode and turbo decode, depending on the device's 248capabilities. The test application is located under app->test-bbdev folder and has the 249following options: 250 251.. code-block:: console 252 253 "-p", "--testapp-path": specifies path to the bbdev test app. 254 "-e", "--eal-params" : EAL arguments which are passed to the test app. 255 "-t", "--timeout" : Timeout in seconds (default=300). 256 "-c", "--test-cases" : Defines test cases to run. Run all if not specified. 257 "-v", "--test-vector" : Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data). 258 "-n", "--num-ops" : Number of operations to process on device (default=32). 259 "-b", "--burst-size" : Operations enqueue/dequeue burst size (default=32). 260 "-l", "--num-lcores" : Number of lcores to run (default=16). 261 "-i", "--init-device" : Initialise PF device with default values. 262 263 264To execute the test application tool using simple turbo decode or turbo encode data, 265type one of the following: 266 267.. code-block:: console 268 269 ./test-bbdev.py -c validation -n 64 -b 8 -v ./turbo_dec_default.data 270 ./test-bbdev.py -c validation -n 64 -b 8 -v ./turbo_enc_default.data 271 272 273The test application ``test-bbdev.py``, supports the ability to configure the PF device with 274a default set of values, if the "-i" or "- -init-device" option is included. The default values 275are defined in test_bbdev_perf.c as: 276 277- VF_UL_QUEUE_VALUE 4 278- VF_DL_QUEUE_VALUE 4 279- UL_BANDWIDTH 3 280- DL_BANDWIDTH 3 281- UL_LOAD_BALANCE 128 282- DL_LOAD_BALANCE 128 283- FLR_TIMEOUT 610 284 285 286Test Vectors 287~~~~~~~~~~~~ 288 289In addition to the simple turbo decoder and turbo encoder tests, bbdev also provides 290a range of additional tests under the test_vectors folder, which may be useful. The results 291of these tests will depend on the FPGA LTE FEC capabilities: 292 293* turbo decoder tests: 294 - ``turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_high_snr.data`` 295 - ``turbo_dec_c1_k6144_r0_e10376_crc24b_sbd_negllr_low_snr.data`` 296 - ``turbo_dec_c1_k6144_r0_e34560_negllr.data`` 297 - ``turbo_dec_c1_k6144_r0_e34560_sbd_negllr.data`` 298 - ``turbo_dec_c2_k3136_r0_e4920_sbd_negllr_crc24b.data`` 299 - ``turbo_dec_c2_k3136_r0_e4920_sbd_negllr.data`` 300 301 302* turbo encoder tests: 303 - ``turbo_enc_c1_k40_r0_e1190_rm.data`` 304 - ``turbo_enc_c1_k40_r0_e1194_rm.data`` 305 - ``turbo_enc_c1_k40_r0_e1196_rm.data`` 306 - ``turbo_enc_c1_k40_r0_e272_rm.data`` 307 - ``turbo_enc_c1_k6144_r0_e18444.data`` 308 - ``turbo_enc_c1_k6144_r0_e32256_crc24b_rm.data`` 309 - ``turbo_enc_c2_k5952_r0_e17868_crc24b.data`` 310 - ``turbo_enc_c3_k4800_r2_e14412_crc24b.data`` 311 - ``turbo_enc_c4_k4800_r2_e14412_crc24b.data`` 312