1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015 Cavium, Inc 3 * Copyright(c) 2022 StarFive 4 * Copyright(c) 2022 SiFive 5 * Copyright(c) 2022 Semihalf 6 */ 7 8 #ifndef _TEST_XMMT_OPS_H_ 9 #define _TEST_XMMT_OPS_H_ 10 11 #include <rte_vect.h> 12 13 #if defined(RTE_ARCH_ARM) 14 15 /* vect_* abstraction implementation using NEON */ 16 17 /* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/ 18 #define vect_loadu_sil128(p) vld1q_s32((const int32_t *)p) 19 20 /* sets the 4 signed 32-bit integer values and returns the xmm_t variable */ 21 static __rte_always_inline xmm_t 22 vect_set_epi32(int i3, int i2, int i1, int i0) 23 { 24 int32_t data[4] = {i0, i1, i2, i3}; 25 26 return vld1q_s32(data); 27 } 28 29 #elif defined(RTE_ARCH_X86) 30 31 /* vect_* abstraction implementation using SSE */ 32 33 /* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/ 34 #define vect_loadu_sil128(p) _mm_loadu_si128(p) 35 36 /* sets the 4 signed 32-bit integer values and returns the xmm_t variable */ 37 #define vect_set_epi32(i3, i2, i1, i0) _mm_set_epi32(i3, i2, i1, i0) 38 39 #elif defined(RTE_ARCH_PPC_64) 40 41 /* vect_* abstraction implementation using ALTIVEC */ 42 43 /* loads the xmm_t value from address p(does not need to be 16-byte aligned)*/ 44 #define vect_loadu_sil128(p) vec_ld(0, p) 45 46 /* sets the 4 signed 32-bit integer values and returns the xmm_t variable */ 47 static __rte_always_inline xmm_t 48 vect_set_epi32(int i3, int i2, int i1, int i0) 49 { 50 xmm_t data = (xmm_t){i0, i1, i2, i3}; 51 52 return data; 53 } 54 55 #elif defined(RTE_ARCH_RISCV) 56 57 #define vect_loadu_sil128(p) vect_load_128(p) 58 59 /* sets the 4 signed 32-bit integer values and returns the xmm_t variable */ 60 static __rte_always_inline xmm_t 61 vect_set_epi32(int i3, int i2, int i1, int i0) 62 { 63 xmm_t data = (xmm_t){i0, i1, i2, i3}; 64 65 return data; 66 } 67 68 #endif 69 70 #endif /* _TEST_XMMT_OPS_H_ */ 71