1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "test.h" 35 36 /* 37 * Timer 38 * ===== 39 * 40 * #. Stress test 1. 41 * 42 * The objective of the timer stress tests is to check that there are no 43 * race conditions in list and status management. This test launches, 44 * resets and stops the timer very often on many cores at the same 45 * time. 46 * 47 * - Only one timer is used for this test. 48 * - On each core, the rte_timer_manage() function is called from the main 49 * loop every 3 microseconds. 50 * - In the main loop, the timer may be reset (randomly, with a 51 * probability of 0.5 %) 100 microseconds later on a random core, or 52 * stopped (with a probability of 0.5 % also). 53 * - In callback, the timer is can be reset (randomly, with a 54 * probability of 0.5 %) 100 microseconds later on the same core or 55 * on another core (same probability), or stopped (same 56 * probability). 57 * 58 * # Stress test 2. 59 * 60 * The objective of this test is similar to the first in that it attempts 61 * to find if there are any race conditions in the timer library. However, 62 * it is less complex in terms of operations performed and duration, as it 63 * is designed to have a predictable outcome that can be tested. 64 * 65 * - A set of timers is initialized for use by the test 66 * - All cores then simultaneously are set to schedule all the timers at 67 * the same time, so conflicts should occur. 68 * - Then there is a delay while we wait for the timers to expire 69 * - Then the master lcore calls timer_manage() and we check that all 70 * timers have had their callbacks called exactly once - no more no less. 71 * - Then we repeat the process, except after setting up the timers, we have 72 * all cores randomly reschedule them. 73 * - Again we check that the expected number of callbacks has occurred when 74 * we call timer-manage. 75 * 76 * #. Basic test. 77 * 78 * This test performs basic functional checks of the timers. The test 79 * uses four different timers that are loaded and stopped under 80 * specific conditions in specific contexts. 81 * 82 * - Four timers are used for this test. 83 * - On each core, the rte_timer_manage() function is called from main loop 84 * every 3 microseconds. 85 * 86 * The autotest python script checks that the behavior is correct: 87 * 88 * - timer0 89 * 90 * - At initialization, timer0 is loaded by the master core, on master core 91 * in "single" mode (time = 1 second). 92 * - In the first 19 callbacks, timer0 is reloaded on the same core, 93 * then, it is explicitly stopped at the 20th call. 94 * - At t=25s, timer0 is reloaded once by timer2. 95 * 96 * - timer1 97 * 98 * - At initialization, timer1 is loaded by the master core, on the 99 * master core in "single" mode (time = 2 seconds). 100 * - In the first 9 callbacks, timer1 is reloaded on another 101 * core. After the 10th callback, timer1 is not reloaded anymore. 102 * 103 * - timer2 104 * 105 * - At initialization, timer2 is loaded by the master core, on the 106 * master core in "periodical" mode (time = 1 second). 107 * - In the callback, when t=25s, it stops timer3 and reloads timer0 108 * on the current core. 109 * 110 * - timer3 111 * 112 * - At initialization, timer3 is loaded by the master core, on 113 * another core in "periodical" mode (time = 1 second). 114 * - It is stopped at t=25s by timer2. 115 */ 116 117 #include <stdio.h> 118 #include <stdarg.h> 119 #include <string.h> 120 #include <stdlib.h> 121 #include <stdint.h> 122 #include <inttypes.h> 123 #include <sys/queue.h> 124 #include <math.h> 125 126 #include <rte_common.h> 127 #include <rte_log.h> 128 #include <rte_memory.h> 129 #include <rte_memzone.h> 130 #include <rte_launch.h> 131 #include <rte_cycles.h> 132 #include <rte_eal.h> 133 #include <rte_per_lcore.h> 134 #include <rte_lcore.h> 135 #include <rte_atomic.h> 136 #include <rte_timer.h> 137 #include <rte_random.h> 138 #include <rte_malloc.h> 139 140 141 #define TEST_DURATION_S 20 /* in seconds */ 142 #define NB_TIMER 4 143 144 #define RTE_LOGTYPE_TESTTIMER RTE_LOGTYPE_USER3 145 146 static volatile uint64_t end_time; 147 148 struct mytimerinfo { 149 struct rte_timer tim; 150 unsigned id; 151 unsigned count; 152 }; 153 154 static struct mytimerinfo mytiminfo[NB_TIMER]; 155 156 static void timer_basic_cb(struct rte_timer *tim, void *arg); 157 158 static void 159 mytimer_reset(struct mytimerinfo *timinfo, uint64_t ticks, 160 enum rte_timer_type type, unsigned tim_lcore, 161 rte_timer_cb_t fct) 162 { 163 rte_timer_reset_sync(&timinfo->tim, ticks, type, tim_lcore, 164 fct, timinfo); 165 } 166 167 /* timer callback for stress tests */ 168 static void 169 timer_stress_cb(__attribute__((unused)) struct rte_timer *tim, 170 __attribute__((unused)) void *arg) 171 { 172 long r; 173 unsigned lcore_id = rte_lcore_id(); 174 uint64_t hz = rte_get_timer_hz(); 175 176 if (rte_timer_pending(tim)) 177 return; 178 179 r = rte_rand(); 180 if ((r & 0xff) == 0) { 181 mytimer_reset(&mytiminfo[0], hz, SINGLE, lcore_id, 182 timer_stress_cb); 183 } 184 else if ((r & 0xff) == 1) { 185 mytimer_reset(&mytiminfo[0], hz, SINGLE, 186 rte_get_next_lcore(lcore_id, 0, 1), 187 timer_stress_cb); 188 } 189 else if ((r & 0xff) == 2) { 190 rte_timer_stop(&mytiminfo[0].tim); 191 } 192 } 193 194 static int 195 timer_stress_main_loop(__attribute__((unused)) void *arg) 196 { 197 uint64_t hz = rte_get_timer_hz(); 198 unsigned lcore_id = rte_lcore_id(); 199 uint64_t cur_time; 200 int64_t diff = 0; 201 long r; 202 203 while (diff >= 0) { 204 205 /* call the timer handler on each core */ 206 rte_timer_manage(); 207 208 /* simulate the processing of a packet 209 * (1 us = 2000 cycles at 2 Ghz) */ 210 rte_delay_us(1); 211 212 /* randomly stop or reset timer */ 213 r = rte_rand(); 214 lcore_id = rte_get_next_lcore(lcore_id, 0, 1); 215 if ((r & 0xff) == 0) { 216 /* 100 us */ 217 mytimer_reset(&mytiminfo[0], hz/10000, SINGLE, lcore_id, 218 timer_stress_cb); 219 } 220 else if ((r & 0xff) == 1) { 221 rte_timer_stop_sync(&mytiminfo[0].tim); 222 } 223 cur_time = rte_get_timer_cycles(); 224 diff = end_time - cur_time; 225 } 226 227 lcore_id = rte_lcore_id(); 228 RTE_LOG(INFO, TESTTIMER, "core %u finished\n", lcore_id); 229 230 return 0; 231 } 232 233 static volatile int cb_count = 0; 234 235 /* callback for second stress test. will only be called 236 * on master lcore */ 237 static void 238 timer_stress2_cb(struct rte_timer *tim __rte_unused, void *arg __rte_unused) 239 { 240 cb_count++; 241 } 242 243 #define NB_STRESS2_TIMERS 8192 244 245 static int 246 timer_stress2_main_loop(__attribute__((unused)) void *arg) 247 { 248 static struct rte_timer *timers; 249 int i, ret; 250 static volatile int ready = 0; 251 uint64_t delay = rte_get_timer_hz() / 4; 252 unsigned lcore_id = rte_lcore_id(); 253 int32_t my_collisions = 0; 254 static rte_atomic32_t collisions = RTE_ATOMIC32_INIT(0); 255 256 if (lcore_id == rte_get_master_lcore()) { 257 cb_count = 0; 258 timers = rte_malloc(NULL, sizeof(*timers) * NB_STRESS2_TIMERS, 0); 259 if (timers == NULL) { 260 printf("Test Failed\n"); 261 printf("- Cannot allocate memory for timers\n" ); 262 return -1; 263 } 264 for (i = 0; i < NB_STRESS2_TIMERS; i++) 265 rte_timer_init(&timers[i]); 266 ready = 1; 267 } else { 268 while (!ready) 269 rte_pause(); 270 } 271 272 /* have all cores schedule all timers on master lcore */ 273 for (i = 0; i < NB_STRESS2_TIMERS; i++) { 274 ret = rte_timer_reset(&timers[i], delay, SINGLE, rte_get_master_lcore(), 275 timer_stress2_cb, NULL); 276 /* there will be collisions when multiple cores simultaneously 277 * configure the same timers */ 278 if (ret != 0) 279 my_collisions++; 280 } 281 if (my_collisions != 0) 282 rte_atomic32_add(&collisions, my_collisions); 283 284 ready = 0; 285 rte_delay_ms(500); 286 287 /* now check that we get the right number of callbacks */ 288 if (lcore_id == rte_get_master_lcore()) { 289 my_collisions = rte_atomic32_read(&collisions); 290 if (my_collisions != 0) 291 printf("- %d timer reset collisions (OK)\n", my_collisions); 292 rte_timer_manage(); 293 if (cb_count != NB_STRESS2_TIMERS) { 294 printf("Test Failed\n"); 295 printf("- Stress test 2, part 1 failed\n"); 296 printf("- Expected %d callbacks, got %d\n", NB_STRESS2_TIMERS, 297 cb_count); 298 return -1; 299 } 300 ready = 1; 301 } else { 302 while (!ready) 303 rte_pause(); 304 } 305 306 /* now test again, just stop and restart timers at random after init*/ 307 for (i = 0; i < NB_STRESS2_TIMERS; i++) 308 rte_timer_reset(&timers[i], delay, SINGLE, rte_get_master_lcore(), 309 timer_stress2_cb, NULL); 310 cb_count = 0; 311 312 /* pick random timer to reset, stopping them first half the time */ 313 for (i = 0; i < 100000; i++) { 314 int r = rand() % NB_STRESS2_TIMERS; 315 if (i % 2) 316 rte_timer_stop(&timers[r]); 317 rte_timer_reset(&timers[r], delay, SINGLE, rte_get_master_lcore(), 318 timer_stress2_cb, NULL); 319 } 320 321 rte_delay_ms(500); 322 323 /* now check that we get the right number of callbacks */ 324 if (lcore_id == rte_get_master_lcore()) { 325 rte_timer_manage(); 326 327 /* clean up statics, in case we run again */ 328 rte_free(timers); 329 timers = NULL; 330 ready = 0; 331 rte_atomic32_set(&collisions, 0); 332 333 if (cb_count != NB_STRESS2_TIMERS) { 334 printf("Test Failed\n"); 335 printf("- Stress test 2, part 2 failed\n"); 336 printf("- Expected %d callbacks, got %d\n", NB_STRESS2_TIMERS, 337 cb_count); 338 return -1; 339 } 340 printf("Test OK\n"); 341 } 342 343 return 0; 344 } 345 346 /* timer callback for basic tests */ 347 static void 348 timer_basic_cb(struct rte_timer *tim, void *arg) 349 { 350 struct mytimerinfo *timinfo = arg; 351 uint64_t hz = rte_get_timer_hz(); 352 unsigned lcore_id = rte_lcore_id(); 353 uint64_t cur_time = rte_get_timer_cycles(); 354 355 if (rte_timer_pending(tim)) 356 return; 357 358 timinfo->count ++; 359 360 RTE_LOG(INFO, TESTTIMER, 361 "%"PRIu64": callback id=%u count=%u on core %u\n", 362 cur_time, timinfo->id, timinfo->count, lcore_id); 363 364 /* reload timer 0 on same core */ 365 if (timinfo->id == 0 && timinfo->count < 20) { 366 mytimer_reset(timinfo, hz, SINGLE, lcore_id, timer_basic_cb); 367 return; 368 } 369 370 /* reload timer 1 on next core */ 371 if (timinfo->id == 1 && timinfo->count < 10) { 372 mytimer_reset(timinfo, hz*2, SINGLE, 373 rte_get_next_lcore(lcore_id, 0, 1), 374 timer_basic_cb); 375 return; 376 } 377 378 /* Explicitelly stop timer 0. Once stop() called, we can even 379 * erase the content of the structure: it is not referenced 380 * anymore by any code (in case of dynamic structure, it can 381 * be freed) */ 382 if (timinfo->id == 0 && timinfo->count == 20) { 383 384 /* stop_sync() is not needed, because we know that the 385 * status of timer is only modified by this core */ 386 rte_timer_stop(tim); 387 memset(tim, 0xAA, sizeof(struct rte_timer)); 388 return; 389 } 390 391 /* stop timer3, and restart a new timer0 (it was removed 5 392 * seconds ago) for a single shot */ 393 if (timinfo->id == 2 && timinfo->count == 25) { 394 rte_timer_stop_sync(&mytiminfo[3].tim); 395 396 /* need to reinit because structure was erased with 0xAA */ 397 rte_timer_init(&mytiminfo[0].tim); 398 mytimer_reset(&mytiminfo[0], hz, SINGLE, lcore_id, 399 timer_basic_cb); 400 } 401 } 402 403 static int 404 timer_basic_main_loop(__attribute__((unused)) void *arg) 405 { 406 uint64_t hz = rte_get_timer_hz(); 407 unsigned lcore_id = rte_lcore_id(); 408 uint64_t cur_time; 409 int64_t diff = 0; 410 411 /* launch all timers on core 0 */ 412 if (lcore_id == rte_get_master_lcore()) { 413 mytimer_reset(&mytiminfo[0], hz, SINGLE, lcore_id, 414 timer_basic_cb); 415 mytimer_reset(&mytiminfo[1], hz*2, SINGLE, lcore_id, 416 timer_basic_cb); 417 mytimer_reset(&mytiminfo[2], hz, PERIODICAL, lcore_id, 418 timer_basic_cb); 419 mytimer_reset(&mytiminfo[3], hz, PERIODICAL, 420 rte_get_next_lcore(lcore_id, 0, 1), 421 timer_basic_cb); 422 } 423 424 while (diff >= 0) { 425 426 /* call the timer handler on each core */ 427 rte_timer_manage(); 428 429 /* simulate the processing of a packet 430 * (3 us = 6000 cycles at 2 Ghz) */ 431 rte_delay_us(3); 432 433 cur_time = rte_get_timer_cycles(); 434 diff = end_time - cur_time; 435 } 436 RTE_LOG(INFO, TESTTIMER, "core %u finished\n", lcore_id); 437 438 return 0; 439 } 440 441 static int 442 timer_sanity_check(void) 443 { 444 #ifdef RTE_LIBEAL_USE_HPET 445 if (eal_timer_source != EAL_TIMER_HPET) { 446 printf("Not using HPET, can't sanity check timer sources\n"); 447 return 0; 448 } 449 450 const uint64_t t_hz = rte_get_tsc_hz(); 451 const uint64_t h_hz = rte_get_hpet_hz(); 452 printf("Hertz values: TSC = %"PRIu64", HPET = %"PRIu64"\n", t_hz, h_hz); 453 454 const uint64_t tsc_start = rte_get_tsc_cycles(); 455 const uint64_t hpet_start = rte_get_hpet_cycles(); 456 rte_delay_ms(100); /* delay 1/10 second */ 457 const uint64_t tsc_end = rte_get_tsc_cycles(); 458 const uint64_t hpet_end = rte_get_hpet_cycles(); 459 printf("Measured cycles: TSC = %"PRIu64", HPET = %"PRIu64"\n", 460 tsc_end-tsc_start, hpet_end-hpet_start); 461 462 const double tsc_time = (double)(tsc_end - tsc_start)/t_hz; 463 const double hpet_time = (double)(hpet_end - hpet_start)/h_hz; 464 /* get the percentage that the times differ by */ 465 const double time_diff = fabs(tsc_time - hpet_time)*100/tsc_time; 466 printf("Measured time: TSC = %.4f, HPET = %.4f\n", tsc_time, hpet_time); 467 468 printf("Elapsed time measured by TSC and HPET differ by %f%%\n", 469 time_diff); 470 if (time_diff > 0.1) { 471 printf("Error times differ by >0.1%%"); 472 return -1; 473 } 474 #endif 475 return 0; 476 } 477 478 static int 479 test_timer(void) 480 { 481 unsigned i; 482 uint64_t cur_time; 483 uint64_t hz; 484 485 /* sanity check our timer sources and timer config values */ 486 if (timer_sanity_check() < 0) { 487 printf("Timer sanity checks failed\n"); 488 return -1; 489 } 490 491 if (rte_lcore_count() < 2) { 492 printf("not enough lcores for this test\n"); 493 return -1; 494 } 495 496 /* init timer */ 497 for (i=0; i<NB_TIMER; i++) { 498 memset(&mytiminfo[i], 0, sizeof(struct mytimerinfo)); 499 mytiminfo[i].id = i; 500 rte_timer_init(&mytiminfo[i].tim); 501 } 502 503 /* calculate the "end of test" time */ 504 cur_time = rte_get_timer_cycles(); 505 hz = rte_get_timer_hz(); 506 end_time = cur_time + (hz * TEST_DURATION_S); 507 508 /* start other cores */ 509 printf("Start timer stress tests (%d seconds)\n", TEST_DURATION_S); 510 rte_eal_mp_remote_launch(timer_stress_main_loop, NULL, CALL_MASTER); 511 rte_eal_mp_wait_lcore(); 512 513 /* stop timer 0 used for stress test */ 514 rte_timer_stop_sync(&mytiminfo[0].tim); 515 516 /* run a second, slightly different set of stress tests */ 517 printf("Start timer stress tests 2\n"); 518 rte_eal_mp_remote_launch(timer_stress2_main_loop, NULL, CALL_MASTER); 519 rte_eal_mp_wait_lcore(); 520 521 /* calculate the "end of test" time */ 522 cur_time = rte_get_timer_cycles(); 523 hz = rte_get_timer_hz(); 524 end_time = cur_time + (hz * TEST_DURATION_S); 525 526 /* start other cores */ 527 printf("Start timer basic tests (%d seconds)\n", TEST_DURATION_S); 528 rte_eal_mp_remote_launch(timer_basic_main_loop, NULL, CALL_MASTER); 529 rte_eal_mp_wait_lcore(); 530 531 /* stop all timers */ 532 for (i=0; i<NB_TIMER; i++) { 533 rte_timer_stop_sync(&mytiminfo[i].tim); 534 } 535 536 rte_timer_dump_stats(stdout); 537 538 return 0; 539 } 540 541 static struct test_command timer_cmd = { 542 .command = "timer_autotest", 543 .callback = test_timer, 544 }; 545 REGISTER_TEST_COMMAND(timer_cmd); 546