1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2021 HiSilicon Limited 3 * Copyright(c) 2021 Intel Corporation 4 */ 5 6 #include <inttypes.h> 7 8 #include <rte_dmadev.h> 9 #include <rte_mbuf.h> 10 #include <rte_pause.h> 11 #include <rte_cycles.h> 12 #include <rte_random.h> 13 #include <rte_bus_vdev.h> 14 #include <rte_dmadev_pmd.h> 15 16 #include "test.h" 17 #include "test_dmadev_api.h" 18 19 #define ERR_RETURN(...) do { print_err(__func__, __LINE__, __VA_ARGS__); return -1; } while (0) 20 21 #define COPY_LEN 1024 22 23 static struct rte_mempool *pool; 24 static uint16_t id_count; 25 26 static void 27 __rte_format_printf(3, 4) 28 print_err(const char *func, int lineno, const char *format, ...) 29 { 30 va_list ap; 31 32 fprintf(stderr, "In %s:%d - ", func, lineno); 33 va_start(ap, format); 34 vfprintf(stderr, format, ap); 35 va_end(ap); 36 } 37 38 static int 39 runtest(const char *printable, int (*test_fn)(int16_t dev_id, uint16_t vchan), int iterations, 40 int16_t dev_id, uint16_t vchan, bool check_err_stats) 41 { 42 struct rte_dma_stats stats; 43 int i; 44 45 rte_dma_stats_reset(dev_id, vchan); 46 printf("DMA Dev %d: Running %s Tests %s\n", dev_id, printable, 47 check_err_stats ? " " : "(errors expected)"); 48 for (i = 0; i < iterations; i++) { 49 if (test_fn(dev_id, vchan) < 0) 50 return -1; 51 52 rte_dma_stats_get(dev_id, 0, &stats); 53 printf("Ops submitted: %"PRIu64"\t", stats.submitted); 54 printf("Ops completed: %"PRIu64"\t", stats.completed); 55 printf("Errors: %"PRIu64"\r", stats.errors); 56 57 if (stats.completed != stats.submitted) 58 ERR_RETURN("\nError, not all submitted jobs are reported as completed\n"); 59 if (check_err_stats && stats.errors != 0) 60 ERR_RETURN("\nErrors reported during op processing, aborting tests\n"); 61 } 62 printf("\n"); 63 return 0; 64 } 65 66 static void 67 await_hw(int16_t dev_id, uint16_t vchan) 68 { 69 enum rte_dma_vchan_status st; 70 71 if (rte_dma_vchan_status(dev_id, vchan, &st) < 0) { 72 /* for drivers that don't support this op, just sleep for 1 millisecond */ 73 rte_delay_us_sleep(1000); 74 return; 75 } 76 77 /* for those that do, *max* end time is one second from now, but all should be faster */ 78 const uint64_t end_cycles = rte_get_timer_cycles() + rte_get_timer_hz(); 79 while (st == RTE_DMA_VCHAN_ACTIVE && rte_get_timer_cycles() < end_cycles) { 80 rte_pause(); 81 rte_dma_vchan_status(dev_id, vchan, &st); 82 } 83 } 84 85 /* run a series of copy tests just using some different options for enqueues and completions */ 86 static int 87 do_multi_copies(int16_t dev_id, uint16_t vchan, 88 int split_batches, /* submit 2 x 16 or 1 x 32 burst */ 89 int split_completions, /* gather 2 x 16 or 1 x 32 completions */ 90 int use_completed_status) /* use completed or completed_status function */ 91 { 92 struct rte_mbuf *srcs[32], *dsts[32]; 93 enum rte_dma_status_code sc[32]; 94 unsigned int i, j; 95 bool dma_err = false; 96 97 /* Enqueue burst of copies and hit doorbell */ 98 for (i = 0; i < RTE_DIM(srcs); i++) { 99 uint64_t *src_data; 100 101 if (split_batches && i == RTE_DIM(srcs) / 2) 102 rte_dma_submit(dev_id, vchan); 103 104 srcs[i] = rte_pktmbuf_alloc(pool); 105 dsts[i] = rte_pktmbuf_alloc(pool); 106 if (srcs[i] == NULL || dsts[i] == NULL) 107 ERR_RETURN("Error allocating buffers\n"); 108 109 src_data = rte_pktmbuf_mtod(srcs[i], uint64_t *); 110 for (j = 0; j < COPY_LEN/sizeof(uint64_t); j++) 111 src_data[j] = rte_rand(); 112 113 if (rte_dma_copy(dev_id, vchan, rte_mbuf_data_iova(srcs[i]), 114 rte_mbuf_data_iova(dsts[i]), COPY_LEN, 0) != id_count++) 115 ERR_RETURN("Error with rte_dma_copy for buffer %u\n", i); 116 } 117 rte_dma_submit(dev_id, vchan); 118 119 await_hw(dev_id, vchan); 120 121 if (split_completions) { 122 /* gather completions in two halves */ 123 uint16_t half_len = RTE_DIM(srcs) / 2; 124 int ret = rte_dma_completed(dev_id, vchan, half_len, NULL, &dma_err); 125 if (ret != half_len || dma_err) 126 ERR_RETURN("Error with rte_dma_completed - first half. ret = %d, expected ret = %u, dma_err = %d\n", 127 ret, half_len, dma_err); 128 129 ret = rte_dma_completed(dev_id, vchan, half_len, NULL, &dma_err); 130 if (ret != half_len || dma_err) 131 ERR_RETURN("Error with rte_dma_completed - second half. ret = %d, expected ret = %u, dma_err = %d\n", 132 ret, half_len, dma_err); 133 } else { 134 /* gather all completions in one go, using either 135 * completed or completed_status fns 136 */ 137 if (!use_completed_status) { 138 int n = rte_dma_completed(dev_id, vchan, RTE_DIM(srcs), NULL, &dma_err); 139 if (n != RTE_DIM(srcs) || dma_err) 140 ERR_RETURN("Error with rte_dma_completed, %u [expected: %zu], dma_err = %d\n", 141 n, RTE_DIM(srcs), dma_err); 142 } else { 143 int n = rte_dma_completed_status(dev_id, vchan, RTE_DIM(srcs), NULL, sc); 144 if (n != RTE_DIM(srcs)) 145 ERR_RETURN("Error with rte_dma_completed_status, %u [expected: %zu]\n", 146 n, RTE_DIM(srcs)); 147 148 for (j = 0; j < (uint16_t)n; j++) 149 if (sc[j] != RTE_DMA_STATUS_SUCCESSFUL) 150 ERR_RETURN("Error with rte_dma_completed_status, job %u reports failure [code %u]\n", 151 j, sc[j]); 152 } 153 } 154 155 /* check for empty */ 156 int ret = use_completed_status ? 157 rte_dma_completed_status(dev_id, vchan, RTE_DIM(srcs), NULL, sc) : 158 rte_dma_completed(dev_id, vchan, RTE_DIM(srcs), NULL, &dma_err); 159 if (ret != 0) 160 ERR_RETURN("Error with completion check - ops unexpectedly returned\n"); 161 162 for (i = 0; i < RTE_DIM(srcs); i++) { 163 char *src_data, *dst_data; 164 165 src_data = rte_pktmbuf_mtod(srcs[i], char *); 166 dst_data = rte_pktmbuf_mtod(dsts[i], char *); 167 for (j = 0; j < COPY_LEN; j++) 168 if (src_data[j] != dst_data[j]) 169 ERR_RETURN("Error with copy of packet %u, byte %u\n", i, j); 170 171 rte_pktmbuf_free(srcs[i]); 172 rte_pktmbuf_free(dsts[i]); 173 } 174 return 0; 175 } 176 177 static int 178 test_enqueue_copies(int16_t dev_id, uint16_t vchan) 179 { 180 enum rte_dma_status_code status; 181 unsigned int i; 182 uint16_t id; 183 184 /* test doing a single copy */ 185 do { 186 struct rte_mbuf *src, *dst; 187 char *src_data, *dst_data; 188 189 src = rte_pktmbuf_alloc(pool); 190 dst = rte_pktmbuf_alloc(pool); 191 src_data = rte_pktmbuf_mtod(src, char *); 192 dst_data = rte_pktmbuf_mtod(dst, char *); 193 194 for (i = 0; i < COPY_LEN; i++) 195 src_data[i] = rte_rand() & 0xFF; 196 197 id = rte_dma_copy(dev_id, vchan, rte_pktmbuf_iova(src), rte_pktmbuf_iova(dst), 198 COPY_LEN, RTE_DMA_OP_FLAG_SUBMIT); 199 if (id != id_count) 200 ERR_RETURN("Error with rte_dma_copy, got %u, expected %u\n", 201 id, id_count); 202 203 /* give time for copy to finish, then check it was done */ 204 await_hw(dev_id, vchan); 205 206 for (i = 0; i < COPY_LEN; i++) 207 if (dst_data[i] != src_data[i]) 208 ERR_RETURN("Data mismatch at char %u [Got %02x not %02x]\n", i, 209 dst_data[i], src_data[i]); 210 211 /* now check completion works */ 212 id = ~id; 213 if (rte_dma_completed(dev_id, vchan, 1, &id, NULL) != 1) 214 ERR_RETURN("Error with rte_dma_completed\n"); 215 216 if (id != id_count) 217 ERR_RETURN("Error:incorrect job id received, %u [expected %u]\n", 218 id, id_count); 219 220 /* check for completed and id when no job done */ 221 id = ~id; 222 if (rte_dma_completed(dev_id, vchan, 1, &id, NULL) != 0) 223 ERR_RETURN("Error with rte_dma_completed when no job done\n"); 224 if (id != id_count) 225 ERR_RETURN("Error:incorrect job id received when no job done, %u [expected %u]\n", 226 id, id_count); 227 228 /* check for completed_status and id when no job done */ 229 id = ~id; 230 if (rte_dma_completed_status(dev_id, vchan, 1, &id, &status) != 0) 231 ERR_RETURN("Error with rte_dma_completed_status when no job done\n"); 232 if (id != id_count) 233 ERR_RETURN("Error:incorrect job id received when no job done, %u [expected %u]\n", 234 id, id_count); 235 236 rte_pktmbuf_free(src); 237 rte_pktmbuf_free(dst); 238 239 /* now check completion returns nothing more */ 240 if (rte_dma_completed(dev_id, 0, 1, NULL, NULL) != 0) 241 ERR_RETURN("Error with rte_dma_completed in empty check\n"); 242 243 id_count++; 244 245 } while (0); 246 247 /* test doing a multiple single copies */ 248 do { 249 const uint16_t max_ops = 4; 250 struct rte_mbuf *src, *dst; 251 char *src_data, *dst_data; 252 uint16_t count; 253 254 src = rte_pktmbuf_alloc(pool); 255 dst = rte_pktmbuf_alloc(pool); 256 src_data = rte_pktmbuf_mtod(src, char *); 257 dst_data = rte_pktmbuf_mtod(dst, char *); 258 259 for (i = 0; i < COPY_LEN; i++) 260 src_data[i] = rte_rand() & 0xFF; 261 262 /* perform the same copy <max_ops> times */ 263 for (i = 0; i < max_ops; i++) 264 if (rte_dma_copy(dev_id, vchan, 265 rte_pktmbuf_iova(src), 266 rte_pktmbuf_iova(dst), 267 COPY_LEN, RTE_DMA_OP_FLAG_SUBMIT) != id_count++) 268 ERR_RETURN("Error with rte_dma_copy\n"); 269 270 await_hw(dev_id, vchan); 271 272 count = rte_dma_completed(dev_id, vchan, max_ops * 2, &id, NULL); 273 if (count != max_ops) 274 ERR_RETURN("Error with rte_dma_completed, got %u not %u\n", 275 count, max_ops); 276 277 if (id != id_count - 1) 278 ERR_RETURN("Error, incorrect job id returned: got %u not %u\n", 279 id, id_count - 1); 280 281 for (i = 0; i < COPY_LEN; i++) 282 if (dst_data[i] != src_data[i]) 283 ERR_RETURN("Data mismatch at char %u\n", i); 284 285 rte_pktmbuf_free(src); 286 rte_pktmbuf_free(dst); 287 } while (0); 288 289 /* test doing multiple copies */ 290 return do_multi_copies(dev_id, vchan, 0, 0, 0) /* enqueue and complete 1 batch at a time */ 291 /* enqueue 2 batches and then complete both */ 292 || do_multi_copies(dev_id, vchan, 1, 0, 0) 293 /* enqueue 1 batch, then complete in two halves */ 294 || do_multi_copies(dev_id, vchan, 0, 1, 0) 295 /* test using completed_status in place of regular completed API */ 296 || do_multi_copies(dev_id, vchan, 0, 0, 1); 297 } 298 299 /* Failure handling test cases - global macros and variables for those tests*/ 300 #define COMP_BURST_SZ 16 301 #define OPT_FENCE(idx) ((fence && idx == 8) ? RTE_DMA_OP_FLAG_FENCE : 0) 302 303 static int 304 test_failure_in_full_burst(int16_t dev_id, uint16_t vchan, bool fence, 305 struct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx) 306 { 307 /* Test single full batch statuses with failures */ 308 enum rte_dma_status_code status[COMP_BURST_SZ]; 309 struct rte_dma_stats baseline, stats; 310 uint16_t invalid_addr_id = 0; 311 uint16_t idx; 312 uint16_t count, status_count; 313 unsigned int i; 314 bool error = false; 315 int err_count = 0; 316 317 rte_dma_stats_get(dev_id, vchan, &baseline); /* get a baseline set of stats */ 318 for (i = 0; i < COMP_BURST_SZ; i++) { 319 int id = rte_dma_copy(dev_id, vchan, 320 (i == fail_idx ? 0 : rte_mbuf_data_iova(srcs[i])), 321 rte_mbuf_data_iova(dsts[i]), COPY_LEN, OPT_FENCE(i)); 322 if (id < 0) 323 ERR_RETURN("Error with rte_dma_copy for buffer %u\n", i); 324 if (i == fail_idx) 325 invalid_addr_id = id; 326 } 327 rte_dma_submit(dev_id, vchan); 328 rte_dma_stats_get(dev_id, vchan, &stats); 329 if (stats.submitted != baseline.submitted + COMP_BURST_SZ) 330 ERR_RETURN("Submitted stats value not as expected, %"PRIu64" not %"PRIu64"\n", 331 stats.submitted, baseline.submitted + COMP_BURST_SZ); 332 333 await_hw(dev_id, vchan); 334 335 count = rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error); 336 if (count != fail_idx) 337 ERR_RETURN("Error with rte_dma_completed for failure test. Got returned %u not %u.\n", 338 count, fail_idx); 339 if (!error) 340 ERR_RETURN("Error, missing expected failed copy, %u. has_error is not set\n", 341 fail_idx); 342 if (idx != invalid_addr_id - 1) 343 ERR_RETURN("Error, missing expected failed copy, %u. Got last idx %u, not %u\n", 344 fail_idx, idx, invalid_addr_id - 1); 345 346 /* all checks ok, now verify calling completed() again always returns 0 */ 347 for (i = 0; i < 10; i++) 348 if (rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error) != 0 349 || error == false || idx != (invalid_addr_id - 1)) 350 ERR_RETURN("Error with follow-up completed calls for fail idx %u\n", 351 fail_idx); 352 353 status_count = rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ, 354 &idx, status); 355 /* some HW may stop on error and be restarted after getting error status for single value 356 * To handle this case, if we get just one error back, wait for more completions and get 357 * status for rest of the burst 358 */ 359 if (status_count == 1) { 360 await_hw(dev_id, vchan); 361 status_count += rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ - 1, 362 &idx, &status[1]); 363 } 364 /* check that at this point we have all status values */ 365 if (status_count != COMP_BURST_SZ - count) 366 ERR_RETURN("Error with completed_status calls for fail idx %u. Got %u not %u\n", 367 fail_idx, status_count, COMP_BURST_SZ - count); 368 /* now verify just one failure followed by multiple successful or skipped entries */ 369 if (status[0] == RTE_DMA_STATUS_SUCCESSFUL) 370 ERR_RETURN("Error with status returned for fail idx %u. First status was not failure\n", 371 fail_idx); 372 for (i = 1; i < status_count; i++) 373 /* after a failure in a burst, depending on ordering/fencing, 374 * operations may be successful or skipped because of previous error. 375 */ 376 if (status[i] != RTE_DMA_STATUS_SUCCESSFUL 377 && status[i] != RTE_DMA_STATUS_NOT_ATTEMPTED) 378 ERR_RETURN("Error with status calls for fail idx %u. Status for job %u (of %u) is not successful\n", 379 fail_idx, count + i, COMP_BURST_SZ); 380 381 /* check the completed + errors stats are as expected */ 382 rte_dma_stats_get(dev_id, vchan, &stats); 383 if (stats.completed != baseline.completed + COMP_BURST_SZ) 384 ERR_RETURN("Completed stats value not as expected, %"PRIu64" not %"PRIu64"\n", 385 stats.completed, baseline.completed + COMP_BURST_SZ); 386 for (i = 0; i < status_count; i++) 387 err_count += (status[i] != RTE_DMA_STATUS_SUCCESSFUL); 388 if (stats.errors != baseline.errors + err_count) 389 ERR_RETURN("'Errors' stats value not as expected, %"PRIu64" not %"PRIu64"\n", 390 stats.errors, baseline.errors + err_count); 391 392 return 0; 393 } 394 395 static int 396 test_individual_status_query_with_failure(int16_t dev_id, uint16_t vchan, bool fence, 397 struct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx) 398 { 399 /* Test gathering batch statuses one at a time */ 400 enum rte_dma_status_code status[COMP_BURST_SZ]; 401 uint16_t invalid_addr_id = 0; 402 uint16_t idx; 403 uint16_t count = 0, status_count = 0; 404 unsigned int j; 405 bool error = false; 406 407 for (j = 0; j < COMP_BURST_SZ; j++) { 408 int id = rte_dma_copy(dev_id, vchan, 409 (j == fail_idx ? 0 : rte_mbuf_data_iova(srcs[j])), 410 rte_mbuf_data_iova(dsts[j]), COPY_LEN, OPT_FENCE(j)); 411 if (id < 0) 412 ERR_RETURN("Error with rte_dma_copy for buffer %u\n", j); 413 if (j == fail_idx) 414 invalid_addr_id = id; 415 } 416 rte_dma_submit(dev_id, vchan); 417 await_hw(dev_id, vchan); 418 419 /* use regular "completed" until we hit error */ 420 while (!error) { 421 uint16_t n = rte_dma_completed(dev_id, vchan, 1, &idx, &error); 422 count += n; 423 if (n > 1 || count >= COMP_BURST_SZ) 424 ERR_RETURN("Error - too many completions got\n"); 425 if (n == 0 && !error) 426 ERR_RETURN("Error, unexpectedly got zero completions after %u completed\n", 427 count); 428 } 429 if (idx != invalid_addr_id - 1) 430 ERR_RETURN("Error, last successful index not as expected, got %u, expected %u\n", 431 idx, invalid_addr_id - 1); 432 433 /* use completed_status until we hit end of burst */ 434 while (count + status_count < COMP_BURST_SZ) { 435 uint16_t n = rte_dma_completed_status(dev_id, vchan, 1, &idx, 436 &status[status_count]); 437 await_hw(dev_id, vchan); /* allow delay to ensure jobs are completed */ 438 status_count += n; 439 if (n != 1) 440 ERR_RETURN("Error: unexpected number of completions received, %u, not 1\n", 441 n); 442 } 443 444 /* check for single failure */ 445 if (status[0] == RTE_DMA_STATUS_SUCCESSFUL) 446 ERR_RETURN("Error, unexpected successful DMA transaction\n"); 447 for (j = 1; j < status_count; j++) 448 if (status[j] != RTE_DMA_STATUS_SUCCESSFUL 449 && status[j] != RTE_DMA_STATUS_NOT_ATTEMPTED) 450 ERR_RETURN("Error, unexpected DMA error reported\n"); 451 452 return 0; 453 } 454 455 static int 456 test_single_item_status_query_with_failure(int16_t dev_id, uint16_t vchan, 457 struct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx) 458 { 459 /* When error occurs just collect a single error using "completed_status()" 460 * before going to back to completed() calls 461 */ 462 enum rte_dma_status_code status; 463 uint16_t invalid_addr_id = 0; 464 uint16_t idx; 465 uint16_t count, status_count, count2; 466 unsigned int j; 467 bool error = false; 468 469 for (j = 0; j < COMP_BURST_SZ; j++) { 470 int id = rte_dma_copy(dev_id, vchan, 471 (j == fail_idx ? 0 : rte_mbuf_data_iova(srcs[j])), 472 rte_mbuf_data_iova(dsts[j]), COPY_LEN, 0); 473 if (id < 0) 474 ERR_RETURN("Error with rte_dma_copy for buffer %u\n", j); 475 if (j == fail_idx) 476 invalid_addr_id = id; 477 } 478 rte_dma_submit(dev_id, vchan); 479 await_hw(dev_id, vchan); 480 481 /* get up to the error point */ 482 count = rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error); 483 if (count != fail_idx) 484 ERR_RETURN("Error with rte_dma_completed for failure test. Got returned %u not %u.\n", 485 count, fail_idx); 486 if (!error) 487 ERR_RETURN("Error, missing expected failed copy, %u. has_error is not set\n", 488 fail_idx); 489 if (idx != invalid_addr_id - 1) 490 ERR_RETURN("Error, missing expected failed copy, %u. Got last idx %u, not %u\n", 491 fail_idx, idx, invalid_addr_id - 1); 492 493 /* get the error code */ 494 status_count = rte_dma_completed_status(dev_id, vchan, 1, &idx, &status); 495 if (status_count != 1) 496 ERR_RETURN("Error with completed_status calls for fail idx %u. Got %u not %u\n", 497 fail_idx, status_count, COMP_BURST_SZ - count); 498 if (status == RTE_DMA_STATUS_SUCCESSFUL) 499 ERR_RETURN("Error with status returned for fail idx %u. First status was not failure\n", 500 fail_idx); 501 502 /* delay in case time needed after err handled to complete other jobs */ 503 await_hw(dev_id, vchan); 504 505 /* get the rest of the completions without status */ 506 count2 = rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error); 507 if (error == true) 508 ERR_RETURN("Error, got further errors post completed_status() call, for failure case %u.\n", 509 fail_idx); 510 if (count + status_count + count2 != COMP_BURST_SZ) 511 ERR_RETURN("Error, incorrect number of completions received, got %u not %u\n", 512 count + status_count + count2, COMP_BURST_SZ); 513 514 return 0; 515 } 516 517 static int 518 test_multi_failure(int16_t dev_id, uint16_t vchan, struct rte_mbuf **srcs, struct rte_mbuf **dsts, 519 const unsigned int *fail, size_t num_fail) 520 { 521 /* test having multiple errors in one go */ 522 enum rte_dma_status_code status[COMP_BURST_SZ]; 523 unsigned int i, j; 524 uint16_t count, err_count = 0; 525 bool error = false; 526 527 /* enqueue and gather completions in one go */ 528 for (j = 0; j < COMP_BURST_SZ; j++) { 529 uintptr_t src = rte_mbuf_data_iova(srcs[j]); 530 /* set up for failure if the current index is anywhere is the fails array */ 531 for (i = 0; i < num_fail; i++) 532 if (j == fail[i]) 533 src = 0; 534 535 int id = rte_dma_copy(dev_id, vchan, src, rte_mbuf_data_iova(dsts[j]), 536 COPY_LEN, 0); 537 if (id < 0) 538 ERR_RETURN("Error with rte_dma_copy for buffer %u\n", j); 539 } 540 rte_dma_submit(dev_id, vchan); 541 await_hw(dev_id, vchan); 542 543 count = rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ, NULL, status); 544 while (count < COMP_BURST_SZ) { 545 await_hw(dev_id, vchan); 546 547 uint16_t ret = rte_dma_completed_status(dev_id, vchan, COMP_BURST_SZ - count, 548 NULL, &status[count]); 549 if (ret == 0) 550 ERR_RETURN("Error getting all completions for jobs. Got %u of %u\n", 551 count, COMP_BURST_SZ); 552 count += ret; 553 } 554 for (i = 0; i < count; i++) 555 if (status[i] != RTE_DMA_STATUS_SUCCESSFUL) 556 err_count++; 557 558 if (err_count != num_fail) 559 ERR_RETURN("Error: Invalid number of failed completions returned, %u; expected %zu\n", 560 err_count, num_fail); 561 562 /* enqueue and gather completions in bursts, but getting errors one at a time */ 563 for (j = 0; j < COMP_BURST_SZ; j++) { 564 uintptr_t src = rte_mbuf_data_iova(srcs[j]); 565 /* set up for failure if the current index is anywhere is the fails array */ 566 for (i = 0; i < num_fail; i++) 567 if (j == fail[i]) 568 src = 0; 569 570 int id = rte_dma_copy(dev_id, vchan, src, rte_mbuf_data_iova(dsts[j]), 571 COPY_LEN, 0); 572 if (id < 0) 573 ERR_RETURN("Error with rte_dma_copy for buffer %u\n", j); 574 } 575 rte_dma_submit(dev_id, vchan); 576 await_hw(dev_id, vchan); 577 578 count = 0; 579 err_count = 0; 580 while (count + err_count < COMP_BURST_SZ) { 581 count += rte_dma_completed(dev_id, vchan, COMP_BURST_SZ, NULL, &error); 582 if (error) { 583 uint16_t ret = rte_dma_completed_status(dev_id, vchan, 1, 584 NULL, status); 585 if (ret != 1) 586 ERR_RETURN("Error getting error-status for completions\n"); 587 err_count += ret; 588 await_hw(dev_id, vchan); 589 } 590 } 591 if (err_count != num_fail) 592 ERR_RETURN("Error: Incorrect number of failed completions received, got %u not %zu\n", 593 err_count, num_fail); 594 595 return 0; 596 } 597 598 static int 599 test_completion_status(int16_t dev_id, uint16_t vchan, bool fence) 600 { 601 const unsigned int fail[] = {0, 7, 14, 15}; 602 struct rte_mbuf *srcs[COMP_BURST_SZ], *dsts[COMP_BURST_SZ]; 603 unsigned int i; 604 605 for (i = 0; i < COMP_BURST_SZ; i++) { 606 srcs[i] = rte_pktmbuf_alloc(pool); 607 dsts[i] = rte_pktmbuf_alloc(pool); 608 } 609 610 for (i = 0; i < RTE_DIM(fail); i++) { 611 if (test_failure_in_full_burst(dev_id, vchan, fence, srcs, dsts, fail[i]) < 0) 612 return -1; 613 614 if (test_individual_status_query_with_failure(dev_id, vchan, fence, 615 srcs, dsts, fail[i]) < 0) 616 return -1; 617 618 /* test is run the same fenced, or unfenced, but no harm in running it twice */ 619 if (test_single_item_status_query_with_failure(dev_id, vchan, 620 srcs, dsts, fail[i]) < 0) 621 return -1; 622 } 623 624 if (test_multi_failure(dev_id, vchan, srcs, dsts, fail, RTE_DIM(fail)) < 0) 625 return -1; 626 627 for (i = 0; i < COMP_BURST_SZ; i++) { 628 rte_pktmbuf_free(srcs[i]); 629 rte_pktmbuf_free(dsts[i]); 630 } 631 return 0; 632 } 633 634 static int 635 test_completion_handling(int16_t dev_id, uint16_t vchan) 636 { 637 return test_completion_status(dev_id, vchan, false) /* without fences */ 638 || test_completion_status(dev_id, vchan, true); /* with fences */ 639 } 640 641 static int 642 test_enqueue_fill(int16_t dev_id, uint16_t vchan) 643 { 644 const unsigned int lengths[] = {8, 64, 1024, 50, 100, 89}; 645 struct rte_mbuf *dst; 646 char *dst_data; 647 uint64_t pattern = 0xfedcba9876543210; 648 unsigned int i, j; 649 650 dst = rte_pktmbuf_alloc(pool); 651 if (dst == NULL) 652 ERR_RETURN("Failed to allocate mbuf\n"); 653 dst_data = rte_pktmbuf_mtod(dst, char *); 654 655 for (i = 0; i < RTE_DIM(lengths); i++) { 656 /* reset dst_data */ 657 memset(dst_data, 0, rte_pktmbuf_data_len(dst)); 658 659 /* perform the fill operation */ 660 int id = rte_dma_fill(dev_id, vchan, pattern, 661 rte_pktmbuf_iova(dst), lengths[i], RTE_DMA_OP_FLAG_SUBMIT); 662 if (id < 0) 663 ERR_RETURN("Error with rte_dma_fill\n"); 664 await_hw(dev_id, vchan); 665 666 if (rte_dma_completed(dev_id, vchan, 1, NULL, NULL) != 1) 667 ERR_RETURN("Error: fill operation failed (length: %u)\n", lengths[i]); 668 /* check the data from the fill operation is correct */ 669 for (j = 0; j < lengths[i]; j++) { 670 char pat_byte = ((char *)&pattern)[j % 8]; 671 if (dst_data[j] != pat_byte) 672 ERR_RETURN("Error with fill operation (lengths = %u): got (%x), not (%x)\n", 673 lengths[i], dst_data[j], pat_byte); 674 } 675 /* check that the data after the fill operation was not written to */ 676 for (; j < rte_pktmbuf_data_len(dst); j++) 677 if (dst_data[j] != 0) 678 ERR_RETURN("Error, fill operation wrote too far (lengths = %u): got (%x), not (%x)\n", 679 lengths[i], dst_data[j], 0); 680 } 681 682 rte_pktmbuf_free(dst); 683 return 0; 684 } 685 686 static int 687 test_burst_capacity(int16_t dev_id, uint16_t vchan) 688 { 689 #define CAP_TEST_BURST_SIZE 64 690 const int ring_space = rte_dma_burst_capacity(dev_id, vchan); 691 struct rte_mbuf *src, *dst; 692 int i, j, iter; 693 int cap, ret; 694 bool dma_err; 695 696 src = rte_pktmbuf_alloc(pool); 697 dst = rte_pktmbuf_alloc(pool); 698 699 /* to test capacity, we enqueue elements and check capacity is reduced 700 * by one each time - rebaselining the expected value after each burst 701 * as the capacity is only for a burst. We enqueue multiple bursts to 702 * fill up half the ring, before emptying it again. We do this multiple 703 * times to ensure that we get to test scenarios where we get ring 704 * wrap-around and wrap-around of the ids returned (at UINT16_MAX). 705 */ 706 for (iter = 0; iter < 2 * (((int)UINT16_MAX + 1) / ring_space); iter++) { 707 for (i = 0; i < (ring_space / (2 * CAP_TEST_BURST_SIZE)) + 1; i++) { 708 cap = rte_dma_burst_capacity(dev_id, vchan); 709 710 for (j = 0; j < CAP_TEST_BURST_SIZE; j++) { 711 ret = rte_dma_copy(dev_id, vchan, rte_pktmbuf_iova(src), 712 rte_pktmbuf_iova(dst), COPY_LEN, 0); 713 if (ret < 0) 714 ERR_RETURN("Error with rte_dmadev_copy\n"); 715 716 if (rte_dma_burst_capacity(dev_id, vchan) != cap - (j + 1)) 717 ERR_RETURN("Error, ring capacity did not change as expected\n"); 718 } 719 if (rte_dma_submit(dev_id, vchan) < 0) 720 ERR_RETURN("Error, failed to submit burst\n"); 721 722 if (cap < rte_dma_burst_capacity(dev_id, vchan)) 723 ERR_RETURN("Error, avail ring capacity has gone up, not down\n"); 724 } 725 await_hw(dev_id, vchan); 726 727 for (i = 0; i < (ring_space / (2 * CAP_TEST_BURST_SIZE)) + 1; i++) { 728 ret = rte_dma_completed(dev_id, vchan, 729 CAP_TEST_BURST_SIZE, NULL, &dma_err); 730 if (ret != CAP_TEST_BURST_SIZE || dma_err) { 731 enum rte_dma_status_code status; 732 733 rte_dma_completed_status(dev_id, vchan, 1, NULL, &status); 734 ERR_RETURN("Error with rte_dmadev_completed, %u [expected: %u], dma_err = %d, i = %u, iter = %u, status = %u\n", 735 ret, CAP_TEST_BURST_SIZE, dma_err, i, iter, status); 736 } 737 } 738 cap = rte_dma_burst_capacity(dev_id, vchan); 739 if (cap != ring_space) 740 ERR_RETURN("Error, ring capacity has not reset to original value, got %u, expected %u\n", 741 cap, ring_space); 742 } 743 744 rte_pktmbuf_free(src); 745 rte_pktmbuf_free(dst); 746 747 return 0; 748 } 749 750 static int 751 test_dmadev_instance(int16_t dev_id) 752 { 753 #define TEST_RINGSIZE 512 754 #define CHECK_ERRS true 755 struct rte_dma_stats stats; 756 struct rte_dma_info info; 757 const struct rte_dma_conf conf = { .nb_vchans = 1}; 758 const struct rte_dma_vchan_conf qconf = { 759 .direction = RTE_DMA_DIR_MEM_TO_MEM, 760 .nb_desc = TEST_RINGSIZE, 761 }; 762 const int vchan = 0; 763 int ret; 764 765 ret = rte_dma_info_get(dev_id, &info); 766 if (ret != 0) 767 ERR_RETURN("Error with rte_dma_info_get()\n"); 768 769 printf("\n### Test dmadev instance %u [%s]\n", 770 dev_id, info.dev_name); 771 772 if (info.max_vchans < 1) 773 ERR_RETURN("Error, no channels available on device id %u\n", dev_id); 774 775 if (rte_dma_configure(dev_id, &conf) != 0) 776 ERR_RETURN("Error with rte_dma_configure()\n"); 777 778 if (rte_dma_vchan_setup(dev_id, vchan, &qconf) < 0) 779 ERR_RETURN("Error with queue configuration\n"); 780 781 ret = rte_dma_info_get(dev_id, &info); 782 if (ret != 0 || info.nb_vchans != 1) 783 ERR_RETURN("Error, no configured queues reported on device id %u\n", dev_id); 784 785 if (rte_dma_start(dev_id) != 0) 786 ERR_RETURN("Error with rte_dma_start()\n"); 787 788 if (rte_dma_stats_get(dev_id, vchan, &stats) != 0) 789 ERR_RETURN("Error with rte_dma_stats_get()\n"); 790 791 if (rte_dma_burst_capacity(dev_id, vchan) < 32) 792 ERR_RETURN("Error: Device does not have sufficient burst capacity to run tests"); 793 794 if (stats.completed != 0 || stats.submitted != 0 || stats.errors != 0) 795 ERR_RETURN("Error device stats are not all zero: completed = %"PRIu64", " 796 "submitted = %"PRIu64", errors = %"PRIu64"\n", 797 stats.completed, stats.submitted, stats.errors); 798 id_count = 0; 799 800 /* create a mempool for running tests */ 801 pool = rte_pktmbuf_pool_create("TEST_DMADEV_POOL", 802 TEST_RINGSIZE * 2, /* n == num elements */ 803 32, /* cache size */ 804 0, /* priv size */ 805 2048, /* data room size */ 806 info.numa_node); 807 if (pool == NULL) 808 ERR_RETURN("Error with mempool creation\n"); 809 810 /* run the test cases, use many iterations to ensure UINT16_MAX id wraparound */ 811 if (runtest("copy", test_enqueue_copies, 640, dev_id, vchan, CHECK_ERRS) < 0) 812 goto err; 813 814 /* run some burst capacity tests */ 815 if (rte_dma_burst_capacity(dev_id, vchan) < 64) 816 printf("DMA Dev %u: insufficient burst capacity (64 required), skipping tests\n", 817 dev_id); 818 else if (runtest("burst capacity", test_burst_capacity, 1, dev_id, vchan, CHECK_ERRS) < 0) 819 goto err; 820 821 /* to test error handling we can provide null pointers for source or dest in copies. This 822 * requires VA mode in DPDK, since NULL(0) is a valid physical address. 823 * We also need hardware that can report errors back. 824 */ 825 if (rte_eal_iova_mode() != RTE_IOVA_VA) 826 printf("DMA Dev %u: DPDK not in VA mode, skipping error handling tests\n", dev_id); 827 else if ((info.dev_capa & RTE_DMA_CAPA_HANDLES_ERRORS) == 0) 828 printf("DMA Dev %u: device does not report errors, skipping error handling tests\n", 829 dev_id); 830 else if (runtest("error handling", test_completion_handling, 1, 831 dev_id, vchan, !CHECK_ERRS) < 0) 832 goto err; 833 834 if ((info.dev_capa & RTE_DMA_CAPA_OPS_FILL) == 0) 835 printf("DMA Dev %u: No device fill support, skipping fill tests\n", dev_id); 836 else if (runtest("fill", test_enqueue_fill, 1, dev_id, vchan, CHECK_ERRS) < 0) 837 goto err; 838 839 rte_mempool_free(pool); 840 rte_dma_stop(dev_id); 841 rte_dma_stats_reset(dev_id, vchan); 842 return 0; 843 844 err: 845 rte_mempool_free(pool); 846 rte_dma_stop(dev_id); 847 return -1; 848 } 849 850 static int 851 test_apis(void) 852 { 853 const char *pmd = "dma_skeleton"; 854 int id; 855 int ret; 856 857 /* attempt to create skeleton instance - ignore errors due to one being already present */ 858 rte_vdev_init(pmd, NULL); 859 id = rte_dma_get_dev_id_by_name(pmd); 860 if (id < 0) 861 return TEST_SKIPPED; 862 printf("\n### Test dmadev infrastructure using skeleton driver\n"); 863 ret = test_dma_api(id); 864 865 return ret; 866 } 867 868 static int 869 test_dma(void) 870 { 871 int i; 872 873 /* basic sanity on dmadev infrastructure */ 874 if (test_apis() < 0) 875 ERR_RETURN("Error performing API tests\n"); 876 877 if (rte_dma_count_avail() == 0) 878 return TEST_SKIPPED; 879 880 RTE_DMA_FOREACH_DEV(i) 881 if (test_dmadev_instance(i) < 0) 882 ERR_RETURN("Error, test failure for device %d\n", i); 883 884 return 0; 885 } 886 887 REGISTER_TEST_COMMAND(dmadev_autotest, test_dma); 888