xref: /dpdk/app/test-pmd/testpmd.h (revision fd8c20aab4c2fe2c568455be4efab76db126791f)
1174a1631SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
2174a1631SBruce Richardson  * Copyright(c) 2010-2017 Intel Corporation
3af75078fSIntel  */
4af75078fSIntel 
5af75078fSIntel #ifndef _TESTPMD_H_
6af75078fSIntel #define _TESTPMD_H_
7af75078fSIntel 
885c18dcbSGaetan Rivet #include <rte_pci.h>
9c752998bSGaetan Rivet #include <rte_bus_pci.h>
10b40f8d78SJiayu Hu #include <rte_gro.h>
1152f38a20SJiayu Hu #include <rte_gso.h>
1285c18dcbSGaetan Rivet 
13ce8d5614SIntel #define RTE_PORT_ALL            (~(portid_t)0x0)
14ce8d5614SIntel 
15ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX    2048
16ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX    2048
17ce8d5614SIntel 
18ce8d5614SIntel #define RTE_PORT_STOPPED        (uint16_t)0
19ce8d5614SIntel #define RTE_PORT_STARTED        (uint16_t)1
20ce8d5614SIntel #define RTE_PORT_CLOSED         (uint16_t)2
21ce8d5614SIntel #define RTE_PORT_HANDLING       (uint16_t)3
22ce8d5614SIntel 
23af75078fSIntel /*
240f6f219eSMohammad Abdul Awal  * It is used to allocate the memory for hash key.
250f6f219eSMohammad Abdul Awal  * The hash key size is NIC dependent.
260f6f219eSMohammad Abdul Awal  */
270f6f219eSMohammad Abdul Awal #define RSS_HASH_KEY_LENGTH 64
280f6f219eSMohammad Abdul Awal 
290f6f219eSMohammad Abdul Awal /*
30af75078fSIntel  * Default size of the mbuf data buffer to receive standard 1518-byte
31af75078fSIntel  * Ethernet frames in a mono-segment memory buffer.
32af75078fSIntel  */
33824cb29cSKonstantin Ananyev #define DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE
34824cb29cSKonstantin Ananyev /**< Default size of mbuf data buffer. */
35af75078fSIntel 
36af75078fSIntel /*
37af75078fSIntel  * The maximum number of segments per packet is used when creating
38af75078fSIntel  * scattered transmit packets composed of a list of mbufs.
39af75078fSIntel  */
40ea672a8bSOlivier Matz #define RTE_MAX_SEGS_PER_PKT 255 /**< nb_segs is a 8-bit unsigned char. */
41af75078fSIntel 
42af75078fSIntel #define MAX_PKT_BURST 512
43836853d3SCunming Liang #define DEF_PKT_BURST 32
44af75078fSIntel 
45e9378bbcSCunming Liang #define DEF_MBUF_CACHE 250
46e9378bbcSCunming Liang 
47fdf20fa7SSergio Gonzalez Monroy #define RTE_CACHE_LINE_SIZE_ROUNDUP(size) \
48fdf20fa7SSergio Gonzalez Monroy 	(RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))
49af75078fSIntel 
50b6ea6408SIntel #define NUMA_NO_CONFIG 0xFF
51b6ea6408SIntel #define UMA_NO_CONFIG  0xFF
52b6ea6408SIntel 
53af75078fSIntel typedef uint8_t  lcoreid_t;
54f8244c63SZhiyong Yang typedef uint16_t portid_t;
55af75078fSIntel typedef uint16_t queueid_t;
56af75078fSIntel typedef uint16_t streamid_t;
57af75078fSIntel 
58af75078fSIntel #define MAX_QUEUE_ID ((1 << (sizeof(queueid_t) * 8)) - 1)
59af75078fSIntel 
605b590fbeSJasvinder Singh #if defined RTE_LIBRTE_PMD_SOFTNIC && defined RTE_LIBRTE_SCHED
615b590fbeSJasvinder Singh #define TM_MODE			1
625b590fbeSJasvinder Singh #else
635b590fbeSJasvinder Singh #define TM_MODE			0
645b590fbeSJasvinder Singh #endif
655b590fbeSJasvinder Singh 
66af75078fSIntel enum {
67af75078fSIntel 	PORT_TOPOLOGY_PAIRED,
683e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_CHAINED,
693e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_LOOP,
70af75078fSIntel };
71af75078fSIntel 
72af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
73af75078fSIntel /**
74af75078fSIntel  * The data structure associated with RX and TX packet burst statistics
75af75078fSIntel  * that are recorded for each forwarding stream.
76af75078fSIntel  */
77af75078fSIntel struct pkt_burst_stats {
78af75078fSIntel 	unsigned int pkt_burst_spread[MAX_PKT_BURST];
79af75078fSIntel };
80af75078fSIntel #endif
81af75078fSIntel 
82af75078fSIntel /**
83af75078fSIntel  * The data structure associated with a forwarding stream between a receive
84af75078fSIntel  * port/queue and a transmit port/queue.
85af75078fSIntel  */
86af75078fSIntel struct fwd_stream {
87af75078fSIntel 	/* "read-only" data */
88af75078fSIntel 	portid_t   rx_port;   /**< port to poll for received packets */
89af75078fSIntel 	queueid_t  rx_queue;  /**< RX queue to poll on "rx_port" */
90af75078fSIntel 	portid_t   tx_port;   /**< forwarding port of received packets */
91af75078fSIntel 	queueid_t  tx_queue;  /**< TX queue to send forwarded packets */
92af75078fSIntel 	streamid_t peer_addr; /**< index of peer ethernet address of packets */
93af75078fSIntel 
94bf56fce1SZhihong Wang 	unsigned int retry_enabled;
95bf56fce1SZhihong Wang 
96af75078fSIntel 	/* "read-write" results */
97af75078fSIntel 	unsigned int rx_packets;  /**< received packets */
98af75078fSIntel 	unsigned int tx_packets;  /**< received packets transmitted */
99af75078fSIntel 	unsigned int fwd_dropped; /**< received packets not forwarded */
100af75078fSIntel 	unsigned int rx_bad_ip_csum ; /**< received packets has bad ip checksum */
101af75078fSIntel 	unsigned int rx_bad_l4_csum ; /**< received packets has bad l4 checksum */
102b7091f1dSJiayu Hu 	unsigned int gro_times;	/**< GRO operation times */
103af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
104af75078fSIntel 	uint64_t     core_cycles; /**< used for RX and TX processing */
105af75078fSIntel #endif
106af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
107af75078fSIntel 	struct pkt_burst_stats rx_burst_stats;
108af75078fSIntel 	struct pkt_burst_stats tx_burst_stats;
109af75078fSIntel #endif
110af75078fSIntel };
111af75078fSIntel 
112938a184aSAdrien Mazarguil /** Descriptor for a single flow. */
113938a184aSAdrien Mazarguil struct port_flow {
114938a184aSAdrien Mazarguil 	size_t size; /**< Allocated space including data[]. */
115938a184aSAdrien Mazarguil 	struct port_flow *next; /**< Next flow in list. */
116938a184aSAdrien Mazarguil 	struct port_flow *tmp; /**< Temporary linking. */
117938a184aSAdrien Mazarguil 	uint32_t id; /**< Flow rule ID. */
118938a184aSAdrien Mazarguil 	struct rte_flow *flow; /**< Opaque flow object returned by PMD. */
119938a184aSAdrien Mazarguil 	struct rte_flow_attr attr; /**< Attributes. */
120938a184aSAdrien Mazarguil 	struct rte_flow_item *pattern; /**< Pattern. */
121938a184aSAdrien Mazarguil 	struct rte_flow_action *actions; /**< Actions. */
122938a184aSAdrien Mazarguil 	uint8_t data[]; /**< Storage for pattern/actions. */
123938a184aSAdrien Mazarguil };
124938a184aSAdrien Mazarguil 
1255b590fbeSJasvinder Singh #ifdef TM_MODE
1265b590fbeSJasvinder Singh /**
1275b590fbeSJasvinder Singh  * Soft port tm related parameters
1285b590fbeSJasvinder Singh  */
1295b590fbeSJasvinder Singh struct softnic_port_tm {
1305b590fbeSJasvinder Singh 	uint32_t default_hierarchy_enable; /**< def hierarchy enable flag */
1315b590fbeSJasvinder Singh 	uint32_t hierarchy_config;  /**< set to 1 if hierarchy configured */
1325b590fbeSJasvinder Singh 
1335b590fbeSJasvinder Singh 	uint32_t n_subports_per_port;  /**< Num of subport nodes per port */
1345b590fbeSJasvinder Singh 	uint32_t n_pipes_per_subport;  /**< Num of pipe nodes per subport */
1355b590fbeSJasvinder Singh 
1365b590fbeSJasvinder Singh 	uint64_t tm_pktfield0_slabpos;	/**< Pkt field position for subport */
1375b590fbeSJasvinder Singh 	uint64_t tm_pktfield0_slabmask; /**< Pkt field mask for the subport */
1385b590fbeSJasvinder Singh 	uint64_t tm_pktfield0_slabshr;
1395b590fbeSJasvinder Singh 	uint64_t tm_pktfield1_slabpos; /**< Pkt field position for the pipe */
1405b590fbeSJasvinder Singh 	uint64_t tm_pktfield1_slabmask; /**< Pkt field mask for the pipe */
1415b590fbeSJasvinder Singh 	uint64_t tm_pktfield1_slabshr;
1425b590fbeSJasvinder Singh 	uint64_t tm_pktfield2_slabpos; /**< Pkt field position table index */
1435b590fbeSJasvinder Singh 	uint64_t tm_pktfield2_slabmask;	/**< Pkt field mask for tc table idx */
1445b590fbeSJasvinder Singh 	uint64_t tm_pktfield2_slabshr;
1455b590fbeSJasvinder Singh 	uint64_t tm_tc_table[64];  /**< TC translation table */
1465b590fbeSJasvinder Singh };
1475b590fbeSJasvinder Singh 
1485b590fbeSJasvinder Singh /**
1495b590fbeSJasvinder Singh  * The data structure associate with softnic port
1505b590fbeSJasvinder Singh  */
1515b590fbeSJasvinder Singh struct softnic_port {
1525b590fbeSJasvinder Singh 	unsigned int tm_flag;	/**< set to 1 if tm feature is enabled */
1535b590fbeSJasvinder Singh 	struct softnic_port_tm tm;	/**< softnic port tm parameters */
1545b590fbeSJasvinder Singh };
1555b590fbeSJasvinder Singh #endif
1565b590fbeSJasvinder Singh 
157af75078fSIntel /**
158af75078fSIntel  * The data structure associated with each port.
159af75078fSIntel  */
160af75078fSIntel struct rte_port {
161af75078fSIntel 	struct rte_eth_dev_info dev_info;   /**< PCI info + driver name */
162af75078fSIntel 	struct rte_eth_conf     dev_conf;   /**< Port configuration. */
163af75078fSIntel 	struct ether_addr       eth_addr;   /**< Port ethernet address */
164af75078fSIntel 	struct rte_eth_stats    stats;      /**< Last port statistics */
165af75078fSIntel 	uint64_t                tx_dropped; /**< If no descriptor in TX ring */
166af75078fSIntel 	struct fwd_stream       *rx_stream; /**< Port RX stream, if unique */
167af75078fSIntel 	struct fwd_stream       *tx_stream; /**< Port TX stream, if unique */
168af75078fSIntel 	unsigned int            socket_id;  /**< For NUMA support */
1693eecba26SShahaf Shuler 	uint16_t		parse_tunnel:1; /**< Parse internal headers */
1700f62d635SJianfeng Tan 	uint16_t                tso_segsz;  /**< Segmentation offload MSS for non-tunneled packets. */
1710f62d635SJianfeng Tan 	uint16_t                tunnel_tso_segsz; /**< Segmentation offload MSS for tunneled pkts. */
17292ebda07SHelin Zhang 	uint16_t                tx_vlan_id;/**< The tag ID */
17392ebda07SHelin Zhang 	uint16_t                tx_vlan_id_outer;/**< The outer tag ID */
174af75078fSIntel 	void                    *fwd_ctx;   /**< Forwarding mode context */
175af75078fSIntel 	uint64_t                rx_bad_ip_csum; /**< rx pkts with bad ip checksum  */
176af75078fSIntel 	uint64_t                rx_bad_l4_csum; /**< rx pkts with bad l4 checksum */
177ed30d9b6SIntel 	uint8_t                 tx_queue_stats_mapping_enabled;
178ed30d9b6SIntel 	uint8_t                 rx_queue_stats_mapping_enabled;
179ce8d5614SIntel 	volatile uint16_t        port_status;    /**< port started or not */
180ce8d5614SIntel 	uint8_t                 need_reconfig;  /**< need reconfiguring port or not */
181ce8d5614SIntel 	uint8_t                 need_reconfig_queues; /**< need reconfiguring queues or not */
182ce8d5614SIntel 	uint8_t                 rss_flag;   /**< enable rss or not */
1837741e4cfSIntel 	uint8_t                 dcb_flag;   /**< enable dcb */
184ce8d5614SIntel 	struct rte_eth_rxconf   rx_conf;    /**< rx configuration */
185ce8d5614SIntel 	struct rte_eth_txconf   tx_conf;    /**< tx configuration */
1868fff6675SIvan Boule 	struct ether_addr       *mc_addr_pool; /**< pool of multicast addrs */
1878fff6675SIvan Boule 	uint32_t                mc_addr_nb; /**< nb. of addr. in mc_addr_pool */
18841b05095SBernard Iremonger 	uint8_t                 slave_flag; /**< bonding slave port */
189938a184aSAdrien Mazarguil 	struct port_flow        *flow_list; /**< Associated flows. */
1905b590fbeSJasvinder Singh #ifdef TM_MODE
1915b590fbeSJasvinder Singh 	unsigned int			softnic_enable;	/**< softnic flag */
1925b590fbeSJasvinder Singh 	struct softnic_port     softport;  /**< softnic port params */
1935b590fbeSJasvinder Singh #endif
194af75078fSIntel };
195af75078fSIntel 
196af75078fSIntel /**
197af75078fSIntel  * The data structure associated with each forwarding logical core.
198af75078fSIntel  * The logical cores are internally numbered by a core index from 0 to
199af75078fSIntel  * the maximum number of logical cores - 1.
200af75078fSIntel  * The system CPU identifier of all logical cores are setup in a global
201af75078fSIntel  * CPU id. configuration table.
202af75078fSIntel  */
203af75078fSIntel struct fwd_lcore {
20452f38a20SJiayu Hu 	struct rte_gso_ctx gso_ctx;     /**< GSO context */
205af75078fSIntel 	struct rte_mempool *mbp; /**< The mbuf pool to use by this core */
206b7091f1dSJiayu Hu 	void *gro_ctx;		/**< GRO context */
207af75078fSIntel 	streamid_t stream_idx;   /**< index of 1st stream in "fwd_streams" */
208af75078fSIntel 	streamid_t stream_nb;    /**< number of streams in "fwd_streams" */
209af75078fSIntel 	lcoreid_t  cpuid_idx;    /**< index of logical core in CPU id table */
210af75078fSIntel 	queueid_t  tx_queue;     /**< TX queue to send forwarded packets */
211af75078fSIntel 	volatile char stopped;   /**< stop forwarding when set */
212af75078fSIntel };
213af75078fSIntel 
214af75078fSIntel /*
215af75078fSIntel  * Forwarding mode operations:
216af75078fSIntel  *   - IO forwarding mode (default mode)
217af75078fSIntel  *     Forwards packets unchanged.
218af75078fSIntel  *
219af75078fSIntel  *   - MAC forwarding mode
220af75078fSIntel  *     Set the source and the destination Ethernet addresses of packets
221af75078fSIntel  *     before forwarding them.
222af75078fSIntel  *
223af75078fSIntel  *   - IEEE1588 forwarding mode
224af75078fSIntel  *     Check that received IEEE1588 Precise Time Protocol (PTP) packets are
225af75078fSIntel  *     filtered and timestamped by the hardware.
226af75078fSIntel  *     Forwards packets unchanged on the same port.
227af75078fSIntel  *     Check that sent IEEE1588 PTP packets are timestamped by the hardware.
228af75078fSIntel  */
229af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi);
230af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi);
231af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs);
232af75078fSIntel 
233af75078fSIntel struct fwd_engine {
234af75078fSIntel 	const char       *fwd_mode_name; /**< Forwarding mode name. */
235af75078fSIntel 	port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */
236af75078fSIntel 	port_fwd_end_t   port_fwd_end;   /**< NULL if nothing special to do. */
237af75078fSIntel 	packet_fwd_t     packet_fwd;     /**< Mandatory. */
238af75078fSIntel };
239af75078fSIntel 
240bf56fce1SZhihong Wang #define BURST_TX_WAIT_US 1
241bf56fce1SZhihong Wang #define BURST_TX_RETRIES 64
242bf56fce1SZhihong Wang 
243bf56fce1SZhihong Wang extern uint32_t burst_tx_delay_time;
244bf56fce1SZhihong Wang extern uint32_t burst_tx_retry_num;
245bf56fce1SZhihong Wang 
246af75078fSIntel extern struct fwd_engine io_fwd_engine;
247af75078fSIntel extern struct fwd_engine mac_fwd_engine;
248d47388f1SCyril Chemparathy extern struct fwd_engine mac_swap_engine;
249e9e23a61SCyril Chemparathy extern struct fwd_engine flow_gen_engine;
250af75078fSIntel extern struct fwd_engine rx_only_engine;
251af75078fSIntel extern struct fwd_engine tx_only_engine;
252af75078fSIntel extern struct fwd_engine csum_fwd_engine;
253168dfa61SIvan Boule extern struct fwd_engine icmp_echo_engine;
2545b590fbeSJasvinder Singh #ifdef TM_MODE
2555b590fbeSJasvinder Singh extern struct fwd_engine softnic_tm_engine;
2565b590fbeSJasvinder Singh extern struct fwd_engine softnic_tm_bypass_engine;
2575b590fbeSJasvinder Singh #endif
258af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588
259af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine;
260af75078fSIntel #endif
261af75078fSIntel 
262af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */
263af75078fSIntel 
264af75078fSIntel /**
265af75078fSIntel  * Forwarding Configuration
266af75078fSIntel  *
267af75078fSIntel  */
268af75078fSIntel struct fwd_config {
269af75078fSIntel 	struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */
270af75078fSIntel 	streamid_t nb_fwd_streams;  /**< Nb. of forward streams to process. */
271af75078fSIntel 	lcoreid_t  nb_fwd_lcores;   /**< Nb. of logical cores to launch. */
272af75078fSIntel 	portid_t   nb_fwd_ports;    /**< Nb. of ports involved. */
273af75078fSIntel };
274af75078fSIntel 
275900550deSIntel /**
276900550deSIntel  * DCB mode enable
277900550deSIntel  */
278900550deSIntel enum dcb_mode_enable
279900550deSIntel {
280900550deSIntel 	DCB_VT_ENABLED,
281900550deSIntel 	DCB_ENABLED
282900550deSIntel };
283900550deSIntel 
284ed30d9b6SIntel #define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */
285ed30d9b6SIntel #define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */
286ed30d9b6SIntel 
287ed30d9b6SIntel struct queue_stats_mappings {
288f8244c63SZhiyong Yang 	portid_t port_id;
289ed30d9b6SIntel 	uint16_t queue_id;
290ed30d9b6SIntel 	uint8_t stats_counter_id;
291ed30d9b6SIntel } __rte_cache_aligned;
292ed30d9b6SIntel 
293ed30d9b6SIntel extern struct queue_stats_mappings tx_queue_stats_mappings_array[];
294ed30d9b6SIntel extern struct queue_stats_mappings rx_queue_stats_mappings_array[];
295ed30d9b6SIntel 
296ed30d9b6SIntel /* Assign both tx and rx queue stats mappings to the same default values */
297ed30d9b6SIntel extern struct queue_stats_mappings *tx_queue_stats_mappings;
298ed30d9b6SIntel extern struct queue_stats_mappings *rx_queue_stats_mappings;
299ed30d9b6SIntel 
300ed30d9b6SIntel extern uint16_t nb_tx_queue_stats_mappings;
301ed30d9b6SIntel extern uint16_t nb_rx_queue_stats_mappings;
302ed30d9b6SIntel 
303a4fd5eeeSElza Mathew extern uint8_t xstats_hide_zero; /**< Hide zero values for xstats display */
304a4fd5eeeSElza Mathew 
305af75078fSIntel /* globals used for configuration */
306af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */
307285fd101SOlivier Matz extern int testpmd_logtype; /**< Log type for testpmd logs */
308af75078fSIntel extern uint8_t  interactive;
309ca7feb22SCyril Chemparathy extern uint8_t  auto_start;
31099cabef0SPablo de Lara extern uint8_t  tx_first;
31181ef862bSAllain Legacy extern char cmdline_filename[PATH_MAX]; /**< offline commands file */
312af75078fSIntel extern uint8_t  numa_support; /**< set by "--numa" parameter */
313af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */
3147741e4cfSIntel extern uint8_t no_flush_rx; /**<set by "--no-flush-rx" parameter */
3157ee3e944SVasily Philipov extern uint8_t flow_isolate_all; /**< set by "--flow-isolate-all */
316148f963fSBruce Richardson extern uint8_t  mp_anon; /**< set by "--mp-anon" parameter */
317bc202406SDavid Marchand extern uint8_t no_link_check; /**<set by "--disable-link-check" parameter */
3182950a769SDeclan Doherty extern volatile int test_done; /* stop packet forwarding when set to 1. */
3198ea656f8SGaetan Rivet extern uint8_t lsc_interrupt; /**< disabled by "--no-lsc-interrupt" parameter */
320284c908cSGaetan Rivet extern uint8_t rmv_interrupt; /**< disabled by "--no-rmv-interrupt" parameter */
3213af72783SGaetan Rivet extern uint32_t event_print_mask;
3223af72783SGaetan Rivet /**< set by "--print-event xxxx" and "--mask-event xxxx parameters */
323af75078fSIntel 
324e261265eSRadu Nicolau #ifdef RTE_LIBRTE_IXGBE_BYPASS
3257b7e5ba7SIntel extern uint32_t bypass_timeout; /**< Store the NIC bypass watchdog timeout */
3267b7e5ba7SIntel #endif
3277b7e5ba7SIntel 
328b6ea6408SIntel /*
329b6ea6408SIntel  * Store specified sockets on which memory pool to be used by ports
330b6ea6408SIntel  * is allocated.
331b6ea6408SIntel  */
332b6ea6408SIntel uint8_t port_numa[RTE_MAX_ETHPORTS];
333b6ea6408SIntel 
334b6ea6408SIntel /*
335b6ea6408SIntel  * Store specified sockets on which RX ring to be used by ports
336b6ea6408SIntel  * is allocated.
337b6ea6408SIntel  */
338b6ea6408SIntel uint8_t rxring_numa[RTE_MAX_ETHPORTS];
339b6ea6408SIntel 
340b6ea6408SIntel /*
341b6ea6408SIntel  * Store specified sockets on which TX ring to be used by ports
342b6ea6408SIntel  * is allocated.
343b6ea6408SIntel  */
344b6ea6408SIntel uint8_t txring_numa[RTE_MAX_ETHPORTS];
345b6ea6408SIntel 
346b6ea6408SIntel extern uint8_t socket_num;
347b6ea6408SIntel 
348af75078fSIntel /*
349af75078fSIntel  * Configuration of logical cores:
350af75078fSIntel  * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores
351af75078fSIntel  */
352af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */
353af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */
354af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */
355af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE];
356c9cafcc8SShahaf Shuler extern unsigned int num_sockets;
357c9cafcc8SShahaf Shuler extern unsigned int socket_ids[RTE_MAX_NUMA_NODES];
358af75078fSIntel 
359af75078fSIntel /*
360af75078fSIntel  * Configuration of Ethernet ports:
361af75078fSIntel  * nb_fwd_ports <= nb_cfg_ports <= nb_ports
362af75078fSIntel  */
363af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */
364af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */
365af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */
366af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS];
367af75078fSIntel extern struct rte_port *ports;
368af75078fSIntel 
369af75078fSIntel extern struct rte_eth_rxmode rx_mode;
370*fd8c20aaSShahaf Shuler extern struct rte_eth_txmode tx_mode;
371*fd8c20aaSShahaf Shuler 
3728a387fa8SHelin Zhang extern uint64_t rss_hf;
373af75078fSIntel 
374af75078fSIntel extern queueid_t nb_rxq;
375af75078fSIntel extern queueid_t nb_txq;
376af75078fSIntel 
377af75078fSIntel extern uint16_t nb_rxd;
378af75078fSIntel extern uint16_t nb_txd;
379af75078fSIntel 
380f2c5125aSPablo de Lara extern int16_t rx_free_thresh;
381f2c5125aSPablo de Lara extern int8_t rx_drop_en;
382f2c5125aSPablo de Lara extern int16_t tx_free_thresh;
383f2c5125aSPablo de Lara extern int16_t tx_rs_thresh;
384f2c5125aSPablo de Lara extern int32_t txq_flags;
385af75078fSIntel 
386900550deSIntel extern uint8_t dcb_config;
387900550deSIntel extern uint8_t dcb_test;
388900550deSIntel extern enum dcb_queue_mapping_mode dcb_q_mapping;
389900550deSIntel 
390af75078fSIntel extern uint16_t mbuf_data_size; /**< Mbuf data space size. */
391c8798818SIntel extern uint32_t param_total_num_mbufs;
392af75078fSIntel 
393cfea1f30SPablo de Lara extern uint16_t stats_period;
39462d3216dSReshma Pattan 
39562d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS
39662d3216dSReshma Pattan extern uint8_t latencystats_enabled;
39762d3216dSReshma Pattan extern lcoreid_t latencystats_lcore_id;
39862d3216dSReshma Pattan #endif
39962d3216dSReshma Pattan 
400e25e6c70SRemy Horton #ifdef RTE_LIBRTE_BITRATE
401e25e6c70SRemy Horton extern lcoreid_t bitrate_lcore_id;
402e25e6c70SRemy Horton extern uint8_t bitrate_enabled;
403e25e6c70SRemy Horton #endif
404e25e6c70SRemy Horton 
405af75078fSIntel extern struct rte_fdir_conf fdir_conf;
406af75078fSIntel 
407af75078fSIntel /*
408af75078fSIntel  * Configuration of packet segments used by the "txonly" processing engine.
409af75078fSIntel  */
410af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64
411af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */
412af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */
413af75078fSIntel extern uint8_t  tx_pkt_nb_segs; /**< Number of segments in TX packets */
414af75078fSIntel 
41579bec05bSKonstantin Ananyev enum tx_pkt_split {
41679bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_OFF,
41779bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_ON,
41879bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_RND,
41979bec05bSKonstantin Ananyev };
42079bec05bSKonstantin Ananyev 
42179bec05bSKonstantin Ananyev extern enum tx_pkt_split tx_pkt_split;
42279bec05bSKonstantin Ananyev 
423af75078fSIntel extern uint16_t nb_pkt_per_burst;
424af75078fSIntel extern uint16_t mb_mempool_cache;
425f2c5125aSPablo de Lara extern int8_t rx_pthresh;
426f2c5125aSPablo de Lara extern int8_t rx_hthresh;
427f2c5125aSPablo de Lara extern int8_t rx_wthresh;
428f2c5125aSPablo de Lara extern int8_t tx_pthresh;
429f2c5125aSPablo de Lara extern int8_t tx_hthresh;
430f2c5125aSPablo de Lara extern int8_t tx_wthresh;
431af75078fSIntel 
432af75078fSIntel extern struct fwd_config cur_fwd_config;
433af75078fSIntel extern struct fwd_engine *cur_fwd_eng;
434bf56fce1SZhihong Wang extern uint32_t retry_enabled;
435af75078fSIntel extern struct fwd_lcore  **fwd_lcores;
436af75078fSIntel extern struct fwd_stream **fwd_streams;
437af75078fSIntel 
438af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */
439af75078fSIntel extern struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS];
440af75078fSIntel 
44157e85242SBruce Richardson extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */
44257e85242SBruce Richardson extern uint32_t burst_tx_retry_num;  /**< Burst tx retry number for mac-retry. */
44357e85242SBruce Richardson 
444b7091f1dSJiayu Hu #define GRO_DEFAULT_ITEM_NUM_PER_FLOW 32
445b7091f1dSJiayu Hu #define GRO_DEFAULT_FLOW_NUM (RTE_GRO_MAX_BURST_ITEM_NUM / \
446b7091f1dSJiayu Hu 		GRO_DEFAULT_ITEM_NUM_PER_FLOW)
447b7091f1dSJiayu Hu 
448b7091f1dSJiayu Hu #define GRO_DEFAULT_FLUSH_CYCLES 1
449b7091f1dSJiayu Hu #define GRO_MAX_FLUSH_CYCLES 4
450b7091f1dSJiayu Hu 
451b40f8d78SJiayu Hu struct gro_status {
452b40f8d78SJiayu Hu 	struct rte_gro_param param;
453b40f8d78SJiayu Hu 	uint8_t enable;
454b40f8d78SJiayu Hu };
455b40f8d78SJiayu Hu extern struct gro_status gro_ports[RTE_MAX_ETHPORTS];
456b7091f1dSJiayu Hu extern uint8_t gro_flush_cycles;
457b40f8d78SJiayu Hu 
45852f38a20SJiayu Hu #define GSO_MAX_PKT_BURST 2048
45952f38a20SJiayu Hu struct gso_status {
46052f38a20SJiayu Hu 	uint8_t enable;
46152f38a20SJiayu Hu };
46252f38a20SJiayu Hu extern struct gso_status gso_ports[RTE_MAX_ETHPORTS];
46352f38a20SJiayu Hu extern uint16_t gso_max_segment_size;
46452f38a20SJiayu Hu 
465af75078fSIntel static inline unsigned int
466af75078fSIntel lcore_num(void)
467af75078fSIntel {
468af75078fSIntel 	unsigned int i;
469af75078fSIntel 
470af75078fSIntel 	for (i = 0; i < RTE_MAX_LCORE; ++i)
471af75078fSIntel 		if (fwd_lcores_cpuids[i] == rte_lcore_id())
472af75078fSIntel 			return i;
473af75078fSIntel 
474af75078fSIntel 	rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n");
475af75078fSIntel }
476af75078fSIntel 
477af75078fSIntel static inline struct fwd_lcore *
478af75078fSIntel current_fwd_lcore(void)
479af75078fSIntel {
480af75078fSIntel 	return fwd_lcores[lcore_num()];
481af75078fSIntel }
482af75078fSIntel 
483af75078fSIntel /* Mbuf Pools */
484af75078fSIntel static inline void
485af75078fSIntel mbuf_poolname_build(unsigned int sock_id, char* mp_name, int name_size)
486af75078fSIntel {
4876f41fe75SStephen Hemminger 	snprintf(mp_name, name_size, "mbuf_pool_socket_%u", sock_id);
488af75078fSIntel }
489af75078fSIntel 
490af75078fSIntel static inline struct rte_mempool *
491af75078fSIntel mbuf_pool_find(unsigned int sock_id)
492af75078fSIntel {
493af75078fSIntel 	char pool_name[RTE_MEMPOOL_NAMESIZE];
494af75078fSIntel 
495af75078fSIntel 	mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name));
496693f715dSHuawei Xie 	return rte_mempool_lookup((const char *)pool_name);
497af75078fSIntel }
498af75078fSIntel 
499af75078fSIntel /**
500af75078fSIntel  * Read/Write operations on a PCI register of a port.
501af75078fSIntel  */
502af75078fSIntel static inline uint32_t
503af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off)
504af75078fSIntel {
505af75078fSIntel 	void *reg_addr;
506af75078fSIntel 	uint32_t reg_v;
507af75078fSIntel 
508eee16c96SStephen Hemminger 	reg_addr = (void *)
509eee16c96SStephen Hemminger 		((char *)port->dev_info.pci_dev->mem_resource[0].addr +
510af75078fSIntel 			reg_off);
511af75078fSIntel 	reg_v = *((volatile uint32_t *)reg_addr);
512af75078fSIntel 	return rte_le_to_cpu_32(reg_v);
513af75078fSIntel }
514af75078fSIntel 
515af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \
516af75078fSIntel 	port_pci_reg_read(&ports[(pt_id)], (reg_off))
517af75078fSIntel 
518af75078fSIntel static inline void
519af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v)
520af75078fSIntel {
521af75078fSIntel 	void *reg_addr;
522af75078fSIntel 
523eee16c96SStephen Hemminger 	reg_addr = (void *)
524eee16c96SStephen Hemminger 		((char *)port->dev_info.pci_dev->mem_resource[0].addr +
525af75078fSIntel 			reg_off);
526af75078fSIntel 	*((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v);
527af75078fSIntel }
528af75078fSIntel 
529af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \
530af75078fSIntel 	port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value))
531af75078fSIntel 
532af75078fSIntel /* Prototypes */
533950d1516SBruce Richardson unsigned int parse_item_list(char* str, const char* item_name,
534950d1516SBruce Richardson 			unsigned int max_items,
535950d1516SBruce Richardson 			unsigned int *parsed_items, int check_unique_values);
536af75078fSIntel void launch_args_parse(int argc, char** argv);
53781ef862bSAllain Legacy void cmdline_read_from_file(const char *filename);
538af75078fSIntel void prompt(void);
539d3a274ceSZhihong Wang void prompt_exit(void);
540af75078fSIntel void nic_stats_display(portid_t port_id);
541af75078fSIntel void nic_stats_clear(portid_t port_id);
542bfd5051bSOlivier Matz void nic_xstats_display(portid_t port_id);
543bfd5051bSOlivier Matz void nic_xstats_clear(portid_t port_id);
544ed30d9b6SIntel void nic_stats_mapping_display(portid_t port_id);
545af75078fSIntel void port_infos_display(portid_t port_id);
546d28645c7SQiming Yang void port_offload_cap_display(portid_t port_id);
547ab3257e1SKonstantin Ananyev void rx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
548ab3257e1SKonstantin Ananyev void tx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
549af75078fSIntel void fwd_lcores_config_display(void);
5500c0db76fSBernard Iremonger void pkt_fwd_config_display(struct fwd_config *cfg);
551af75078fSIntel void rxtx_config_display(void);
552af75078fSIntel void fwd_config_setup(void);
553af75078fSIntel void set_def_fwd_config(void);
554a21d5a4bSDeclan Doherty void reconfig(portid_t new_port_id, unsigned socket_id);
555013af9b6SIntel int init_fwd_streams(void);
556013af9b6SIntel 
557ae03d0d1SIvan Boule void port_mtu_set(portid_t port_id, uint16_t mtu);
558af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos);
559af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos,
560af75078fSIntel 		      uint8_t bit_v);
561af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off,
562af75078fSIntel 				uint8_t bit1_pos, uint8_t bit2_pos);
563af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off,
564af75078fSIntel 			    uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value);
565af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off);
566af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value);
567938a184aSAdrien Mazarguil int port_flow_validate(portid_t port_id,
568938a184aSAdrien Mazarguil 		       const struct rte_flow_attr *attr,
569938a184aSAdrien Mazarguil 		       const struct rte_flow_item *pattern,
570938a184aSAdrien Mazarguil 		       const struct rte_flow_action *actions);
571938a184aSAdrien Mazarguil int port_flow_create(portid_t port_id,
572938a184aSAdrien Mazarguil 		     const struct rte_flow_attr *attr,
573938a184aSAdrien Mazarguil 		     const struct rte_flow_item *pattern,
574938a184aSAdrien Mazarguil 		     const struct rte_flow_action *actions);
575938a184aSAdrien Mazarguil int port_flow_destroy(portid_t port_id, uint32_t n, const uint32_t *rule);
576938a184aSAdrien Mazarguil int port_flow_flush(portid_t port_id);
577938a184aSAdrien Mazarguil int port_flow_query(portid_t port_id, uint32_t rule,
578938a184aSAdrien Mazarguil 		    enum rte_flow_action_type action);
579938a184aSAdrien Mazarguil void port_flow_list(portid_t port_id, uint32_t n, const uint32_t *group);
580323f811aSAdrien Mazarguil int port_flow_isolate(portid_t port_id, int set);
581af75078fSIntel 
582af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id);
583af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id);
584af75078fSIntel 
585013af9b6SIntel int set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc);
586013af9b6SIntel int set_fwd_lcores_mask(uint64_t lcoremask);
587af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc);
588af75078fSIntel 
589af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt);
590af75078fSIntel void set_fwd_ports_mask(uint64_t portmask);
591af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt);
592a8ef3e3aSBernard Iremonger int port_is_forwarding(portid_t port_id);
593af75078fSIntel 
594a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on);
595a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on);
596a47aa8b9SIntel 
597a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on);
598af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on);
59964b01ee0SMichal Jastrzebski int rx_vft_set(portid_t port_id, uint16_t vlan_id, int on);
600a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on);
60119b16e2fSHelin Zhang void vlan_tpid_set(portid_t port_id, enum rte_vlan_type vlan_type,
60219b16e2fSHelin Zhang 		   uint16_t tp_id);
603af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id);
60492ebda07SHelin Zhang void tx_qinq_set(portid_t port_id, uint16_t vlan_id, uint16_t vlan_id_outer);
605af75078fSIntel void tx_vlan_reset(portid_t port_id);
606529ba951SHelin Zhang void tx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on);
607ed30d9b6SIntel 
608ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value);
609ed30d9b6SIntel 
610a4fd5eeeSElza Mathew void set_xstats_hide_zero(uint8_t on_off);
611a4fd5eeeSElza Mathew 
612af75078fSIntel void set_verbose_level(uint16_t vb_level);
613af75078fSIntel void set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs);
61479bec05bSKonstantin Ananyev void show_tx_pkt_segments(void);
61579bec05bSKonstantin Ananyev void set_tx_pkt_split(const char *name);
616af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst);
617769ce6b1SThomas Monjalon char *list_pkt_forwarding_modes(void);
618bf56fce1SZhihong Wang char *list_pkt_forwarding_retry_modes(void);
619af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode);
620af75078fSIntel void start_packet_forwarding(int with_tx_first);
621af75078fSIntel void stop_packet_forwarding(void);
622cfae07fdSOuyang Changchun void dev_set_link_up(portid_t pid);
623cfae07fdSOuyang Changchun void dev_set_link_down(portid_t pid);
624ce8d5614SIntel void init_port_config(void);
62541b05095SBernard Iremonger void set_port_slave_flag(portid_t slave_pid);
62641b05095SBernard Iremonger void clear_port_slave_flag(portid_t slave_pid);
6270e545d30SBernard Iremonger uint8_t port_is_bonding_slave(portid_t slave_pid);
6280e545d30SBernard Iremonger 
6291a572499SJingjing Wu int init_port_dcb_config(portid_t pid, enum dcb_mode_enable dcb_mode,
6301a572499SJingjing Wu 		     enum rte_eth_nb_tcs num_tcs,
6311a572499SJingjing Wu 		     uint8_t pfc_en);
632148f963fSBruce Richardson int start_port(portid_t pid);
633ce8d5614SIntel void stop_port(portid_t pid);
634ce8d5614SIntel void close_port(portid_t pid);
63597f1e196SWei Dai void reset_port(portid_t pid);
636edab33b1STetsuya Mukawa void attach_port(char *identifier);
63728caa76aSZhiyong Yang void detach_port(portid_t port_id);
638ce8d5614SIntel int all_ports_stopped(void);
6396018eb8cSShahaf Shuler int port_is_stopped(portid_t port_id);
6405f4ec54fSChen Jing D(Mark) int port_is_started(portid_t port_id);
641af75078fSIntel void pmd_test_exit(void);
642af75078fSIntel void fdir_get_infos(portid_t port_id);
643aeca06dfSJingjing Wu void fdir_set_flex_mask(portid_t port_id,
644aeca06dfSJingjing Wu 			   struct rte_eth_fdir_flex_mask *cfg);
64597b74464SJingjing Wu void fdir_set_flex_payload(portid_t port_id,
64697b74464SJingjing Wu 			   struct rte_eth_flex_payload_cfg *cfg);
64766c59490SHelin Zhang void port_rss_reta_info(portid_t port_id,
64866c59490SHelin Zhang 			struct rte_eth_rss_reta_entry64 *reta_conf,
64966c59490SHelin Zhang 			uint16_t nb_entries);
6506a18e1afSOuyang Changchun 
6517741e4cfSIntel void set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on);
652af75078fSIntel 
6536a18e1afSOuyang Changchun int set_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate);
6546a18e1afSOuyang Changchun int set_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate,
6556a18e1afSOuyang Changchun 				uint64_t q_msk);
6566a18e1afSOuyang Changchun 
6578205e241SNelio Laranjeiro void port_rss_hash_conf_show(portid_t port_id, char rss_info[],
6588205e241SNelio Laranjeiro 			     int show_rss_key);
6598205e241SNelio Laranjeiro void port_rss_hash_key_update(portid_t port_id, char rss_type[],
6608205e241SNelio Laranjeiro 			      uint8_t *hash_key, uint hash_key_len);
6615f4ec54fSChen Jing D(Mark) int rx_queue_id_is_invalid(queueid_t rxq_id);
6625f4ec54fSChen Jing D(Mark) int tx_queue_id_is_invalid(queueid_t txq_id);
663b7091f1dSJiayu Hu void setup_gro(const char *onoff, portid_t port_id);
664b7091f1dSJiayu Hu void setup_gro_flush_cycles(uint8_t cycles);
665b7091f1dSJiayu Hu void show_gro(portid_t port_id);
66652f38a20SJiayu Hu void setup_gso(const char *mode, portid_t port_id);
66716321de0SIvan Boule 
6688fff6675SIvan Boule /* Functions to manage the set of filtered Multicast MAC addresses */
66928caa76aSZhiyong Yang void mcast_addr_add(portid_t port_id, struct ether_addr *mc_addr);
67028caa76aSZhiyong Yang void mcast_addr_remove(portid_t port_id, struct ether_addr *mc_addr);
67128caa76aSZhiyong Yang void port_dcb_info_display(portid_t port_id);
6728fff6675SIvan Boule 
673a92a5a2cSBeilei Xing uint8_t *open_ddp_package_file(const char *file_path, uint32_t *size);
6748d21a622SAndrey Chilikin int save_ddp_package_file(const char *file_path, uint8_t *buf, uint32_t size);
675a92a5a2cSBeilei Xing int close_ddp_package_file(uint8_t *buf);
676a92a5a2cSBeilei Xing 
6773c272b28SWei Zhao void port_queue_region_info_display(portid_t port_id, void *buf);
6783c272b28SWei Zhao 
679edab33b1STetsuya Mukawa enum print_warning {
680edab33b1STetsuya Mukawa 	ENABLED_WARN = 0,
681edab33b1STetsuya Mukawa 	DISABLED_WARN
682edab33b1STetsuya Mukawa };
683edab33b1STetsuya Mukawa int port_id_is_invalid(portid_t port_id, enum print_warning warning);
684c9cafcc8SShahaf Shuler int new_socket_id(unsigned int socket_id);
685edab33b1STetsuya Mukawa 
686af75078fSIntel /*
687af75078fSIntel  * Work-around of a compilation error with ICC on invocations of the
688af75078fSIntel  * rte_be_to_cpu_16() function.
689af75078fSIntel  */
690af75078fSIntel #ifdef __GCC__
691af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  rte_be_to_cpu_16((be_16_v))
692af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v))
693af75078fSIntel #else
69444eb9456SThomas Monjalon #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
695af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  (be_16_v)
696af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v)
697af75078fSIntel #else
698af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \
699af75078fSIntel 	(uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8))
700af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \
701af75078fSIntel 	(uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8))
702af75078fSIntel #endif
703af75078fSIntel #endif /* __GCC__ */
704af75078fSIntel 
705285fd101SOlivier Matz #define TESTPMD_LOG(level, fmt, args...) \
706285fd101SOlivier Matz 	rte_log(RTE_LOG_ ## level, testpmd_logtype, "testpmd: " fmt, ## args)
707285fd101SOlivier Matz 
708af75078fSIntel #endif /* _TESTPMD_H_ */
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