xref: /dpdk/app/test-pmd/testpmd.h (revision fb8fd96d4251f615a0e7acdb3af8b4546f900b4d)
1174a1631SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
2174a1631SBruce Richardson  * Copyright(c) 2010-2017 Intel Corporation
3af75078fSIntel  */
4af75078fSIntel 
5af75078fSIntel #ifndef _TESTPMD_H_
6af75078fSIntel #define _TESTPMD_H_
7af75078fSIntel 
885c18dcbSGaetan Rivet #include <rte_pci.h>
9c752998bSGaetan Rivet #include <rte_bus_pci.h>
10b40f8d78SJiayu Hu #include <rte_gro.h>
1152f38a20SJiayu Hu #include <rte_gso.h>
1285c18dcbSGaetan Rivet 
13ce8d5614SIntel #define RTE_PORT_ALL            (~(portid_t)0x0)
14ce8d5614SIntel 
15ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX    2048
16ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX    2048
17ce8d5614SIntel 
18ce8d5614SIntel #define RTE_PORT_STOPPED        (uint16_t)0
19ce8d5614SIntel #define RTE_PORT_STARTED        (uint16_t)1
20ce8d5614SIntel #define RTE_PORT_CLOSED         (uint16_t)2
21ce8d5614SIntel #define RTE_PORT_HANDLING       (uint16_t)3
22ce8d5614SIntel 
23af75078fSIntel /*
240f6f219eSMohammad Abdul Awal  * It is used to allocate the memory for hash key.
250f6f219eSMohammad Abdul Awal  * The hash key size is NIC dependent.
260f6f219eSMohammad Abdul Awal  */
270f6f219eSMohammad Abdul Awal #define RSS_HASH_KEY_LENGTH 64
280f6f219eSMohammad Abdul Awal 
290f6f219eSMohammad Abdul Awal /*
30af75078fSIntel  * Default size of the mbuf data buffer to receive standard 1518-byte
31af75078fSIntel  * Ethernet frames in a mono-segment memory buffer.
32af75078fSIntel  */
33824cb29cSKonstantin Ananyev #define DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE
34824cb29cSKonstantin Ananyev /**< Default size of mbuf data buffer. */
35af75078fSIntel 
36af75078fSIntel /*
37af75078fSIntel  * The maximum number of segments per packet is used when creating
38af75078fSIntel  * scattered transmit packets composed of a list of mbufs.
39af75078fSIntel  */
40ea672a8bSOlivier Matz #define RTE_MAX_SEGS_PER_PKT 255 /**< nb_segs is a 8-bit unsigned char. */
41af75078fSIntel 
42af75078fSIntel #define MAX_PKT_BURST 512
43836853d3SCunming Liang #define DEF_PKT_BURST 32
44af75078fSIntel 
45e9378bbcSCunming Liang #define DEF_MBUF_CACHE 250
46e9378bbcSCunming Liang 
47fdf20fa7SSergio Gonzalez Monroy #define RTE_CACHE_LINE_SIZE_ROUNDUP(size) \
48fdf20fa7SSergio Gonzalez Monroy 	(RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))
49af75078fSIntel 
50b6ea6408SIntel #define NUMA_NO_CONFIG 0xFF
51b6ea6408SIntel #define UMA_NO_CONFIG  0xFF
52b6ea6408SIntel 
53af75078fSIntel typedef uint8_t  lcoreid_t;
54f8244c63SZhiyong Yang typedef uint16_t portid_t;
55af75078fSIntel typedef uint16_t queueid_t;
56af75078fSIntel typedef uint16_t streamid_t;
57af75078fSIntel 
58af75078fSIntel #define MAX_QUEUE_ID ((1 << (sizeof(queueid_t) * 8)) - 1)
59af75078fSIntel 
605b590fbeSJasvinder Singh #if defined RTE_LIBRTE_PMD_SOFTNIC && defined RTE_LIBRTE_SCHED
615b590fbeSJasvinder Singh #define TM_MODE			1
625b590fbeSJasvinder Singh #else
635b590fbeSJasvinder Singh #define TM_MODE			0
645b590fbeSJasvinder Singh #endif
655b590fbeSJasvinder Singh 
66af75078fSIntel enum {
67af75078fSIntel 	PORT_TOPOLOGY_PAIRED,
683e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_CHAINED,
693e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_LOOP,
70af75078fSIntel };
71af75078fSIntel 
72af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
73af75078fSIntel /**
74af75078fSIntel  * The data structure associated with RX and TX packet burst statistics
75af75078fSIntel  * that are recorded for each forwarding stream.
76af75078fSIntel  */
77af75078fSIntel struct pkt_burst_stats {
78af75078fSIntel 	unsigned int pkt_burst_spread[MAX_PKT_BURST];
79af75078fSIntel };
80af75078fSIntel #endif
81af75078fSIntel 
82f4d623f9SAdrien Mazarguil /** Information for a given RSS type. */
83f4d623f9SAdrien Mazarguil struct rss_type_info {
84f4d623f9SAdrien Mazarguil 	const char *str; /**< Type name. */
85f4d623f9SAdrien Mazarguil 	uint64_t rss_type; /**< Type value. */
86f4d623f9SAdrien Mazarguil };
87f4d623f9SAdrien Mazarguil 
88f4d623f9SAdrien Mazarguil /**
89f4d623f9SAdrien Mazarguil  * RSS type information table.
90f4d623f9SAdrien Mazarguil  *
91f4d623f9SAdrien Mazarguil  * An entry with a NULL type name terminates the list.
92f4d623f9SAdrien Mazarguil  */
93f4d623f9SAdrien Mazarguil extern const struct rss_type_info rss_type_table[];
94f4d623f9SAdrien Mazarguil 
95af75078fSIntel /**
96af75078fSIntel  * The data structure associated with a forwarding stream between a receive
97af75078fSIntel  * port/queue and a transmit port/queue.
98af75078fSIntel  */
99af75078fSIntel struct fwd_stream {
100af75078fSIntel 	/* "read-only" data */
101af75078fSIntel 	portid_t   rx_port;   /**< port to poll for received packets */
102af75078fSIntel 	queueid_t  rx_queue;  /**< RX queue to poll on "rx_port" */
103af75078fSIntel 	portid_t   tx_port;   /**< forwarding port of received packets */
104af75078fSIntel 	queueid_t  tx_queue;  /**< TX queue to send forwarded packets */
105af75078fSIntel 	streamid_t peer_addr; /**< index of peer ethernet address of packets */
106af75078fSIntel 
107bf56fce1SZhihong Wang 	unsigned int retry_enabled;
108bf56fce1SZhihong Wang 
109af75078fSIntel 	/* "read-write" results */
110af75078fSIntel 	unsigned int rx_packets;  /**< received packets */
111af75078fSIntel 	unsigned int tx_packets;  /**< received packets transmitted */
112af75078fSIntel 	unsigned int fwd_dropped; /**< received packets not forwarded */
113af75078fSIntel 	unsigned int rx_bad_ip_csum ; /**< received packets has bad ip checksum */
114af75078fSIntel 	unsigned int rx_bad_l4_csum ; /**< received packets has bad l4 checksum */
115b7091f1dSJiayu Hu 	unsigned int gro_times;	/**< GRO operation times */
116af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
117af75078fSIntel 	uint64_t     core_cycles; /**< used for RX and TX processing */
118af75078fSIntel #endif
119af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
120af75078fSIntel 	struct pkt_burst_stats rx_burst_stats;
121af75078fSIntel 	struct pkt_burst_stats tx_burst_stats;
122af75078fSIntel #endif
123af75078fSIntel };
124af75078fSIntel 
125938a184aSAdrien Mazarguil /** Descriptor for a single flow. */
126938a184aSAdrien Mazarguil struct port_flow {
127938a184aSAdrien Mazarguil 	size_t size; /**< Allocated space including data[]. */
128938a184aSAdrien Mazarguil 	struct port_flow *next; /**< Next flow in list. */
129938a184aSAdrien Mazarguil 	struct port_flow *tmp; /**< Temporary linking. */
130938a184aSAdrien Mazarguil 	uint32_t id; /**< Flow rule ID. */
131938a184aSAdrien Mazarguil 	struct rte_flow *flow; /**< Opaque flow object returned by PMD. */
132938a184aSAdrien Mazarguil 	struct rte_flow_attr attr; /**< Attributes. */
133938a184aSAdrien Mazarguil 	struct rte_flow_item *pattern; /**< Pattern. */
134938a184aSAdrien Mazarguil 	struct rte_flow_action *actions; /**< Actions. */
135938a184aSAdrien Mazarguil 	uint8_t data[]; /**< Storage for pattern/actions. */
136938a184aSAdrien Mazarguil };
137938a184aSAdrien Mazarguil 
1385b590fbeSJasvinder Singh #ifdef TM_MODE
1395b590fbeSJasvinder Singh /**
1405b590fbeSJasvinder Singh  * Soft port tm related parameters
1415b590fbeSJasvinder Singh  */
1425b590fbeSJasvinder Singh struct softnic_port_tm {
1435b590fbeSJasvinder Singh 	uint32_t default_hierarchy_enable; /**< def hierarchy enable flag */
1445b590fbeSJasvinder Singh 	uint32_t hierarchy_config;  /**< set to 1 if hierarchy configured */
1455b590fbeSJasvinder Singh 
1465b590fbeSJasvinder Singh 	uint32_t n_subports_per_port;  /**< Num of subport nodes per port */
1475b590fbeSJasvinder Singh 	uint32_t n_pipes_per_subport;  /**< Num of pipe nodes per subport */
1485b590fbeSJasvinder Singh 
1495b590fbeSJasvinder Singh 	uint64_t tm_pktfield0_slabpos;	/**< Pkt field position for subport */
1505b590fbeSJasvinder Singh 	uint64_t tm_pktfield0_slabmask; /**< Pkt field mask for the subport */
1515b590fbeSJasvinder Singh 	uint64_t tm_pktfield0_slabshr;
1525b590fbeSJasvinder Singh 	uint64_t tm_pktfield1_slabpos; /**< Pkt field position for the pipe */
1535b590fbeSJasvinder Singh 	uint64_t tm_pktfield1_slabmask; /**< Pkt field mask for the pipe */
1545b590fbeSJasvinder Singh 	uint64_t tm_pktfield1_slabshr;
1555b590fbeSJasvinder Singh 	uint64_t tm_pktfield2_slabpos; /**< Pkt field position table index */
1565b590fbeSJasvinder Singh 	uint64_t tm_pktfield2_slabmask;	/**< Pkt field mask for tc table idx */
1575b590fbeSJasvinder Singh 	uint64_t tm_pktfield2_slabshr;
1585b590fbeSJasvinder Singh 	uint64_t tm_tc_table[64];  /**< TC translation table */
1595b590fbeSJasvinder Singh };
1605b590fbeSJasvinder Singh 
1615b590fbeSJasvinder Singh /**
1625b590fbeSJasvinder Singh  * The data structure associate with softnic port
1635b590fbeSJasvinder Singh  */
1645b590fbeSJasvinder Singh struct softnic_port {
1655b590fbeSJasvinder Singh 	unsigned int tm_flag;	/**< set to 1 if tm feature is enabled */
1665b590fbeSJasvinder Singh 	struct softnic_port_tm tm;	/**< softnic port tm parameters */
1675b590fbeSJasvinder Singh };
1685b590fbeSJasvinder Singh #endif
1695b590fbeSJasvinder Singh 
170af75078fSIntel /**
171af75078fSIntel  * The data structure associated with each port.
172af75078fSIntel  */
173af75078fSIntel struct rte_port {
174af75078fSIntel 	struct rte_eth_dev_info dev_info;   /**< PCI info + driver name */
175af75078fSIntel 	struct rte_eth_conf     dev_conf;   /**< Port configuration. */
176af75078fSIntel 	struct ether_addr       eth_addr;   /**< Port ethernet address */
177af75078fSIntel 	struct rte_eth_stats    stats;      /**< Last port statistics */
178af75078fSIntel 	uint64_t                tx_dropped; /**< If no descriptor in TX ring */
179af75078fSIntel 	struct fwd_stream       *rx_stream; /**< Port RX stream, if unique */
180af75078fSIntel 	struct fwd_stream       *tx_stream; /**< Port TX stream, if unique */
181af75078fSIntel 	unsigned int            socket_id;  /**< For NUMA support */
1823eecba26SShahaf Shuler 	uint16_t		parse_tunnel:1; /**< Parse internal headers */
1830f62d635SJianfeng Tan 	uint16_t                tso_segsz;  /**< Segmentation offload MSS for non-tunneled packets. */
1840f62d635SJianfeng Tan 	uint16_t                tunnel_tso_segsz; /**< Segmentation offload MSS for tunneled pkts. */
18592ebda07SHelin Zhang 	uint16_t                tx_vlan_id;/**< The tag ID */
18692ebda07SHelin Zhang 	uint16_t                tx_vlan_id_outer;/**< The outer tag ID */
187af75078fSIntel 	void                    *fwd_ctx;   /**< Forwarding mode context */
188af75078fSIntel 	uint64_t                rx_bad_ip_csum; /**< rx pkts with bad ip checksum  */
189af75078fSIntel 	uint64_t                rx_bad_l4_csum; /**< rx pkts with bad l4 checksum */
190ed30d9b6SIntel 	uint8_t                 tx_queue_stats_mapping_enabled;
191ed30d9b6SIntel 	uint8_t                 rx_queue_stats_mapping_enabled;
192ce8d5614SIntel 	volatile uint16_t        port_status;    /**< port started or not */
193ce8d5614SIntel 	uint8_t                 need_reconfig;  /**< need reconfiguring port or not */
194ce8d5614SIntel 	uint8_t                 need_reconfig_queues; /**< need reconfiguring queues or not */
195ce8d5614SIntel 	uint8_t                 rss_flag;   /**< enable rss or not */
1967741e4cfSIntel 	uint8_t                 dcb_flag;   /**< enable dcb */
197d44f8a48SQi Zhang 	uint16_t                nb_rx_desc[MAX_QUEUE_ID+1]; /**< per queue rx desc number */
198d44f8a48SQi Zhang 	uint16_t                nb_tx_desc[MAX_QUEUE_ID+1]; /**< per queue tx desc number */
199d44f8a48SQi Zhang 	struct rte_eth_rxconf   rx_conf[MAX_QUEUE_ID+1]; /**< per queue rx configuration */
200d44f8a48SQi Zhang 	struct rte_eth_txconf   tx_conf[MAX_QUEUE_ID+1]; /**< per queue tx configuration */
2018fff6675SIvan Boule 	struct ether_addr       *mc_addr_pool; /**< pool of multicast addrs */
2028fff6675SIvan Boule 	uint32_t                mc_addr_nb; /**< nb. of addr. in mc_addr_pool */
20341b05095SBernard Iremonger 	uint8_t                 slave_flag; /**< bonding slave port */
204938a184aSAdrien Mazarguil 	struct port_flow        *flow_list; /**< Associated flows. */
2055b590fbeSJasvinder Singh #ifdef TM_MODE
2065b590fbeSJasvinder Singh 	unsigned int			softnic_enable;	/**< softnic flag */
2075b590fbeSJasvinder Singh 	struct softnic_port     softport;  /**< softnic port params */
2085b590fbeSJasvinder Singh #endif
209af75078fSIntel };
210af75078fSIntel 
211af75078fSIntel /**
212af75078fSIntel  * The data structure associated with each forwarding logical core.
213af75078fSIntel  * The logical cores are internally numbered by a core index from 0 to
214af75078fSIntel  * the maximum number of logical cores - 1.
215af75078fSIntel  * The system CPU identifier of all logical cores are setup in a global
216af75078fSIntel  * CPU id. configuration table.
217af75078fSIntel  */
218af75078fSIntel struct fwd_lcore {
21952f38a20SJiayu Hu 	struct rte_gso_ctx gso_ctx;     /**< GSO context */
220af75078fSIntel 	struct rte_mempool *mbp; /**< The mbuf pool to use by this core */
221b7091f1dSJiayu Hu 	void *gro_ctx;		/**< GRO context */
222af75078fSIntel 	streamid_t stream_idx;   /**< index of 1st stream in "fwd_streams" */
223af75078fSIntel 	streamid_t stream_nb;    /**< number of streams in "fwd_streams" */
224af75078fSIntel 	lcoreid_t  cpuid_idx;    /**< index of logical core in CPU id table */
225af75078fSIntel 	queueid_t  tx_queue;     /**< TX queue to send forwarded packets */
226af75078fSIntel 	volatile char stopped;   /**< stop forwarding when set */
227af75078fSIntel };
228af75078fSIntel 
229af75078fSIntel /*
230af75078fSIntel  * Forwarding mode operations:
231af75078fSIntel  *   - IO forwarding mode (default mode)
232af75078fSIntel  *     Forwards packets unchanged.
233af75078fSIntel  *
234af75078fSIntel  *   - MAC forwarding mode
235af75078fSIntel  *     Set the source and the destination Ethernet addresses of packets
236af75078fSIntel  *     before forwarding them.
237af75078fSIntel  *
238af75078fSIntel  *   - IEEE1588 forwarding mode
239af75078fSIntel  *     Check that received IEEE1588 Precise Time Protocol (PTP) packets are
240af75078fSIntel  *     filtered and timestamped by the hardware.
241af75078fSIntel  *     Forwards packets unchanged on the same port.
242af75078fSIntel  *     Check that sent IEEE1588 PTP packets are timestamped by the hardware.
243af75078fSIntel  */
244af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi);
245af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi);
246af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs);
247af75078fSIntel 
248af75078fSIntel struct fwd_engine {
249af75078fSIntel 	const char       *fwd_mode_name; /**< Forwarding mode name. */
250af75078fSIntel 	port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */
251af75078fSIntel 	port_fwd_end_t   port_fwd_end;   /**< NULL if nothing special to do. */
252af75078fSIntel 	packet_fwd_t     packet_fwd;     /**< Mandatory. */
253af75078fSIntel };
254af75078fSIntel 
255bf56fce1SZhihong Wang #define BURST_TX_WAIT_US 1
256bf56fce1SZhihong Wang #define BURST_TX_RETRIES 64
257bf56fce1SZhihong Wang 
258bf56fce1SZhihong Wang extern uint32_t burst_tx_delay_time;
259bf56fce1SZhihong Wang extern uint32_t burst_tx_retry_num;
260bf56fce1SZhihong Wang 
261af75078fSIntel extern struct fwd_engine io_fwd_engine;
262af75078fSIntel extern struct fwd_engine mac_fwd_engine;
263d47388f1SCyril Chemparathy extern struct fwd_engine mac_swap_engine;
264e9e23a61SCyril Chemparathy extern struct fwd_engine flow_gen_engine;
265af75078fSIntel extern struct fwd_engine rx_only_engine;
266af75078fSIntel extern struct fwd_engine tx_only_engine;
267af75078fSIntel extern struct fwd_engine csum_fwd_engine;
268168dfa61SIvan Boule extern struct fwd_engine icmp_echo_engine;
2695b590fbeSJasvinder Singh #ifdef TM_MODE
2705b590fbeSJasvinder Singh extern struct fwd_engine softnic_tm_engine;
2715b590fbeSJasvinder Singh extern struct fwd_engine softnic_tm_bypass_engine;
2725b590fbeSJasvinder Singh #endif
273af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588
274af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine;
275af75078fSIntel #endif
276af75078fSIntel 
277af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */
278af75078fSIntel 
279af75078fSIntel /**
280af75078fSIntel  * Forwarding Configuration
281af75078fSIntel  *
282af75078fSIntel  */
283af75078fSIntel struct fwd_config {
284af75078fSIntel 	struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */
285af75078fSIntel 	streamid_t nb_fwd_streams;  /**< Nb. of forward streams to process. */
286af75078fSIntel 	lcoreid_t  nb_fwd_lcores;   /**< Nb. of logical cores to launch. */
287af75078fSIntel 	portid_t   nb_fwd_ports;    /**< Nb. of ports involved. */
288af75078fSIntel };
289af75078fSIntel 
290900550deSIntel /**
291900550deSIntel  * DCB mode enable
292900550deSIntel  */
293900550deSIntel enum dcb_mode_enable
294900550deSIntel {
295900550deSIntel 	DCB_VT_ENABLED,
296900550deSIntel 	DCB_ENABLED
297900550deSIntel };
298900550deSIntel 
299ed30d9b6SIntel #define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */
300ed30d9b6SIntel #define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */
301ed30d9b6SIntel 
302ed30d9b6SIntel struct queue_stats_mappings {
303f8244c63SZhiyong Yang 	portid_t port_id;
304ed30d9b6SIntel 	uint16_t queue_id;
305ed30d9b6SIntel 	uint8_t stats_counter_id;
306ed30d9b6SIntel } __rte_cache_aligned;
307ed30d9b6SIntel 
308ed30d9b6SIntel extern struct queue_stats_mappings tx_queue_stats_mappings_array[];
309ed30d9b6SIntel extern struct queue_stats_mappings rx_queue_stats_mappings_array[];
310ed30d9b6SIntel 
311ed30d9b6SIntel /* Assign both tx and rx queue stats mappings to the same default values */
312ed30d9b6SIntel extern struct queue_stats_mappings *tx_queue_stats_mappings;
313ed30d9b6SIntel extern struct queue_stats_mappings *rx_queue_stats_mappings;
314ed30d9b6SIntel 
315ed30d9b6SIntel extern uint16_t nb_tx_queue_stats_mappings;
316ed30d9b6SIntel extern uint16_t nb_rx_queue_stats_mappings;
317ed30d9b6SIntel 
318a4fd5eeeSElza Mathew extern uint8_t xstats_hide_zero; /**< Hide zero values for xstats display */
319a4fd5eeeSElza Mathew 
320af75078fSIntel /* globals used for configuration */
321af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */
322285fd101SOlivier Matz extern int testpmd_logtype; /**< Log type for testpmd logs */
323af75078fSIntel extern uint8_t  interactive;
324ca7feb22SCyril Chemparathy extern uint8_t  auto_start;
32599cabef0SPablo de Lara extern uint8_t  tx_first;
32681ef862bSAllain Legacy extern char cmdline_filename[PATH_MAX]; /**< offline commands file */
327af75078fSIntel extern uint8_t  numa_support; /**< set by "--numa" parameter */
328af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */
3297741e4cfSIntel extern uint8_t no_flush_rx; /**<set by "--no-flush-rx" parameter */
3307ee3e944SVasily Philipov extern uint8_t flow_isolate_all; /**< set by "--flow-isolate-all */
331148f963fSBruce Richardson extern uint8_t  mp_anon; /**< set by "--mp-anon" parameter */
332bc202406SDavid Marchand extern uint8_t no_link_check; /**<set by "--disable-link-check" parameter */
3332950a769SDeclan Doherty extern volatile int test_done; /* stop packet forwarding when set to 1. */
3348ea656f8SGaetan Rivet extern uint8_t lsc_interrupt; /**< disabled by "--no-lsc-interrupt" parameter */
335284c908cSGaetan Rivet extern uint8_t rmv_interrupt; /**< disabled by "--no-rmv-interrupt" parameter */
3363af72783SGaetan Rivet extern uint32_t event_print_mask;
337fb73e096SJeff Guo extern uint8_t hot_plug; /**< enable by "--hot-plug" parameter */
338fb73e096SJeff Guo 
3393af72783SGaetan Rivet /**< set by "--print-event xxxx" and "--mask-event xxxx parameters */
340af75078fSIntel 
341e261265eSRadu Nicolau #ifdef RTE_LIBRTE_IXGBE_BYPASS
3427b7e5ba7SIntel extern uint32_t bypass_timeout; /**< Store the NIC bypass watchdog timeout */
3437b7e5ba7SIntel #endif
3447b7e5ba7SIntel 
345b6ea6408SIntel /*
346b6ea6408SIntel  * Store specified sockets on which memory pool to be used by ports
347b6ea6408SIntel  * is allocated.
348b6ea6408SIntel  */
34963531389SGeorgios Katsikas extern uint8_t port_numa[RTE_MAX_ETHPORTS];
350b6ea6408SIntel 
351b6ea6408SIntel /*
352b6ea6408SIntel  * Store specified sockets on which RX ring to be used by ports
353b6ea6408SIntel  * is allocated.
354b6ea6408SIntel  */
35563531389SGeorgios Katsikas extern uint8_t rxring_numa[RTE_MAX_ETHPORTS];
356b6ea6408SIntel 
357b6ea6408SIntel /*
358b6ea6408SIntel  * Store specified sockets on which TX ring to be used by ports
359b6ea6408SIntel  * is allocated.
360b6ea6408SIntel  */
36163531389SGeorgios Katsikas extern uint8_t txring_numa[RTE_MAX_ETHPORTS];
362b6ea6408SIntel 
363b6ea6408SIntel extern uint8_t socket_num;
364b6ea6408SIntel 
365af75078fSIntel /*
366af75078fSIntel  * Configuration of logical cores:
367af75078fSIntel  * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores
368af75078fSIntel  */
369af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */
370af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */
371af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */
372af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE];
373c9cafcc8SShahaf Shuler extern unsigned int num_sockets;
374c9cafcc8SShahaf Shuler extern unsigned int socket_ids[RTE_MAX_NUMA_NODES];
375af75078fSIntel 
376af75078fSIntel /*
377af75078fSIntel  * Configuration of Ethernet ports:
378af75078fSIntel  * nb_fwd_ports <= nb_cfg_ports <= nb_ports
379af75078fSIntel  */
380af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */
381af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */
382af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */
383af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS];
384af75078fSIntel extern struct rte_port *ports;
385af75078fSIntel 
386af75078fSIntel extern struct rte_eth_rxmode rx_mode;
387fd8c20aaSShahaf Shuler extern struct rte_eth_txmode tx_mode;
388fd8c20aaSShahaf Shuler 
3898a387fa8SHelin Zhang extern uint64_t rss_hf;
390af75078fSIntel 
391af75078fSIntel extern queueid_t nb_rxq;
392af75078fSIntel extern queueid_t nb_txq;
393af75078fSIntel 
394af75078fSIntel extern uint16_t nb_rxd;
395af75078fSIntel extern uint16_t nb_txd;
396af75078fSIntel 
397f2c5125aSPablo de Lara extern int16_t rx_free_thresh;
398f2c5125aSPablo de Lara extern int8_t rx_drop_en;
399f2c5125aSPablo de Lara extern int16_t tx_free_thresh;
400f2c5125aSPablo de Lara extern int16_t tx_rs_thresh;
401af75078fSIntel 
402900550deSIntel extern uint8_t dcb_config;
403900550deSIntel extern uint8_t dcb_test;
404900550deSIntel 
405af75078fSIntel extern uint16_t mbuf_data_size; /**< Mbuf data space size. */
406c8798818SIntel extern uint32_t param_total_num_mbufs;
407af75078fSIntel 
408cfea1f30SPablo de Lara extern uint16_t stats_period;
40962d3216dSReshma Pattan 
41062d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS
41162d3216dSReshma Pattan extern uint8_t latencystats_enabled;
41262d3216dSReshma Pattan extern lcoreid_t latencystats_lcore_id;
41362d3216dSReshma Pattan #endif
41462d3216dSReshma Pattan 
415e25e6c70SRemy Horton #ifdef RTE_LIBRTE_BITRATE
416e25e6c70SRemy Horton extern lcoreid_t bitrate_lcore_id;
417e25e6c70SRemy Horton extern uint8_t bitrate_enabled;
418e25e6c70SRemy Horton #endif
419e25e6c70SRemy Horton 
420af75078fSIntel extern struct rte_fdir_conf fdir_conf;
421af75078fSIntel 
422af75078fSIntel /*
423af75078fSIntel  * Configuration of packet segments used by the "txonly" processing engine.
424af75078fSIntel  */
425af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64
426af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */
427af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */
428af75078fSIntel extern uint8_t  tx_pkt_nb_segs; /**< Number of segments in TX packets */
429af75078fSIntel 
43079bec05bSKonstantin Ananyev enum tx_pkt_split {
43179bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_OFF,
43279bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_ON,
43379bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_RND,
43479bec05bSKonstantin Ananyev };
43579bec05bSKonstantin Ananyev 
43679bec05bSKonstantin Ananyev extern enum tx_pkt_split tx_pkt_split;
43779bec05bSKonstantin Ananyev 
438af75078fSIntel extern uint16_t nb_pkt_per_burst;
439af75078fSIntel extern uint16_t mb_mempool_cache;
440f2c5125aSPablo de Lara extern int8_t rx_pthresh;
441f2c5125aSPablo de Lara extern int8_t rx_hthresh;
442f2c5125aSPablo de Lara extern int8_t rx_wthresh;
443f2c5125aSPablo de Lara extern int8_t tx_pthresh;
444f2c5125aSPablo de Lara extern int8_t tx_hthresh;
445f2c5125aSPablo de Lara extern int8_t tx_wthresh;
446af75078fSIntel 
447af75078fSIntel extern struct fwd_config cur_fwd_config;
448af75078fSIntel extern struct fwd_engine *cur_fwd_eng;
449bf56fce1SZhihong Wang extern uint32_t retry_enabled;
450af75078fSIntel extern struct fwd_lcore  **fwd_lcores;
451af75078fSIntel extern struct fwd_stream **fwd_streams;
452af75078fSIntel 
45339e5e20fSXueming Li extern uint16_t vxlan_gpe_udp_port; /**< UDP port of tunnel VXLAN-GPE. */
45439e5e20fSXueming Li 
455af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */
456af75078fSIntel extern struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS];
457af75078fSIntel 
45857e85242SBruce Richardson extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */
45957e85242SBruce Richardson extern uint32_t burst_tx_retry_num;  /**< Burst tx retry number for mac-retry. */
46057e85242SBruce Richardson 
461b7091f1dSJiayu Hu #define GRO_DEFAULT_ITEM_NUM_PER_FLOW 32
462b7091f1dSJiayu Hu #define GRO_DEFAULT_FLOW_NUM (RTE_GRO_MAX_BURST_ITEM_NUM / \
463b7091f1dSJiayu Hu 		GRO_DEFAULT_ITEM_NUM_PER_FLOW)
464b7091f1dSJiayu Hu 
465b7091f1dSJiayu Hu #define GRO_DEFAULT_FLUSH_CYCLES 1
466b7091f1dSJiayu Hu #define GRO_MAX_FLUSH_CYCLES 4
467b7091f1dSJiayu Hu 
468b40f8d78SJiayu Hu struct gro_status {
469b40f8d78SJiayu Hu 	struct rte_gro_param param;
470b40f8d78SJiayu Hu 	uint8_t enable;
471b40f8d78SJiayu Hu };
472b40f8d78SJiayu Hu extern struct gro_status gro_ports[RTE_MAX_ETHPORTS];
473b7091f1dSJiayu Hu extern uint8_t gro_flush_cycles;
474b40f8d78SJiayu Hu 
47552f38a20SJiayu Hu #define GSO_MAX_PKT_BURST 2048
47652f38a20SJiayu Hu struct gso_status {
47752f38a20SJiayu Hu 	uint8_t enable;
47852f38a20SJiayu Hu };
47952f38a20SJiayu Hu extern struct gso_status gso_ports[RTE_MAX_ETHPORTS];
48052f38a20SJiayu Hu extern uint16_t gso_max_segment_size;
48152f38a20SJiayu Hu 
482af75078fSIntel static inline unsigned int
483af75078fSIntel lcore_num(void)
484af75078fSIntel {
485af75078fSIntel 	unsigned int i;
486af75078fSIntel 
487af75078fSIntel 	for (i = 0; i < RTE_MAX_LCORE; ++i)
488af75078fSIntel 		if (fwd_lcores_cpuids[i] == rte_lcore_id())
489af75078fSIntel 			return i;
490af75078fSIntel 
491af75078fSIntel 	rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n");
492af75078fSIntel }
493af75078fSIntel 
494af75078fSIntel static inline struct fwd_lcore *
495af75078fSIntel current_fwd_lcore(void)
496af75078fSIntel {
497af75078fSIntel 	return fwd_lcores[lcore_num()];
498af75078fSIntel }
499af75078fSIntel 
500af75078fSIntel /* Mbuf Pools */
501af75078fSIntel static inline void
502af75078fSIntel mbuf_poolname_build(unsigned int sock_id, char* mp_name, int name_size)
503af75078fSIntel {
5046f41fe75SStephen Hemminger 	snprintf(mp_name, name_size, "mbuf_pool_socket_%u", sock_id);
505af75078fSIntel }
506af75078fSIntel 
507af75078fSIntel static inline struct rte_mempool *
508af75078fSIntel mbuf_pool_find(unsigned int sock_id)
509af75078fSIntel {
510af75078fSIntel 	char pool_name[RTE_MEMPOOL_NAMESIZE];
511af75078fSIntel 
512af75078fSIntel 	mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name));
513693f715dSHuawei Xie 	return rte_mempool_lookup((const char *)pool_name);
514af75078fSIntel }
515af75078fSIntel 
516af75078fSIntel /**
517af75078fSIntel  * Read/Write operations on a PCI register of a port.
518af75078fSIntel  */
519af75078fSIntel static inline uint32_t
520af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off)
521af75078fSIntel {
522cd8c7c7cSFerruh Yigit 	const struct rte_pci_device *pci_dev;
523cd8c7c7cSFerruh Yigit 	const struct rte_bus *bus;
524af75078fSIntel 	void *reg_addr;
525af75078fSIntel 	uint32_t reg_v;
526af75078fSIntel 
527cd8c7c7cSFerruh Yigit 	if (!port->dev_info.device) {
528cd8c7c7cSFerruh Yigit 		printf("Invalid device\n");
529cd8c7c7cSFerruh Yigit 		return 0;
530cd8c7c7cSFerruh Yigit 	}
531cd8c7c7cSFerruh Yigit 
532cd8c7c7cSFerruh Yigit 	bus = rte_bus_find_by_device(port->dev_info.device);
533cd8c7c7cSFerruh Yigit 	if (bus && !strcmp(bus->name, "pci")) {
534cd8c7c7cSFerruh Yigit 		pci_dev = RTE_DEV_TO_PCI(port->dev_info.device);
535cd8c7c7cSFerruh Yigit 	} else {
536cd8c7c7cSFerruh Yigit 		printf("Not a PCI device\n");
537cd8c7c7cSFerruh Yigit 		return 0;
538cd8c7c7cSFerruh Yigit 	}
539cd8c7c7cSFerruh Yigit 
540cd8c7c7cSFerruh Yigit 	reg_addr = ((char *)pci_dev->mem_resource[0].addr + reg_off);
541af75078fSIntel 	reg_v = *((volatile uint32_t *)reg_addr);
542af75078fSIntel 	return rte_le_to_cpu_32(reg_v);
543af75078fSIntel }
544af75078fSIntel 
545af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \
546af75078fSIntel 	port_pci_reg_read(&ports[(pt_id)], (reg_off))
547af75078fSIntel 
548af75078fSIntel static inline void
549af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v)
550af75078fSIntel {
551cd8c7c7cSFerruh Yigit 	const struct rte_pci_device *pci_dev;
552cd8c7c7cSFerruh Yigit 	const struct rte_bus *bus;
553af75078fSIntel 	void *reg_addr;
554af75078fSIntel 
555cd8c7c7cSFerruh Yigit 	if (!port->dev_info.device) {
556cd8c7c7cSFerruh Yigit 		printf("Invalid device\n");
557cd8c7c7cSFerruh Yigit 		return;
558cd8c7c7cSFerruh Yigit 	}
559cd8c7c7cSFerruh Yigit 
560cd8c7c7cSFerruh Yigit 	bus = rte_bus_find_by_device(port->dev_info.device);
561cd8c7c7cSFerruh Yigit 	if (bus && !strcmp(bus->name, "pci")) {
562cd8c7c7cSFerruh Yigit 		pci_dev = RTE_DEV_TO_PCI(port->dev_info.device);
563cd8c7c7cSFerruh Yigit 	} else {
564cd8c7c7cSFerruh Yigit 		printf("Not a PCI device\n");
565cd8c7c7cSFerruh Yigit 		return;
566cd8c7c7cSFerruh Yigit 	}
567cd8c7c7cSFerruh Yigit 
568cd8c7c7cSFerruh Yigit 	reg_addr = ((char *)pci_dev->mem_resource[0].addr + reg_off);
569af75078fSIntel 	*((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v);
570af75078fSIntel }
571af75078fSIntel 
572af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \
573af75078fSIntel 	port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value))
574af75078fSIntel 
575af75078fSIntel /* Prototypes */
576950d1516SBruce Richardson unsigned int parse_item_list(char* str, const char* item_name,
577950d1516SBruce Richardson 			unsigned int max_items,
578950d1516SBruce Richardson 			unsigned int *parsed_items, int check_unique_values);
579af75078fSIntel void launch_args_parse(int argc, char** argv);
58081ef862bSAllain Legacy void cmdline_read_from_file(const char *filename);
581af75078fSIntel void prompt(void);
582d3a274ceSZhihong Wang void prompt_exit(void);
583af75078fSIntel void nic_stats_display(portid_t port_id);
584af75078fSIntel void nic_stats_clear(portid_t port_id);
585bfd5051bSOlivier Matz void nic_xstats_display(portid_t port_id);
586bfd5051bSOlivier Matz void nic_xstats_clear(portid_t port_id);
587ed30d9b6SIntel void nic_stats_mapping_display(portid_t port_id);
588af75078fSIntel void port_infos_display(portid_t port_id);
589d28645c7SQiming Yang void port_offload_cap_display(portid_t port_id);
590ab3257e1SKonstantin Ananyev void rx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
591ab3257e1SKonstantin Ananyev void tx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
592af75078fSIntel void fwd_lcores_config_display(void);
5930c0db76fSBernard Iremonger void pkt_fwd_config_display(struct fwd_config *cfg);
594af75078fSIntel void rxtx_config_display(void);
595af75078fSIntel void fwd_config_setup(void);
596af75078fSIntel void set_def_fwd_config(void);
597a21d5a4bSDeclan Doherty void reconfig(portid_t new_port_id, unsigned socket_id);
598013af9b6SIntel int init_fwd_streams(void);
599013af9b6SIntel 
600aac6f11fSWisam Jaddo void set_fwd_eth_peer(portid_t port_id, char *peer_addr);
601aac6f11fSWisam Jaddo 
602ae03d0d1SIvan Boule void port_mtu_set(portid_t port_id, uint16_t mtu);
603af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos);
604af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos,
605af75078fSIntel 		      uint8_t bit_v);
606af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off,
607af75078fSIntel 				uint8_t bit1_pos, uint8_t bit2_pos);
608af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off,
609af75078fSIntel 			    uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value);
610af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off);
611af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value);
612938a184aSAdrien Mazarguil int port_flow_validate(portid_t port_id,
613938a184aSAdrien Mazarguil 		       const struct rte_flow_attr *attr,
614938a184aSAdrien Mazarguil 		       const struct rte_flow_item *pattern,
615938a184aSAdrien Mazarguil 		       const struct rte_flow_action *actions);
616938a184aSAdrien Mazarguil int port_flow_create(portid_t port_id,
617938a184aSAdrien Mazarguil 		     const struct rte_flow_attr *attr,
618938a184aSAdrien Mazarguil 		     const struct rte_flow_item *pattern,
619938a184aSAdrien Mazarguil 		     const struct rte_flow_action *actions);
620938a184aSAdrien Mazarguil int port_flow_destroy(portid_t port_id, uint32_t n, const uint32_t *rule);
621938a184aSAdrien Mazarguil int port_flow_flush(portid_t port_id);
622938a184aSAdrien Mazarguil int port_flow_query(portid_t port_id, uint32_t rule,
623*fb8fd96dSDeclan Doherty 		    const struct rte_flow_action *action);
624938a184aSAdrien Mazarguil void port_flow_list(portid_t port_id, uint32_t n, const uint32_t *group);
625323f811aSAdrien Mazarguil int port_flow_isolate(portid_t port_id, int set);
626af75078fSIntel 
627af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id);
628af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id);
629af75078fSIntel 
630013af9b6SIntel int set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc);
631013af9b6SIntel int set_fwd_lcores_mask(uint64_t lcoremask);
632af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc);
633af75078fSIntel 
634af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt);
635af75078fSIntel void set_fwd_ports_mask(uint64_t portmask);
636af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt);
637a8ef3e3aSBernard Iremonger int port_is_forwarding(portid_t port_id);
638af75078fSIntel 
639a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on);
640a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on);
641a47aa8b9SIntel 
642a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on);
643af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on);
64464b01ee0SMichal Jastrzebski int rx_vft_set(portid_t port_id, uint16_t vlan_id, int on);
645a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on);
64619b16e2fSHelin Zhang void vlan_tpid_set(portid_t port_id, enum rte_vlan_type vlan_type,
64719b16e2fSHelin Zhang 		   uint16_t tp_id);
648af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id);
64992ebda07SHelin Zhang void tx_qinq_set(portid_t port_id, uint16_t vlan_id, uint16_t vlan_id_outer);
650af75078fSIntel void tx_vlan_reset(portid_t port_id);
651529ba951SHelin Zhang void tx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on);
652ed30d9b6SIntel 
653ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value);
654ed30d9b6SIntel 
655a4fd5eeeSElza Mathew void set_xstats_hide_zero(uint8_t on_off);
656a4fd5eeeSElza Mathew 
657af75078fSIntel void set_verbose_level(uint16_t vb_level);
658af75078fSIntel void set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs);
65979bec05bSKonstantin Ananyev void show_tx_pkt_segments(void);
66079bec05bSKonstantin Ananyev void set_tx_pkt_split(const char *name);
661af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst);
662769ce6b1SThomas Monjalon char *list_pkt_forwarding_modes(void);
663bf56fce1SZhihong Wang char *list_pkt_forwarding_retry_modes(void);
664af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode);
665af75078fSIntel void start_packet_forwarding(int with_tx_first);
666af75078fSIntel void stop_packet_forwarding(void);
667cfae07fdSOuyang Changchun void dev_set_link_up(portid_t pid);
668cfae07fdSOuyang Changchun void dev_set_link_down(portid_t pid);
669ce8d5614SIntel void init_port_config(void);
67041b05095SBernard Iremonger void set_port_slave_flag(portid_t slave_pid);
67141b05095SBernard Iremonger void clear_port_slave_flag(portid_t slave_pid);
6720e545d30SBernard Iremonger uint8_t port_is_bonding_slave(portid_t slave_pid);
6730e545d30SBernard Iremonger 
6741a572499SJingjing Wu int init_port_dcb_config(portid_t pid, enum dcb_mode_enable dcb_mode,
6751a572499SJingjing Wu 		     enum rte_eth_nb_tcs num_tcs,
6761a572499SJingjing Wu 		     uint8_t pfc_en);
677148f963fSBruce Richardson int start_port(portid_t pid);
678ce8d5614SIntel void stop_port(portid_t pid);
679ce8d5614SIntel void close_port(portid_t pid);
68097f1e196SWei Dai void reset_port(portid_t pid);
681edab33b1STetsuya Mukawa void attach_port(char *identifier);
68228caa76aSZhiyong Yang void detach_port(portid_t port_id);
683ce8d5614SIntel int all_ports_stopped(void);
6846018eb8cSShahaf Shuler int port_is_stopped(portid_t port_id);
6855f4ec54fSChen Jing D(Mark) int port_is_started(portid_t port_id);
686af75078fSIntel void pmd_test_exit(void);
687af75078fSIntel void fdir_get_infos(portid_t port_id);
688aeca06dfSJingjing Wu void fdir_set_flex_mask(portid_t port_id,
689aeca06dfSJingjing Wu 			   struct rte_eth_fdir_flex_mask *cfg);
69097b74464SJingjing Wu void fdir_set_flex_payload(portid_t port_id,
69197b74464SJingjing Wu 			   struct rte_eth_flex_payload_cfg *cfg);
69266c59490SHelin Zhang void port_rss_reta_info(portid_t port_id,
69366c59490SHelin Zhang 			struct rte_eth_rss_reta_entry64 *reta_conf,
69466c59490SHelin Zhang 			uint16_t nb_entries);
6956a18e1afSOuyang Changchun 
6967741e4cfSIntel void set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on);
697af75078fSIntel 
6986a18e1afSOuyang Changchun int set_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate);
6996a18e1afSOuyang Changchun int set_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate,
7006a18e1afSOuyang Changchun 				uint64_t q_msk);
7016a18e1afSOuyang Changchun 
7028205e241SNelio Laranjeiro void port_rss_hash_conf_show(portid_t port_id, char rss_info[],
7038205e241SNelio Laranjeiro 			     int show_rss_key);
7048205e241SNelio Laranjeiro void port_rss_hash_key_update(portid_t port_id, char rss_type[],
7058205e241SNelio Laranjeiro 			      uint8_t *hash_key, uint hash_key_len);
7065f4ec54fSChen Jing D(Mark) int rx_queue_id_is_invalid(queueid_t rxq_id);
7075f4ec54fSChen Jing D(Mark) int tx_queue_id_is_invalid(queueid_t txq_id);
708b7091f1dSJiayu Hu void setup_gro(const char *onoff, portid_t port_id);
709b7091f1dSJiayu Hu void setup_gro_flush_cycles(uint8_t cycles);
710b7091f1dSJiayu Hu void show_gro(portid_t port_id);
71152f38a20SJiayu Hu void setup_gso(const char *mode, portid_t port_id);
71216321de0SIvan Boule 
7138fff6675SIvan Boule /* Functions to manage the set of filtered Multicast MAC addresses */
71428caa76aSZhiyong Yang void mcast_addr_add(portid_t port_id, struct ether_addr *mc_addr);
71528caa76aSZhiyong Yang void mcast_addr_remove(portid_t port_id, struct ether_addr *mc_addr);
71628caa76aSZhiyong Yang void port_dcb_info_display(portid_t port_id);
7178fff6675SIvan Boule 
7189999dc6fSKirill Rybalchenko uint8_t *open_file(const char *file_path, uint32_t *size);
7199999dc6fSKirill Rybalchenko int save_file(const char *file_path, uint8_t *buf, uint32_t size);
7209999dc6fSKirill Rybalchenko int close_file(uint8_t *buf);
721a92a5a2cSBeilei Xing 
7223c272b28SWei Zhao void port_queue_region_info_display(portid_t port_id, void *buf);
7233c272b28SWei Zhao 
724edab33b1STetsuya Mukawa enum print_warning {
725edab33b1STetsuya Mukawa 	ENABLED_WARN = 0,
726edab33b1STetsuya Mukawa 	DISABLED_WARN
727edab33b1STetsuya Mukawa };
728edab33b1STetsuya Mukawa int port_id_is_invalid(portid_t port_id, enum print_warning warning);
729c9cafcc8SShahaf Shuler int new_socket_id(unsigned int socket_id);
730edab33b1STetsuya Mukawa 
7313f7311baSWei Dai queueid_t get_allowed_max_nb_rxq(portid_t *pid);
7323f7311baSWei Dai int check_nb_rxq(queueid_t rxq);
73336db4f6cSWei Dai queueid_t get_allowed_max_nb_txq(portid_t *pid);
73436db4f6cSWei Dai int check_nb_txq(queueid_t txq);
7353f7311baSWei Dai 
736af75078fSIntel /*
737af75078fSIntel  * Work-around of a compilation error with ICC on invocations of the
738af75078fSIntel  * rte_be_to_cpu_16() function.
739af75078fSIntel  */
740af75078fSIntel #ifdef __GCC__
741af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  rte_be_to_cpu_16((be_16_v))
742af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v))
743af75078fSIntel #else
74444eb9456SThomas Monjalon #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
745af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  (be_16_v)
746af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v)
747af75078fSIntel #else
748af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \
749af75078fSIntel 	(uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8))
750af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \
751af75078fSIntel 	(uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8))
752af75078fSIntel #endif
753af75078fSIntel #endif /* __GCC__ */
754af75078fSIntel 
755285fd101SOlivier Matz #define TESTPMD_LOG(level, fmt, args...) \
756285fd101SOlivier Matz 	rte_log(RTE_LOG_ ## level, testpmd_logtype, "testpmd: " fmt, ## args)
757285fd101SOlivier Matz 
758af75078fSIntel #endif /* _TESTPMD_H_ */
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