xref: /dpdk/app/test-pmd/testpmd.h (revision cfea1f3048d1bfda61036e6f823949fba4d692d4)
1af75078fSIntel /*-
2af75078fSIntel  *   BSD LICENSE
3af75078fSIntel  *
462d3216dSReshma Pattan  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
5af75078fSIntel  *   All rights reserved.
6af75078fSIntel  *
7af75078fSIntel  *   Redistribution and use in source and binary forms, with or without
8af75078fSIntel  *   modification, are permitted provided that the following conditions
9af75078fSIntel  *   are met:
10af75078fSIntel  *
11af75078fSIntel  *     * Redistributions of source code must retain the above copyright
12af75078fSIntel  *       notice, this list of conditions and the following disclaimer.
13af75078fSIntel  *     * Redistributions in binary form must reproduce the above copyright
14af75078fSIntel  *       notice, this list of conditions and the following disclaimer in
15af75078fSIntel  *       the documentation and/or other materials provided with the
16af75078fSIntel  *       distribution.
17af75078fSIntel  *     * Neither the name of Intel Corporation nor the names of its
18af75078fSIntel  *       contributors may be used to endorse or promote products derived
19af75078fSIntel  *       from this software without specific prior written permission.
20af75078fSIntel  *
21af75078fSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22af75078fSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23af75078fSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24af75078fSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25af75078fSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26af75078fSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27af75078fSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28af75078fSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29af75078fSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30af75078fSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31af75078fSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32af75078fSIntel  */
33af75078fSIntel 
34af75078fSIntel #ifndef _TESTPMD_H_
35af75078fSIntel #define _TESTPMD_H_
36af75078fSIntel 
37ce8d5614SIntel #define RTE_PORT_ALL            (~(portid_t)0x0)
38ce8d5614SIntel 
39ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX    2048
40ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX    2048
41ce8d5614SIntel 
42ce8d5614SIntel #define RTE_PORT_STOPPED        (uint16_t)0
43ce8d5614SIntel #define RTE_PORT_STARTED        (uint16_t)1
44ce8d5614SIntel #define RTE_PORT_CLOSED         (uint16_t)2
45ce8d5614SIntel #define RTE_PORT_HANDLING       (uint16_t)3
46ce8d5614SIntel 
47af75078fSIntel /*
480f6f219eSMohammad Abdul Awal  * It is used to allocate the memory for hash key.
490f6f219eSMohammad Abdul Awal  * The hash key size is NIC dependent.
500f6f219eSMohammad Abdul Awal  */
510f6f219eSMohammad Abdul Awal #define RSS_HASH_KEY_LENGTH 64
520f6f219eSMohammad Abdul Awal 
530f6f219eSMohammad Abdul Awal /*
54af75078fSIntel  * Default size of the mbuf data buffer to receive standard 1518-byte
55af75078fSIntel  * Ethernet frames in a mono-segment memory buffer.
56af75078fSIntel  */
57824cb29cSKonstantin Ananyev #define DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE
58824cb29cSKonstantin Ananyev /**< Default size of mbuf data buffer. */
59af75078fSIntel 
60af75078fSIntel /*
61af75078fSIntel  * The maximum number of segments per packet is used when creating
62af75078fSIntel  * scattered transmit packets composed of a list of mbufs.
63af75078fSIntel  */
64ea672a8bSOlivier Matz #define RTE_MAX_SEGS_PER_PKT 255 /**< nb_segs is a 8-bit unsigned char. */
65af75078fSIntel 
66af75078fSIntel #define MAX_PKT_BURST 512
67836853d3SCunming Liang #define DEF_PKT_BURST 32
68af75078fSIntel 
69e9378bbcSCunming Liang #define DEF_MBUF_CACHE 250
70e9378bbcSCunming Liang 
71fdf20fa7SSergio Gonzalez Monroy #define RTE_CACHE_LINE_SIZE_ROUNDUP(size) \
72fdf20fa7SSergio Gonzalez Monroy 	(RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))
73af75078fSIntel 
74b6ea6408SIntel #define NUMA_NO_CONFIG 0xFF
75b6ea6408SIntel #define UMA_NO_CONFIG  0xFF
76b6ea6408SIntel 
77af75078fSIntel typedef uint8_t  lcoreid_t;
78af75078fSIntel typedef uint8_t  portid_t;
79af75078fSIntel typedef uint16_t queueid_t;
80af75078fSIntel typedef uint16_t streamid_t;
81af75078fSIntel 
82af75078fSIntel #define MAX_QUEUE_ID ((1 << (sizeof(queueid_t) * 8)) - 1)
83af75078fSIntel 
84af75078fSIntel enum {
85af75078fSIntel 	PORT_TOPOLOGY_PAIRED,
863e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_CHAINED,
873e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_LOOP,
88af75078fSIntel };
89af75078fSIntel 
90af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
91af75078fSIntel /**
92af75078fSIntel  * The data structure associated with RX and TX packet burst statistics
93af75078fSIntel  * that are recorded for each forwarding stream.
94af75078fSIntel  */
95af75078fSIntel struct pkt_burst_stats {
96af75078fSIntel 	unsigned int pkt_burst_spread[MAX_PKT_BURST];
97af75078fSIntel };
98af75078fSIntel #endif
99af75078fSIntel 
100af75078fSIntel /**
101af75078fSIntel  * The data structure associated with a forwarding stream between a receive
102af75078fSIntel  * port/queue and a transmit port/queue.
103af75078fSIntel  */
104af75078fSIntel struct fwd_stream {
105af75078fSIntel 	/* "read-only" data */
106af75078fSIntel 	portid_t   rx_port;   /**< port to poll for received packets */
107af75078fSIntel 	queueid_t  rx_queue;  /**< RX queue to poll on "rx_port" */
108af75078fSIntel 	portid_t   tx_port;   /**< forwarding port of received packets */
109af75078fSIntel 	queueid_t  tx_queue;  /**< TX queue to send forwarded packets */
110af75078fSIntel 	streamid_t peer_addr; /**< index of peer ethernet address of packets */
111af75078fSIntel 
112bf56fce1SZhihong Wang 	unsigned int retry_enabled;
113bf56fce1SZhihong Wang 
114af75078fSIntel 	/* "read-write" results */
115af75078fSIntel 	unsigned int rx_packets;  /**< received packets */
116af75078fSIntel 	unsigned int tx_packets;  /**< received packets transmitted */
117af75078fSIntel 	unsigned int fwd_dropped; /**< received packets not forwarded */
118af75078fSIntel 	unsigned int rx_bad_ip_csum ; /**< received packets has bad ip checksum */
119af75078fSIntel 	unsigned int rx_bad_l4_csum ; /**< received packets has bad l4 checksum */
120af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
121af75078fSIntel 	uint64_t     core_cycles; /**< used for RX and TX processing */
122af75078fSIntel #endif
123af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
124af75078fSIntel 	struct pkt_burst_stats rx_burst_stats;
125af75078fSIntel 	struct pkt_burst_stats tx_burst_stats;
126af75078fSIntel #endif
127af75078fSIntel };
128af75078fSIntel 
129cf543fdbSOlivier Matz /** Offload IP checksum in csum forward engine */
130cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_IP_CKSUM          0x0001
131cf543fdbSOlivier Matz /** Offload UDP checksum in csum forward engine */
132cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_UDP_CKSUM         0x0002
133cf543fdbSOlivier Matz /** Offload TCP checksum in csum forward engine */
134cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_TCP_CKSUM         0x0004
135cf543fdbSOlivier Matz /** Offload SCTP checksum in csum forward engine */
136cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_SCTP_CKSUM        0x0008
1373994a3e8SOlivier Matz /** Offload outer IP checksum in csum forward engine for recognized tunnels */
1383994a3e8SOlivier Matz #define TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM    0x0010
13964fc3606SOlivier Matz /** Parse tunnel in csum forward engine. If set, dissect tunnel headers
14064fc3606SOlivier Matz  * of rx packets. If not set, treat inner headers as payload. */
14164fc3606SOlivier Matz #define TESTPMD_TX_OFFLOAD_PARSE_TUNNEL      0x0020
142cf543fdbSOlivier Matz /** Insert VLAN header in forward engine */
14364fc3606SOlivier Matz #define TESTPMD_TX_OFFLOAD_INSERT_VLAN       0x0040
14492ebda07SHelin Zhang /** Insert double VLAN header in forward engine */
14592ebda07SHelin Zhang #define TESTPMD_TX_OFFLOAD_INSERT_QINQ       0x0080
146bb98856fSTiwei Bie /** Offload MACsec in forward engine */
147bb98856fSTiwei Bie #define TESTPMD_TX_OFFLOAD_MACSEC            0x0100
14851f694ddSOlivier Matz 
149938a184aSAdrien Mazarguil /** Descriptor for a single flow. */
150938a184aSAdrien Mazarguil struct port_flow {
151938a184aSAdrien Mazarguil 	size_t size; /**< Allocated space including data[]. */
152938a184aSAdrien Mazarguil 	struct port_flow *next; /**< Next flow in list. */
153938a184aSAdrien Mazarguil 	struct port_flow *tmp; /**< Temporary linking. */
154938a184aSAdrien Mazarguil 	uint32_t id; /**< Flow rule ID. */
155938a184aSAdrien Mazarguil 	struct rte_flow *flow; /**< Opaque flow object returned by PMD. */
156938a184aSAdrien Mazarguil 	struct rte_flow_attr attr; /**< Attributes. */
157938a184aSAdrien Mazarguil 	struct rte_flow_item *pattern; /**< Pattern. */
158938a184aSAdrien Mazarguil 	struct rte_flow_action *actions; /**< Actions. */
159938a184aSAdrien Mazarguil 	uint8_t data[]; /**< Storage for pattern/actions. */
160938a184aSAdrien Mazarguil };
161938a184aSAdrien Mazarguil 
162af75078fSIntel /**
163af75078fSIntel  * The data structure associated with each port.
164af75078fSIntel  */
165af75078fSIntel struct rte_port {
166af75078fSIntel 	struct rte_eth_dev_info dev_info;   /**< PCI info + driver name */
167af75078fSIntel 	struct rte_eth_conf     dev_conf;   /**< Port configuration. */
168af75078fSIntel 	struct ether_addr       eth_addr;   /**< Port ethernet address */
169af75078fSIntel 	struct rte_eth_stats    stats;      /**< Last port statistics */
170af75078fSIntel 	uint64_t                tx_dropped; /**< If no descriptor in TX ring */
171af75078fSIntel 	struct fwd_stream       *rx_stream; /**< Port RX stream, if unique */
172af75078fSIntel 	struct fwd_stream       *tx_stream; /**< Port TX stream, if unique */
173af75078fSIntel 	unsigned int            socket_id;  /**< For NUMA support */
174cf543fdbSOlivier Matz 	uint16_t                tx_ol_flags;/**< TX Offload Flags (TESTPMD_TX_OFFLOAD...). */
1750f62d635SJianfeng Tan 	uint16_t                tso_segsz;  /**< Segmentation offload MSS for non-tunneled packets. */
1760f62d635SJianfeng Tan 	uint16_t                tunnel_tso_segsz; /**< Segmentation offload MSS for tunneled pkts. */
17792ebda07SHelin Zhang 	uint16_t                tx_vlan_id;/**< The tag ID */
17892ebda07SHelin Zhang 	uint16_t                tx_vlan_id_outer;/**< The outer tag ID */
179af75078fSIntel 	void                    *fwd_ctx;   /**< Forwarding mode context */
180af75078fSIntel 	uint64_t                rx_bad_ip_csum; /**< rx pkts with bad ip checksum  */
181af75078fSIntel 	uint64_t                rx_bad_l4_csum; /**< rx pkts with bad l4 checksum */
182ed30d9b6SIntel 	uint8_t                 tx_queue_stats_mapping_enabled;
183ed30d9b6SIntel 	uint8_t                 rx_queue_stats_mapping_enabled;
184ce8d5614SIntel 	volatile uint16_t        port_status;    /**< port started or not */
185ce8d5614SIntel 	uint8_t                 need_reconfig;  /**< need reconfiguring port or not */
186ce8d5614SIntel 	uint8_t                 need_reconfig_queues; /**< need reconfiguring queues or not */
187ce8d5614SIntel 	uint8_t                 rss_flag;   /**< enable rss or not */
1887741e4cfSIntel 	uint8_t                 dcb_flag;   /**< enable dcb */
189ce8d5614SIntel 	struct rte_eth_rxconf   rx_conf;    /**< rx configuration */
190ce8d5614SIntel 	struct rte_eth_txconf   tx_conf;    /**< tx configuration */
1918fff6675SIvan Boule 	struct ether_addr       *mc_addr_pool; /**< pool of multicast addrs */
1928fff6675SIvan Boule 	uint32_t                mc_addr_nb; /**< nb. of addr. in mc_addr_pool */
19341b05095SBernard Iremonger 	uint8_t                 slave_flag; /**< bonding slave port */
194938a184aSAdrien Mazarguil 	struct port_flow        *flow_list; /**< Associated flows. */
195af75078fSIntel };
196af75078fSIntel 
197af75078fSIntel /**
198af75078fSIntel  * The data structure associated with each forwarding logical core.
199af75078fSIntel  * The logical cores are internally numbered by a core index from 0 to
200af75078fSIntel  * the maximum number of logical cores - 1.
201af75078fSIntel  * The system CPU identifier of all logical cores are setup in a global
202af75078fSIntel  * CPU id. configuration table.
203af75078fSIntel  */
204af75078fSIntel struct fwd_lcore {
205af75078fSIntel 	struct rte_mempool *mbp; /**< The mbuf pool to use by this core */
206af75078fSIntel 	streamid_t stream_idx;   /**< index of 1st stream in "fwd_streams" */
207af75078fSIntel 	streamid_t stream_nb;    /**< number of streams in "fwd_streams" */
208af75078fSIntel 	lcoreid_t  cpuid_idx;    /**< index of logical core in CPU id table */
209af75078fSIntel 	queueid_t  tx_queue;     /**< TX queue to send forwarded packets */
210af75078fSIntel 	volatile char stopped;   /**< stop forwarding when set */
211af75078fSIntel };
212af75078fSIntel 
213af75078fSIntel /*
214af75078fSIntel  * Forwarding mode operations:
215af75078fSIntel  *   - IO forwarding mode (default mode)
216af75078fSIntel  *     Forwards packets unchanged.
217af75078fSIntel  *
218af75078fSIntel  *   - MAC forwarding mode
219af75078fSIntel  *     Set the source and the destination Ethernet addresses of packets
220af75078fSIntel  *     before forwarding them.
221af75078fSIntel  *
222af75078fSIntel  *   - IEEE1588 forwarding mode
223af75078fSIntel  *     Check that received IEEE1588 Precise Time Protocol (PTP) packets are
224af75078fSIntel  *     filtered and timestamped by the hardware.
225af75078fSIntel  *     Forwards packets unchanged on the same port.
226af75078fSIntel  *     Check that sent IEEE1588 PTP packets are timestamped by the hardware.
227af75078fSIntel  */
228af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi);
229af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi);
230af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs);
231af75078fSIntel 
232af75078fSIntel struct fwd_engine {
233af75078fSIntel 	const char       *fwd_mode_name; /**< Forwarding mode name. */
234af75078fSIntel 	port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */
235af75078fSIntel 	port_fwd_end_t   port_fwd_end;   /**< NULL if nothing special to do. */
236af75078fSIntel 	packet_fwd_t     packet_fwd;     /**< Mandatory. */
237af75078fSIntel };
238af75078fSIntel 
239bf56fce1SZhihong Wang #define BURST_TX_WAIT_US 1
240bf56fce1SZhihong Wang #define BURST_TX_RETRIES 64
241bf56fce1SZhihong Wang 
242bf56fce1SZhihong Wang extern uint32_t burst_tx_delay_time;
243bf56fce1SZhihong Wang extern uint32_t burst_tx_retry_num;
244bf56fce1SZhihong Wang 
245af75078fSIntel extern struct fwd_engine io_fwd_engine;
246af75078fSIntel extern struct fwd_engine mac_fwd_engine;
247d47388f1SCyril Chemparathy extern struct fwd_engine mac_swap_engine;
248e9e23a61SCyril Chemparathy extern struct fwd_engine flow_gen_engine;
249af75078fSIntel extern struct fwd_engine rx_only_engine;
250af75078fSIntel extern struct fwd_engine tx_only_engine;
251af75078fSIntel extern struct fwd_engine csum_fwd_engine;
252168dfa61SIvan Boule extern struct fwd_engine icmp_echo_engine;
253af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588
254af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine;
255af75078fSIntel #endif
256af75078fSIntel 
257af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */
258af75078fSIntel 
259af75078fSIntel /**
260af75078fSIntel  * Forwarding Configuration
261af75078fSIntel  *
262af75078fSIntel  */
263af75078fSIntel struct fwd_config {
264af75078fSIntel 	struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */
265af75078fSIntel 	streamid_t nb_fwd_streams;  /**< Nb. of forward streams to process. */
266af75078fSIntel 	lcoreid_t  nb_fwd_lcores;   /**< Nb. of logical cores to launch. */
267af75078fSIntel 	portid_t   nb_fwd_ports;    /**< Nb. of ports involved. */
268af75078fSIntel };
269af75078fSIntel 
270900550deSIntel /**
271900550deSIntel  * DCB mode enable
272900550deSIntel  */
273900550deSIntel enum dcb_mode_enable
274900550deSIntel {
275900550deSIntel 	DCB_VT_ENABLED,
276900550deSIntel 	DCB_ENABLED
277900550deSIntel };
278900550deSIntel 
279ed30d9b6SIntel #define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */
280ed30d9b6SIntel #define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */
281ed30d9b6SIntel 
282ed30d9b6SIntel struct queue_stats_mappings {
283ed30d9b6SIntel 	uint8_t port_id;
284ed30d9b6SIntel 	uint16_t queue_id;
285ed30d9b6SIntel 	uint8_t stats_counter_id;
286ed30d9b6SIntel } __rte_cache_aligned;
287ed30d9b6SIntel 
288ed30d9b6SIntel extern struct queue_stats_mappings tx_queue_stats_mappings_array[];
289ed30d9b6SIntel extern struct queue_stats_mappings rx_queue_stats_mappings_array[];
290ed30d9b6SIntel 
291ed30d9b6SIntel /* Assign both tx and rx queue stats mappings to the same default values */
292ed30d9b6SIntel extern struct queue_stats_mappings *tx_queue_stats_mappings;
293ed30d9b6SIntel extern struct queue_stats_mappings *rx_queue_stats_mappings;
294ed30d9b6SIntel 
295ed30d9b6SIntel extern uint16_t nb_tx_queue_stats_mappings;
296ed30d9b6SIntel extern uint16_t nb_rx_queue_stats_mappings;
297ed30d9b6SIntel 
298af75078fSIntel /* globals used for configuration */
299af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */
300af75078fSIntel extern uint8_t  interactive;
301ca7feb22SCyril Chemparathy extern uint8_t  auto_start;
30299cabef0SPablo de Lara extern uint8_t  tx_first;
30381ef862bSAllain Legacy extern char cmdline_filename[PATH_MAX]; /**< offline commands file */
304af75078fSIntel extern uint8_t  numa_support; /**< set by "--numa" parameter */
305af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */
3067741e4cfSIntel extern uint8_t no_flush_rx; /**<set by "--no-flush-rx" parameter */
307148f963fSBruce Richardson extern uint8_t  mp_anon; /**< set by "--mp-anon" parameter */
308bc202406SDavid Marchand extern uint8_t no_link_check; /**<set by "--disable-link-check" parameter */
3092950a769SDeclan Doherty extern volatile int test_done; /* stop packet forwarding when set to 1. */
3108ea656f8SGaetan Rivet extern uint8_t lsc_interrupt; /**< disabled by "--no-lsc-interrupt" parameter */
311284c908cSGaetan Rivet extern uint8_t rmv_interrupt; /**< disabled by "--no-rmv-interrupt" parameter */
3123af72783SGaetan Rivet extern uint32_t event_print_mask;
3133af72783SGaetan Rivet /**< set by "--print-event xxxx" and "--mask-event xxxx parameters */
314af75078fSIntel 
315e261265eSRadu Nicolau #ifdef RTE_LIBRTE_IXGBE_BYPASS
3167b7e5ba7SIntel extern uint32_t bypass_timeout; /**< Store the NIC bypass watchdog timeout */
3177b7e5ba7SIntel #endif
3187b7e5ba7SIntel 
319b6ea6408SIntel /*
320b6ea6408SIntel  * Store specified sockets on which memory pool to be used by ports
321b6ea6408SIntel  * is allocated.
322b6ea6408SIntel  */
323b6ea6408SIntel uint8_t port_numa[RTE_MAX_ETHPORTS];
324b6ea6408SIntel 
325b6ea6408SIntel /*
326b6ea6408SIntel  * Store specified sockets on which RX ring to be used by ports
327b6ea6408SIntel  * is allocated.
328b6ea6408SIntel  */
329b6ea6408SIntel uint8_t rxring_numa[RTE_MAX_ETHPORTS];
330b6ea6408SIntel 
331b6ea6408SIntel /*
332b6ea6408SIntel  * Store specified sockets on which TX ring to be used by ports
333b6ea6408SIntel  * is allocated.
334b6ea6408SIntel  */
335b6ea6408SIntel uint8_t txring_numa[RTE_MAX_ETHPORTS];
336b6ea6408SIntel 
337b6ea6408SIntel extern uint8_t socket_num;
338b6ea6408SIntel 
339af75078fSIntel /*
340af75078fSIntel  * Configuration of logical cores:
341af75078fSIntel  * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores
342af75078fSIntel  */
343af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */
344af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */
345af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */
346af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE];
347c9cafcc8SShahaf Shuler extern unsigned int num_sockets;
348c9cafcc8SShahaf Shuler extern unsigned int socket_ids[RTE_MAX_NUMA_NODES];
349af75078fSIntel 
350af75078fSIntel /*
351af75078fSIntel  * Configuration of Ethernet ports:
352af75078fSIntel  * nb_fwd_ports <= nb_cfg_ports <= nb_ports
353af75078fSIntel  */
354af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */
355af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */
356af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */
357af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS];
358af75078fSIntel extern struct rte_port *ports;
359af75078fSIntel 
360af75078fSIntel extern struct rte_eth_rxmode rx_mode;
3618a387fa8SHelin Zhang extern uint64_t rss_hf;
362af75078fSIntel 
363af75078fSIntel extern queueid_t nb_rxq;
364af75078fSIntel extern queueid_t nb_txq;
365af75078fSIntel 
366af75078fSIntel extern uint16_t nb_rxd;
367af75078fSIntel extern uint16_t nb_txd;
368af75078fSIntel 
369f2c5125aSPablo de Lara extern int16_t rx_free_thresh;
370f2c5125aSPablo de Lara extern int8_t rx_drop_en;
371f2c5125aSPablo de Lara extern int16_t tx_free_thresh;
372f2c5125aSPablo de Lara extern int16_t tx_rs_thresh;
373f2c5125aSPablo de Lara extern int32_t txq_flags;
374af75078fSIntel 
375900550deSIntel extern uint8_t dcb_config;
376900550deSIntel extern uint8_t dcb_test;
377900550deSIntel extern enum dcb_queue_mapping_mode dcb_q_mapping;
378900550deSIntel 
379af75078fSIntel extern uint16_t mbuf_data_size; /**< Mbuf data space size. */
380c8798818SIntel extern uint32_t param_total_num_mbufs;
381af75078fSIntel 
382*cfea1f30SPablo de Lara extern uint16_t stats_period;
38362d3216dSReshma Pattan 
38462d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS
38562d3216dSReshma Pattan extern uint8_t latencystats_enabled;
38662d3216dSReshma Pattan extern lcoreid_t latencystats_lcore_id;
38762d3216dSReshma Pattan #endif
38862d3216dSReshma Pattan 
389e25e6c70SRemy Horton #ifdef RTE_LIBRTE_BITRATE
390e25e6c70SRemy Horton extern lcoreid_t bitrate_lcore_id;
391e25e6c70SRemy Horton extern uint8_t bitrate_enabled;
392e25e6c70SRemy Horton #endif
393e25e6c70SRemy Horton 
394af75078fSIntel extern struct rte_fdir_conf fdir_conf;
395af75078fSIntel 
396af75078fSIntel /*
397af75078fSIntel  * Configuration of packet segments used by the "txonly" processing engine.
398af75078fSIntel  */
399af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64
400af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */
401af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */
402af75078fSIntel extern uint8_t  tx_pkt_nb_segs; /**< Number of segments in TX packets */
403af75078fSIntel 
40479bec05bSKonstantin Ananyev enum tx_pkt_split {
40579bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_OFF,
40679bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_ON,
40779bec05bSKonstantin Ananyev 	TX_PKT_SPLIT_RND,
40879bec05bSKonstantin Ananyev };
40979bec05bSKonstantin Ananyev 
41079bec05bSKonstantin Ananyev extern enum tx_pkt_split tx_pkt_split;
41179bec05bSKonstantin Ananyev 
412af75078fSIntel extern uint16_t nb_pkt_per_burst;
413af75078fSIntel extern uint16_t mb_mempool_cache;
414f2c5125aSPablo de Lara extern int8_t rx_pthresh;
415f2c5125aSPablo de Lara extern int8_t rx_hthresh;
416f2c5125aSPablo de Lara extern int8_t rx_wthresh;
417f2c5125aSPablo de Lara extern int8_t tx_pthresh;
418f2c5125aSPablo de Lara extern int8_t tx_hthresh;
419f2c5125aSPablo de Lara extern int8_t tx_wthresh;
420af75078fSIntel 
421af75078fSIntel extern struct fwd_config cur_fwd_config;
422af75078fSIntel extern struct fwd_engine *cur_fwd_eng;
423bf56fce1SZhihong Wang extern uint32_t retry_enabled;
424af75078fSIntel extern struct fwd_lcore  **fwd_lcores;
425af75078fSIntel extern struct fwd_stream **fwd_streams;
426af75078fSIntel 
427af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */
428af75078fSIntel extern struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS];
429af75078fSIntel 
43057e85242SBruce Richardson extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */
43157e85242SBruce Richardson extern uint32_t burst_tx_retry_num;  /**< Burst tx retry number for mac-retry. */
43257e85242SBruce Richardson 
433af75078fSIntel static inline unsigned int
434af75078fSIntel lcore_num(void)
435af75078fSIntel {
436af75078fSIntel 	unsigned int i;
437af75078fSIntel 
438af75078fSIntel 	for (i = 0; i < RTE_MAX_LCORE; ++i)
439af75078fSIntel 		if (fwd_lcores_cpuids[i] == rte_lcore_id())
440af75078fSIntel 			return i;
441af75078fSIntel 
442af75078fSIntel 	rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n");
443af75078fSIntel }
444af75078fSIntel 
445af75078fSIntel static inline struct fwd_lcore *
446af75078fSIntel current_fwd_lcore(void)
447af75078fSIntel {
448af75078fSIntel 	return fwd_lcores[lcore_num()];
449af75078fSIntel }
450af75078fSIntel 
451af75078fSIntel /* Mbuf Pools */
452af75078fSIntel static inline void
453af75078fSIntel mbuf_poolname_build(unsigned int sock_id, char* mp_name, int name_size)
454af75078fSIntel {
4556f41fe75SStephen Hemminger 	snprintf(mp_name, name_size, "mbuf_pool_socket_%u", sock_id);
456af75078fSIntel }
457af75078fSIntel 
458af75078fSIntel static inline struct rte_mempool *
459af75078fSIntel mbuf_pool_find(unsigned int sock_id)
460af75078fSIntel {
461af75078fSIntel 	char pool_name[RTE_MEMPOOL_NAMESIZE];
462af75078fSIntel 
463af75078fSIntel 	mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name));
464693f715dSHuawei Xie 	return rte_mempool_lookup((const char *)pool_name);
465af75078fSIntel }
466af75078fSIntel 
467af75078fSIntel /**
468af75078fSIntel  * Read/Write operations on a PCI register of a port.
469af75078fSIntel  */
470af75078fSIntel static inline uint32_t
471af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off)
472af75078fSIntel {
473af75078fSIntel 	void *reg_addr;
474af75078fSIntel 	uint32_t reg_v;
475af75078fSIntel 
476eee16c96SStephen Hemminger 	reg_addr = (void *)
477eee16c96SStephen Hemminger 		((char *)port->dev_info.pci_dev->mem_resource[0].addr +
478af75078fSIntel 			reg_off);
479af75078fSIntel 	reg_v = *((volatile uint32_t *)reg_addr);
480af75078fSIntel 	return rte_le_to_cpu_32(reg_v);
481af75078fSIntel }
482af75078fSIntel 
483af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \
484af75078fSIntel 	port_pci_reg_read(&ports[(pt_id)], (reg_off))
485af75078fSIntel 
486af75078fSIntel static inline void
487af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v)
488af75078fSIntel {
489af75078fSIntel 	void *reg_addr;
490af75078fSIntel 
491eee16c96SStephen Hemminger 	reg_addr = (void *)
492eee16c96SStephen Hemminger 		((char *)port->dev_info.pci_dev->mem_resource[0].addr +
493af75078fSIntel 			reg_off);
494af75078fSIntel 	*((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v);
495af75078fSIntel }
496af75078fSIntel 
497af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \
498af75078fSIntel 	port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value))
499af75078fSIntel 
500af75078fSIntel /* Prototypes */
501950d1516SBruce Richardson unsigned int parse_item_list(char* str, const char* item_name,
502950d1516SBruce Richardson 			unsigned int max_items,
503950d1516SBruce Richardson 			unsigned int *parsed_items, int check_unique_values);
504af75078fSIntel void launch_args_parse(int argc, char** argv);
50581ef862bSAllain Legacy void cmdline_read_from_file(const char *filename);
506af75078fSIntel void prompt(void);
507d3a274ceSZhihong Wang void prompt_exit(void);
508af75078fSIntel void nic_stats_display(portid_t port_id);
509af75078fSIntel void nic_stats_clear(portid_t port_id);
510bfd5051bSOlivier Matz void nic_xstats_display(portid_t port_id);
511bfd5051bSOlivier Matz void nic_xstats_clear(portid_t port_id);
512ed30d9b6SIntel void nic_stats_mapping_display(portid_t port_id);
513af75078fSIntel void port_infos_display(portid_t port_id);
514d28645c7SQiming Yang void port_offload_cap_display(portid_t port_id);
515ab3257e1SKonstantin Ananyev void rx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
516ab3257e1SKonstantin Ananyev void tx_queue_infos_display(portid_t port_idi, uint16_t queue_id);
517af75078fSIntel void fwd_lcores_config_display(void);
5180c0db76fSBernard Iremonger void pkt_fwd_config_display(struct fwd_config *cfg);
519af75078fSIntel void rxtx_config_display(void);
520af75078fSIntel void fwd_config_setup(void);
521af75078fSIntel void set_def_fwd_config(void);
522a21d5a4bSDeclan Doherty void reconfig(portid_t new_port_id, unsigned socket_id);
523013af9b6SIntel int init_fwd_streams(void);
524013af9b6SIntel 
525ae03d0d1SIvan Boule void port_mtu_set(portid_t port_id, uint16_t mtu);
526af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos);
527af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos,
528af75078fSIntel 		      uint8_t bit_v);
529af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off,
530af75078fSIntel 				uint8_t bit1_pos, uint8_t bit2_pos);
531af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off,
532af75078fSIntel 			    uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value);
533af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off);
534af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value);
535938a184aSAdrien Mazarguil int port_flow_validate(portid_t port_id,
536938a184aSAdrien Mazarguil 		       const struct rte_flow_attr *attr,
537938a184aSAdrien Mazarguil 		       const struct rte_flow_item *pattern,
538938a184aSAdrien Mazarguil 		       const struct rte_flow_action *actions);
539938a184aSAdrien Mazarguil int port_flow_create(portid_t port_id,
540938a184aSAdrien Mazarguil 		     const struct rte_flow_attr *attr,
541938a184aSAdrien Mazarguil 		     const struct rte_flow_item *pattern,
542938a184aSAdrien Mazarguil 		     const struct rte_flow_action *actions);
543938a184aSAdrien Mazarguil int port_flow_destroy(portid_t port_id, uint32_t n, const uint32_t *rule);
544938a184aSAdrien Mazarguil int port_flow_flush(portid_t port_id);
545938a184aSAdrien Mazarguil int port_flow_query(portid_t port_id, uint32_t rule,
546938a184aSAdrien Mazarguil 		    enum rte_flow_action_type action);
547938a184aSAdrien Mazarguil void port_flow_list(portid_t port_id, uint32_t n, const uint32_t *group);
548323f811aSAdrien Mazarguil int port_flow_isolate(portid_t port_id, int set);
549af75078fSIntel 
550af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id);
551af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id);
552af75078fSIntel 
553013af9b6SIntel int set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc);
554013af9b6SIntel int set_fwd_lcores_mask(uint64_t lcoremask);
555af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc);
556af75078fSIntel 
557af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt);
558af75078fSIntel void set_fwd_ports_mask(uint64_t portmask);
559af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt);
560a8ef3e3aSBernard Iremonger int port_is_forwarding(portid_t port_id);
561af75078fSIntel 
562a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on);
563a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on);
564a47aa8b9SIntel 
565a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on);
566af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on);
56764b01ee0SMichal Jastrzebski int rx_vft_set(portid_t port_id, uint16_t vlan_id, int on);
568a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on);
56919b16e2fSHelin Zhang void vlan_tpid_set(portid_t port_id, enum rte_vlan_type vlan_type,
57019b16e2fSHelin Zhang 		   uint16_t tp_id);
571af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id);
57292ebda07SHelin Zhang void tx_qinq_set(portid_t port_id, uint16_t vlan_id, uint16_t vlan_id_outer);
573af75078fSIntel void tx_vlan_reset(portid_t port_id);
574529ba951SHelin Zhang void tx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on);
575ed30d9b6SIntel 
576ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value);
577ed30d9b6SIntel 
578af75078fSIntel void set_verbose_level(uint16_t vb_level);
579af75078fSIntel void set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs);
58079bec05bSKonstantin Ananyev void show_tx_pkt_segments(void);
58179bec05bSKonstantin Ananyev void set_tx_pkt_split(const char *name);
582af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst);
583769ce6b1SThomas Monjalon char *list_pkt_forwarding_modes(void);
584bf56fce1SZhihong Wang char *list_pkt_forwarding_retry_modes(void);
585af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode);
586af75078fSIntel void start_packet_forwarding(int with_tx_first);
587af75078fSIntel void stop_packet_forwarding(void);
588cfae07fdSOuyang Changchun void dev_set_link_up(portid_t pid);
589cfae07fdSOuyang Changchun void dev_set_link_down(portid_t pid);
590ce8d5614SIntel void init_port_config(void);
59141b05095SBernard Iremonger void set_port_slave_flag(portid_t slave_pid);
59241b05095SBernard Iremonger void clear_port_slave_flag(portid_t slave_pid);
5930e545d30SBernard Iremonger uint8_t port_is_bonding_slave(portid_t slave_pid);
5940e545d30SBernard Iremonger 
5951a572499SJingjing Wu int init_port_dcb_config(portid_t pid, enum dcb_mode_enable dcb_mode,
5961a572499SJingjing Wu 		     enum rte_eth_nb_tcs num_tcs,
5971a572499SJingjing Wu 		     uint8_t pfc_en);
598148f963fSBruce Richardson int start_port(portid_t pid);
599ce8d5614SIntel void stop_port(portid_t pid);
600ce8d5614SIntel void close_port(portid_t pid);
601edab33b1STetsuya Mukawa void attach_port(char *identifier);
602edab33b1STetsuya Mukawa void detach_port(uint8_t port_id);
603ce8d5614SIntel int all_ports_stopped(void);
6045f4ec54fSChen Jing D(Mark) int port_is_started(portid_t port_id);
605af75078fSIntel void pmd_test_exit(void);
606af75078fSIntel void fdir_get_infos(portid_t port_id);
607aeca06dfSJingjing Wu void fdir_set_flex_mask(portid_t port_id,
608aeca06dfSJingjing Wu 			   struct rte_eth_fdir_flex_mask *cfg);
60997b74464SJingjing Wu void fdir_set_flex_payload(portid_t port_id,
61097b74464SJingjing Wu 			   struct rte_eth_flex_payload_cfg *cfg);
61166c59490SHelin Zhang void port_rss_reta_info(portid_t port_id,
61266c59490SHelin Zhang 			struct rte_eth_rss_reta_entry64 *reta_conf,
61366c59490SHelin Zhang 			uint16_t nb_entries);
6146a18e1afSOuyang Changchun 
6157741e4cfSIntel void set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on);
616af75078fSIntel 
6176a18e1afSOuyang Changchun int set_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate);
6186a18e1afSOuyang Changchun int set_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate,
6196a18e1afSOuyang Changchun 				uint64_t q_msk);
6206a18e1afSOuyang Changchun 
6218205e241SNelio Laranjeiro void port_rss_hash_conf_show(portid_t port_id, char rss_info[],
6228205e241SNelio Laranjeiro 			     int show_rss_key);
6238205e241SNelio Laranjeiro void port_rss_hash_key_update(portid_t port_id, char rss_type[],
6248205e241SNelio Laranjeiro 			      uint8_t *hash_key, uint hash_key_len);
6250db70a80SJingjing Wu void get_syn_filter(uint8_t port_id);
6260db70a80SJingjing Wu void get_ethertype_filter(uint8_t port_id, uint16_t index);
6270db70a80SJingjing Wu void get_2tuple_filter(uint8_t port_id, uint16_t index);
6280db70a80SJingjing Wu void get_5tuple_filter(uint8_t port_id, uint16_t index);
6295f4ec54fSChen Jing D(Mark) int rx_queue_id_is_invalid(queueid_t rxq_id);
6305f4ec54fSChen Jing D(Mark) int tx_queue_id_is_invalid(queueid_t txq_id);
63116321de0SIvan Boule 
6328fff6675SIvan Boule /* Functions to manage the set of filtered Multicast MAC addresses */
6338fff6675SIvan Boule void mcast_addr_add(uint8_t port_id, struct ether_addr *mc_addr);
6348fff6675SIvan Boule void mcast_addr_remove(uint8_t port_id, struct ether_addr *mc_addr);
635cd80f411SJingjing Wu void port_dcb_info_display(uint8_t port_id);
6368fff6675SIvan Boule 
637a92a5a2cSBeilei Xing uint8_t *open_ddp_package_file(const char *file_path, uint32_t *size);
638a92a5a2cSBeilei Xing int close_ddp_package_file(uint8_t *buf);
639a92a5a2cSBeilei Xing 
640edab33b1STetsuya Mukawa enum print_warning {
641edab33b1STetsuya Mukawa 	ENABLED_WARN = 0,
642edab33b1STetsuya Mukawa 	DISABLED_WARN
643edab33b1STetsuya Mukawa };
644edab33b1STetsuya Mukawa int port_id_is_invalid(portid_t port_id, enum print_warning warning);
645c9cafcc8SShahaf Shuler int new_socket_id(unsigned int socket_id);
646edab33b1STetsuya Mukawa 
647af75078fSIntel /*
648af75078fSIntel  * Work-around of a compilation error with ICC on invocations of the
649af75078fSIntel  * rte_be_to_cpu_16() function.
650af75078fSIntel  */
651af75078fSIntel #ifdef __GCC__
652af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  rte_be_to_cpu_16((be_16_v))
653af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v))
654af75078fSIntel #else
65544eb9456SThomas Monjalon #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
656af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  (be_16_v)
657af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v)
658af75078fSIntel #else
659af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \
660af75078fSIntel 	(uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8))
661af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \
662af75078fSIntel 	(uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8))
663af75078fSIntel #endif
664af75078fSIntel #endif /* __GCC__ */
665af75078fSIntel 
666af75078fSIntel #endif /* _TESTPMD_H_ */
667