xref: /dpdk/app/test-pmd/testpmd.h (revision cfae07fdaa3e71ca9fafbc3e22fcf66d2f97e9ba)
1af75078fSIntel /*-
2af75078fSIntel  *   BSD LICENSE
3af75078fSIntel  *
4e9d48c00SBruce Richardson  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5af75078fSIntel  *   All rights reserved.
6af75078fSIntel  *
7af75078fSIntel  *   Redistribution and use in source and binary forms, with or without
8af75078fSIntel  *   modification, are permitted provided that the following conditions
9af75078fSIntel  *   are met:
10af75078fSIntel  *
11af75078fSIntel  *     * Redistributions of source code must retain the above copyright
12af75078fSIntel  *       notice, this list of conditions and the following disclaimer.
13af75078fSIntel  *     * Redistributions in binary form must reproduce the above copyright
14af75078fSIntel  *       notice, this list of conditions and the following disclaimer in
15af75078fSIntel  *       the documentation and/or other materials provided with the
16af75078fSIntel  *       distribution.
17af75078fSIntel  *     * Neither the name of Intel Corporation nor the names of its
18af75078fSIntel  *       contributors may be used to endorse or promote products derived
19af75078fSIntel  *       from this software without specific prior written permission.
20af75078fSIntel  *
21af75078fSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22af75078fSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23af75078fSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24af75078fSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25af75078fSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26af75078fSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27af75078fSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28af75078fSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29af75078fSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30af75078fSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31af75078fSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32af75078fSIntel  */
33af75078fSIntel 
34af75078fSIntel #ifndef _TESTPMD_H_
35af75078fSIntel #define _TESTPMD_H_
36af75078fSIntel 
37af75078fSIntel /* icc on baremetal gives us troubles with function named 'main' */
38af75078fSIntel #ifdef RTE_EXEC_ENV_BAREMETAL
39af75078fSIntel #define main _main
40af75078fSIntel int main(int argc, char **argv);
41af75078fSIntel #endif
42af75078fSIntel 
43ce8d5614SIntel #define RTE_PORT_ALL            (~(portid_t)0x0)
44ce8d5614SIntel 
45ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX    2048
46ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX    2048
47ce8d5614SIntel 
48ce8d5614SIntel #define RTE_PORT_STOPPED        (uint16_t)0
49ce8d5614SIntel #define RTE_PORT_STARTED        (uint16_t)1
50ce8d5614SIntel #define RTE_PORT_CLOSED         (uint16_t)2
51ce8d5614SIntel #define RTE_PORT_HANDLING       (uint16_t)3
52ce8d5614SIntel 
53af75078fSIntel /*
54af75078fSIntel  * Default size of the mbuf data buffer to receive standard 1518-byte
55af75078fSIntel  * Ethernet frames in a mono-segment memory buffer.
56af75078fSIntel  */
57af75078fSIntel #define DEFAULT_MBUF_DATA_SIZE 2048 /**< Default size of mbuf data buffer. */
58af75078fSIntel 
59af75078fSIntel /*
60af75078fSIntel  * The maximum number of segments per packet is used when creating
61af75078fSIntel  * scattered transmit packets composed of a list of mbufs.
62af75078fSIntel  */
63af75078fSIntel #define RTE_MAX_SEGS_PER_PKT 255 /**< pkt.nb_segs is a 8-bit unsigned char. */
64af75078fSIntel 
65af75078fSIntel #define MAX_PKT_BURST 512
66af75078fSIntel #define DEF_PKT_BURST 16
67af75078fSIntel 
68af75078fSIntel #define CACHE_LINE_SIZE_ROUNDUP(size) \
69af75078fSIntel 	(CACHE_LINE_SIZE * ((size + CACHE_LINE_SIZE - 1) / CACHE_LINE_SIZE))
70af75078fSIntel 
71b6ea6408SIntel #define NUMA_NO_CONFIG 0xFF
72b6ea6408SIntel #define UMA_NO_CONFIG  0xFF
73b6ea6408SIntel 
74af75078fSIntel typedef uint8_t  lcoreid_t;
75af75078fSIntel typedef uint8_t  portid_t;
76af75078fSIntel typedef uint16_t queueid_t;
77af75078fSIntel typedef uint16_t streamid_t;
78af75078fSIntel 
79af75078fSIntel #define MAX_QUEUE_ID ((1 << (sizeof(queueid_t) * 8)) - 1)
80af75078fSIntel 
81af75078fSIntel enum {
82af75078fSIntel 	PORT_TOPOLOGY_PAIRED,
833e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_CHAINED,
843e2006d6SCyril Chemparathy 	PORT_TOPOLOGY_LOOP,
85af75078fSIntel };
86af75078fSIntel 
87af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
88af75078fSIntel /**
89af75078fSIntel  * The data structure associated with RX and TX packet burst statistics
90af75078fSIntel  * that are recorded for each forwarding stream.
91af75078fSIntel  */
92af75078fSIntel struct pkt_burst_stats {
93af75078fSIntel 	unsigned int pkt_burst_spread[MAX_PKT_BURST];
94af75078fSIntel };
95af75078fSIntel #endif
96af75078fSIntel 
97af75078fSIntel /**
98af75078fSIntel  * The data structure associated with a forwarding stream between a receive
99af75078fSIntel  * port/queue and a transmit port/queue.
100af75078fSIntel  */
101af75078fSIntel struct fwd_stream {
102af75078fSIntel 	/* "read-only" data */
103af75078fSIntel 	portid_t   rx_port;   /**< port to poll for received packets */
104af75078fSIntel 	queueid_t  rx_queue;  /**< RX queue to poll on "rx_port" */
105af75078fSIntel 	portid_t   tx_port;   /**< forwarding port of received packets */
106af75078fSIntel 	queueid_t  tx_queue;  /**< TX queue to send forwarded packets */
107af75078fSIntel 	streamid_t peer_addr; /**< index of peer ethernet address of packets */
108af75078fSIntel 
109af75078fSIntel 	/* "read-write" results */
110af75078fSIntel 	unsigned int rx_packets;  /**< received packets */
111af75078fSIntel 	unsigned int tx_packets;  /**< received packets transmitted */
112af75078fSIntel 	unsigned int fwd_dropped; /**< received packets not forwarded */
113af75078fSIntel 	unsigned int rx_bad_ip_csum ; /**< received packets has bad ip checksum */
114af75078fSIntel 	unsigned int rx_bad_l4_csum ; /**< received packets has bad l4 checksum */
115af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES
116af75078fSIntel 	uint64_t     core_cycles; /**< used for RX and TX processing */
117af75078fSIntel #endif
118af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS
119af75078fSIntel 	struct pkt_burst_stats rx_burst_stats;
120af75078fSIntel 	struct pkt_burst_stats tx_burst_stats;
121af75078fSIntel #endif
122af75078fSIntel };
123af75078fSIntel 
124af75078fSIntel /**
125af75078fSIntel  * The data structure associated with each port.
126af75078fSIntel  * tx_ol_flags is slightly different from ol_flags of rte_mbuf.
127af75078fSIntel  *   Bit  0: Insert IP checksum
128af75078fSIntel  *   Bit  1: Insert UDP checksum
129af75078fSIntel  *   Bit  2: Insert TCP checksum
130af75078fSIntel  *   Bit  3: Insert SCTP checksum
131af75078fSIntel  *   Bit 11: Insert VLAN Label
132af75078fSIntel  */
133af75078fSIntel struct rte_port {
134af75078fSIntel 	struct rte_eth_dev_info dev_info;   /**< PCI info + driver name */
135af75078fSIntel 	struct rte_eth_conf     dev_conf;   /**< Port configuration. */
136af75078fSIntel 	struct ether_addr       eth_addr;   /**< Port ethernet address */
137af75078fSIntel 	struct rte_eth_stats    stats;      /**< Last port statistics */
138af75078fSIntel 	uint64_t                tx_dropped; /**< If no descriptor in TX ring */
139af75078fSIntel 	struct fwd_stream       *rx_stream; /**< Port RX stream, if unique */
140af75078fSIntel 	struct fwd_stream       *tx_stream; /**< Port TX stream, if unique */
141af75078fSIntel 	unsigned int            socket_id;  /**< For NUMA support */
142af75078fSIntel 	uint16_t                tx_ol_flags;/**< Offload Flags of TX packets. */
143af75078fSIntel 	uint16_t                tx_vlan_id; /**< Tag Id. in TX VLAN packets. */
144af75078fSIntel 	void                    *fwd_ctx;   /**< Forwarding mode context */
145af75078fSIntel 	uint64_t                rx_bad_ip_csum; /**< rx pkts with bad ip checksum  */
146af75078fSIntel 	uint64_t                rx_bad_l4_csum; /**< rx pkts with bad l4 checksum */
147ed30d9b6SIntel 	uint8_t                 tx_queue_stats_mapping_enabled;
148ed30d9b6SIntel 	uint8_t                 rx_queue_stats_mapping_enabled;
149ce8d5614SIntel 	volatile uint16_t        port_status;    /**< port started or not */
150ce8d5614SIntel 	uint8_t                 need_reconfig;  /**< need reconfiguring port or not */
151ce8d5614SIntel 	uint8_t                 need_reconfig_queues; /**< need reconfiguring queues or not */
152ce8d5614SIntel 	uint8_t                 rss_flag;   /**< enable rss or not */
1537741e4cfSIntel 	uint8_t			dcb_flag;   /**< enable dcb */
154ce8d5614SIntel 	struct rte_eth_rxconf   rx_conf;    /**< rx configuration */
155ce8d5614SIntel 	struct rte_eth_txconf   tx_conf;    /**< tx configuration */
156af75078fSIntel };
157af75078fSIntel 
158af75078fSIntel /**
159af75078fSIntel  * The data structure associated with each forwarding logical core.
160af75078fSIntel  * The logical cores are internally numbered by a core index from 0 to
161af75078fSIntel  * the maximum number of logical cores - 1.
162af75078fSIntel  * The system CPU identifier of all logical cores are setup in a global
163af75078fSIntel  * CPU id. configuration table.
164af75078fSIntel  */
165af75078fSIntel struct fwd_lcore {
166af75078fSIntel 	struct rte_mempool *mbp; /**< The mbuf pool to use by this core */
167af75078fSIntel 	streamid_t stream_idx;   /**< index of 1st stream in "fwd_streams" */
168af75078fSIntel 	streamid_t stream_nb;    /**< number of streams in "fwd_streams" */
169af75078fSIntel 	lcoreid_t  cpuid_idx;    /**< index of logical core in CPU id table */
170af75078fSIntel 	queueid_t  tx_queue;     /**< TX queue to send forwarded packets */
171af75078fSIntel 	volatile char stopped;   /**< stop forwarding when set */
172af75078fSIntel };
173af75078fSIntel 
174af75078fSIntel /*
175af75078fSIntel  * Forwarding mode operations:
176af75078fSIntel  *   - IO forwarding mode (default mode)
177af75078fSIntel  *     Forwards packets unchanged.
178af75078fSIntel  *
179af75078fSIntel  *   - MAC forwarding mode
180af75078fSIntel  *     Set the source and the destination Ethernet addresses of packets
181af75078fSIntel  *     before forwarding them.
182af75078fSIntel  *
183af75078fSIntel  *   - IEEE1588 forwarding mode
184af75078fSIntel  *     Check that received IEEE1588 Precise Time Protocol (PTP) packets are
185af75078fSIntel  *     filtered and timestamped by the hardware.
186af75078fSIntel  *     Forwards packets unchanged on the same port.
187af75078fSIntel  *     Check that sent IEEE1588 PTP packets are timestamped by the hardware.
188af75078fSIntel  */
189af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi);
190af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi);
191af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs);
192af75078fSIntel 
193af75078fSIntel struct fwd_engine {
194af75078fSIntel 	const char       *fwd_mode_name; /**< Forwarding mode name. */
195af75078fSIntel 	port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */
196af75078fSIntel 	port_fwd_end_t   port_fwd_end;   /**< NULL if nothing special to do. */
197af75078fSIntel 	packet_fwd_t     packet_fwd;     /**< Mandatory. */
198af75078fSIntel };
199af75078fSIntel 
200af75078fSIntel extern struct fwd_engine io_fwd_engine;
201af75078fSIntel extern struct fwd_engine mac_fwd_engine;
20257e85242SBruce Richardson extern struct fwd_engine mac_retry_fwd_engine;
203d47388f1SCyril Chemparathy extern struct fwd_engine mac_swap_engine;
204e9e23a61SCyril Chemparathy extern struct fwd_engine flow_gen_engine;
205af75078fSIntel extern struct fwd_engine rx_only_engine;
206af75078fSIntel extern struct fwd_engine tx_only_engine;
207af75078fSIntel extern struct fwd_engine csum_fwd_engine;
208168dfa61SIvan Boule extern struct fwd_engine icmp_echo_engine;
209af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588
210af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine;
211af75078fSIntel #endif
212af75078fSIntel 
213af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */
214af75078fSIntel 
215af75078fSIntel /**
216af75078fSIntel  * Forwarding Configuration
217af75078fSIntel  *
218af75078fSIntel  */
219af75078fSIntel struct fwd_config {
220af75078fSIntel 	struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */
221af75078fSIntel 	streamid_t nb_fwd_streams;  /**< Nb. of forward streams to process. */
222af75078fSIntel 	lcoreid_t  nb_fwd_lcores;   /**< Nb. of logical cores to launch. */
223af75078fSIntel 	portid_t   nb_fwd_ports;    /**< Nb. of ports involved. */
224af75078fSIntel };
225af75078fSIntel 
226900550deSIntel /**
227900550deSIntel  * DCB mode enable
228900550deSIntel  */
229900550deSIntel enum dcb_mode_enable
230900550deSIntel {
231900550deSIntel 	DCB_VT_ENABLED,
232900550deSIntel 	DCB_ENABLED
233900550deSIntel };
234900550deSIntel 
235900550deSIntel /*
236900550deSIntel  * DCB general config info
237900550deSIntel  */
238900550deSIntel struct dcb_config {
239900550deSIntel 	enum dcb_mode_enable dcb_mode;
240900550deSIntel 	uint8_t vt_en;
241900550deSIntel 	enum rte_eth_nb_tcs num_tcs;
242900550deSIntel 	uint8_t pfc_en;
243900550deSIntel };
244900550deSIntel 
245900550deSIntel /*
246900550deSIntel  * In DCB io FWD mode, 128 RX queue to 128 TX queue mapping
247900550deSIntel  */
248900550deSIntel enum dcb_queue_mapping_mode {
249900550deSIntel 	DCB_VT_Q_MAPPING = 0,
250900550deSIntel 	DCB_4_TCS_Q_MAPPING,
251900550deSIntel 	DCB_8_TCS_Q_MAPPING
252900550deSIntel };
253900550deSIntel 
254ed30d9b6SIntel #define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */
255ed30d9b6SIntel #define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */
256ed30d9b6SIntel 
257ed30d9b6SIntel struct queue_stats_mappings {
258ed30d9b6SIntel 	uint8_t port_id;
259ed30d9b6SIntel 	uint16_t queue_id;
260ed30d9b6SIntel 	uint8_t stats_counter_id;
261ed30d9b6SIntel } __rte_cache_aligned;
262ed30d9b6SIntel 
263ed30d9b6SIntel extern struct queue_stats_mappings tx_queue_stats_mappings_array[];
264ed30d9b6SIntel extern struct queue_stats_mappings rx_queue_stats_mappings_array[];
265ed30d9b6SIntel 
266ed30d9b6SIntel /* Assign both tx and rx queue stats mappings to the same default values */
267ed30d9b6SIntel extern struct queue_stats_mappings *tx_queue_stats_mappings;
268ed30d9b6SIntel extern struct queue_stats_mappings *rx_queue_stats_mappings;
269ed30d9b6SIntel 
270ed30d9b6SIntel extern uint16_t nb_tx_queue_stats_mappings;
271ed30d9b6SIntel extern uint16_t nb_rx_queue_stats_mappings;
272ed30d9b6SIntel 
273af75078fSIntel /* globals used for configuration */
274af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */
275af75078fSIntel extern uint8_t  interactive;
276ca7feb22SCyril Chemparathy extern uint8_t  auto_start;
277af75078fSIntel extern uint8_t  numa_support; /**< set by "--numa" parameter */
278af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */
2797741e4cfSIntel extern uint8_t no_flush_rx; /**<set by "--no-flush-rx" parameter */
280148f963fSBruce Richardson extern uint8_t  mp_anon; /**< set by "--mp-anon" parameter */
281bc202406SDavid Marchand extern uint8_t no_link_check; /**<set by "--disable-link-check" parameter */
282af75078fSIntel 
2837b7e5ba7SIntel #ifdef RTE_NIC_BYPASS
2847b7e5ba7SIntel extern uint32_t bypass_timeout; /**< Store the NIC bypass watchdog timeout */
2857b7e5ba7SIntel #endif
2867b7e5ba7SIntel 
287b6ea6408SIntel #define MAX_SOCKET 2 /*MAX SOCKET:currently, it is 2 */
288b6ea6408SIntel 
289b6ea6408SIntel /*
290b6ea6408SIntel  * Store specified sockets on which memory pool to be used by ports
291b6ea6408SIntel  * is allocated.
292b6ea6408SIntel  */
293b6ea6408SIntel uint8_t port_numa[RTE_MAX_ETHPORTS];
294b6ea6408SIntel 
295b6ea6408SIntel /*
296b6ea6408SIntel  * Store specified sockets on which RX ring to be used by ports
297b6ea6408SIntel  * is allocated.
298b6ea6408SIntel  */
299b6ea6408SIntel uint8_t rxring_numa[RTE_MAX_ETHPORTS];
300b6ea6408SIntel 
301b6ea6408SIntel /*
302b6ea6408SIntel  * Store specified sockets on which TX ring to be used by ports
303b6ea6408SIntel  * is allocated.
304b6ea6408SIntel  */
305b6ea6408SIntel uint8_t txring_numa[RTE_MAX_ETHPORTS];
306b6ea6408SIntel 
307b6ea6408SIntel extern uint8_t socket_num;
308b6ea6408SIntel 
309af75078fSIntel /*
310af75078fSIntel  * Configuration of logical cores:
311af75078fSIntel  * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores
312af75078fSIntel  */
313af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */
314af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */
315af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */
316af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE];
317af75078fSIntel 
318af75078fSIntel /*
319af75078fSIntel  * Configuration of Ethernet ports:
320af75078fSIntel  * nb_fwd_ports <= nb_cfg_ports <= nb_ports
321af75078fSIntel  */
322af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */
323af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */
324af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */
325af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS];
326af75078fSIntel extern struct rte_port *ports;
327af75078fSIntel 
328af75078fSIntel extern struct rte_eth_rxmode rx_mode;
329af75078fSIntel extern uint16_t rss_hf;
330af75078fSIntel 
331af75078fSIntel extern queueid_t nb_rxq;
332af75078fSIntel extern queueid_t nb_txq;
333af75078fSIntel 
334af75078fSIntel extern uint16_t nb_rxd;
335af75078fSIntel extern uint16_t nb_txd;
336af75078fSIntel 
337af75078fSIntel extern uint16_t rx_free_thresh;
338ce8d5614SIntel extern uint8_t rx_drop_en;
339af75078fSIntel extern uint16_t tx_free_thresh;
340af75078fSIntel extern uint16_t tx_rs_thresh;
341ce8d5614SIntel extern uint32_t txq_flags;
342af75078fSIntel 
343900550deSIntel extern uint8_t dcb_config;
344900550deSIntel extern uint8_t dcb_test;
345900550deSIntel extern enum dcb_queue_mapping_mode dcb_q_mapping;
346900550deSIntel 
347af75078fSIntel extern uint16_t mbuf_data_size; /**< Mbuf data space size. */
348c8798818SIntel extern uint32_t param_total_num_mbufs;
349af75078fSIntel 
350af75078fSIntel extern struct rte_fdir_conf fdir_conf;
351af75078fSIntel 
352af75078fSIntel /*
353af75078fSIntel  * Configuration of packet segments used by the "txonly" processing engine.
354af75078fSIntel  */
355af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64
356af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */
357af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */
358af75078fSIntel extern uint8_t  tx_pkt_nb_segs; /**< Number of segments in TX packets */
359af75078fSIntel 
360af75078fSIntel extern uint16_t nb_pkt_per_burst;
361af75078fSIntel extern uint16_t mb_mempool_cache;
362af75078fSIntel extern struct rte_eth_thresh rx_thresh;
363af75078fSIntel extern struct rte_eth_thresh tx_thresh;
364af75078fSIntel 
365af75078fSIntel extern struct fwd_config cur_fwd_config;
366af75078fSIntel extern struct fwd_engine *cur_fwd_eng;
367af75078fSIntel extern struct fwd_lcore  **fwd_lcores;
368af75078fSIntel extern struct fwd_stream **fwd_streams;
369af75078fSIntel 
370af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */
371af75078fSIntel extern struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS];
372af75078fSIntel 
37357e85242SBruce Richardson extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */
37457e85242SBruce Richardson extern uint32_t burst_tx_retry_num;  /**< Burst tx retry number for mac-retry. */
37557e85242SBruce Richardson 
376af75078fSIntel static inline unsigned int
377af75078fSIntel lcore_num(void)
378af75078fSIntel {
379af75078fSIntel 	unsigned int i;
380af75078fSIntel 
381af75078fSIntel 	for (i = 0; i < RTE_MAX_LCORE; ++i)
382af75078fSIntel 		if (fwd_lcores_cpuids[i] == rte_lcore_id())
383af75078fSIntel 			return i;
384af75078fSIntel 
385af75078fSIntel 	rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n");
386af75078fSIntel }
387af75078fSIntel 
388af75078fSIntel static inline struct fwd_lcore *
389af75078fSIntel current_fwd_lcore(void)
390af75078fSIntel {
391af75078fSIntel 	return fwd_lcores[lcore_num()];
392af75078fSIntel }
393af75078fSIntel 
394af75078fSIntel /* Mbuf Pools */
395af75078fSIntel static inline void
396af75078fSIntel mbuf_poolname_build(unsigned int sock_id, char* mp_name, int name_size)
397af75078fSIntel {
398af75078fSIntel 	rte_snprintf(mp_name, name_size, "mbuf_pool_socket_%u", sock_id);
399af75078fSIntel }
400af75078fSIntel 
401af75078fSIntel static inline struct rte_mempool *
402af75078fSIntel mbuf_pool_find(unsigned int sock_id)
403af75078fSIntel {
404af75078fSIntel 	char pool_name[RTE_MEMPOOL_NAMESIZE];
405af75078fSIntel 
406af75078fSIntel 	mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name));
407af75078fSIntel 	return (rte_mempool_lookup((const char *)pool_name));
408af75078fSIntel }
409af75078fSIntel 
410af75078fSIntel /**
411af75078fSIntel  * Read/Write operations on a PCI register of a port.
412af75078fSIntel  */
413af75078fSIntel static inline uint32_t
414af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off)
415af75078fSIntel {
416af75078fSIntel 	void *reg_addr;
417af75078fSIntel 	uint32_t reg_v;
418af75078fSIntel 
419eee16c96SStephen Hemminger 	reg_addr = (void *)
420eee16c96SStephen Hemminger 		((char *)port->dev_info.pci_dev->mem_resource[0].addr +
421af75078fSIntel 			reg_off);
422af75078fSIntel 	reg_v = *((volatile uint32_t *)reg_addr);
423af75078fSIntel 	return rte_le_to_cpu_32(reg_v);
424af75078fSIntel }
425af75078fSIntel 
426af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \
427af75078fSIntel 	port_pci_reg_read(&ports[(pt_id)], (reg_off))
428af75078fSIntel 
429af75078fSIntel static inline void
430af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v)
431af75078fSIntel {
432af75078fSIntel 	void *reg_addr;
433af75078fSIntel 
434eee16c96SStephen Hemminger 	reg_addr = (void *)
435eee16c96SStephen Hemminger 		((char *)port->dev_info.pci_dev->mem_resource[0].addr +
436af75078fSIntel 			reg_off);
437af75078fSIntel 	*((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v);
438af75078fSIntel }
439af75078fSIntel 
440af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \
441af75078fSIntel 	port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value))
442af75078fSIntel 
443af75078fSIntel /* Prototypes */
444af75078fSIntel void launch_args_parse(int argc, char** argv);
445af75078fSIntel void prompt(void);
446af75078fSIntel void nic_stats_display(portid_t port_id);
447af75078fSIntel void nic_stats_clear(portid_t port_id);
448ed30d9b6SIntel void nic_stats_mapping_display(portid_t port_id);
449af75078fSIntel void port_infos_display(portid_t port_id);
450af75078fSIntel void fwd_lcores_config_display(void);
451af75078fSIntel void fwd_config_display(void);
452af75078fSIntel void rxtx_config_display(void);
453af75078fSIntel void fwd_config_setup(void);
454af75078fSIntel void set_def_fwd_config(void);
455013af9b6SIntel int init_fwd_streams(void);
456013af9b6SIntel 
457af75078fSIntel 
458af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos);
459af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos,
460af75078fSIntel 		      uint8_t bit_v);
461af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off,
462af75078fSIntel 				uint8_t bit1_pos, uint8_t bit2_pos);
463af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off,
464af75078fSIntel 			    uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value);
465af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off);
466af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value);
467af75078fSIntel 
468af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id);
469af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id);
470af75078fSIntel 
471013af9b6SIntel int set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc);
472013af9b6SIntel int set_fwd_lcores_mask(uint64_t lcoremask);
473af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc);
474af75078fSIntel 
475af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt);
476af75078fSIntel void set_fwd_ports_mask(uint64_t portmask);
477af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt);
478af75078fSIntel 
479a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on);
480a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on);
481a47aa8b9SIntel 
482a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on);
483af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on);
484a47aa8b9SIntel void rx_vft_set(portid_t port_id, uint16_t vlan_id, int on);
485a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on);
486a47aa8b9SIntel void vlan_tpid_set(portid_t port_id, uint16_t tp_id);
487af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id);
488af75078fSIntel void tx_vlan_reset(portid_t port_id);
489af75078fSIntel 
490ed30d9b6SIntel 
491ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value);
492ed30d9b6SIntel 
493af75078fSIntel void tx_cksum_set(portid_t port_id, uint8_t cksum_mask);
494af75078fSIntel 
495af75078fSIntel void set_verbose_level(uint16_t vb_level);
496af75078fSIntel void set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs);
497af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst);
498769ce6b1SThomas Monjalon char *list_pkt_forwarding_modes(void);
499af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode);
500af75078fSIntel void start_packet_forwarding(int with_tx_first);
501af75078fSIntel void stop_packet_forwarding(void);
502*cfae07fdSOuyang Changchun void dev_set_link_up(portid_t pid);
503*cfae07fdSOuyang Changchun void dev_set_link_down(portid_t pid);
504ce8d5614SIntel void init_port_config(void);
505900550deSIntel int init_port_dcb_config(portid_t pid,struct dcb_config *dcb_conf);
506148f963fSBruce Richardson int start_port(portid_t pid);
507ce8d5614SIntel void stop_port(portid_t pid);
508ce8d5614SIntel void close_port(portid_t pid);
509ce8d5614SIntel int all_ports_stopped(void);
510af75078fSIntel void pmd_test_exit(void);
511af75078fSIntel 
512af75078fSIntel void fdir_add_signature_filter(portid_t port_id, uint8_t queue_id,
513af75078fSIntel 			       struct rte_fdir_filter *fdir_filter);
514af75078fSIntel void fdir_update_signature_filter(portid_t port_id, uint8_t queue_id,
515af75078fSIntel 				  struct rte_fdir_filter *fdir_filter);
516af75078fSIntel void fdir_remove_signature_filter(portid_t port_id,
517af75078fSIntel 				  struct rte_fdir_filter *fdir_filter);
518af75078fSIntel void fdir_get_infos(portid_t port_id);
519af75078fSIntel void fdir_add_perfect_filter(portid_t port_id, uint16_t soft_id,
520af75078fSIntel 			     uint8_t queue_id, uint8_t drop,
521af75078fSIntel 			     struct rte_fdir_filter *fdir_filter);
522af75078fSIntel void fdir_update_perfect_filter(portid_t port_id, uint16_t soft_id,
523af75078fSIntel 				uint8_t queue_id, uint8_t drop,
524af75078fSIntel 				struct rte_fdir_filter *fdir_filter);
525af75078fSIntel void fdir_remove_perfect_filter(portid_t port_id, uint16_t soft_id,
526af75078fSIntel 				struct rte_fdir_filter *fdir_filter);
527af75078fSIntel void fdir_set_masks(portid_t port_id, struct rte_fdir_masks *fdir_masks);
52801a638e1SIntel void port_rss_reta_info(portid_t port_id, struct rte_eth_rss_reta *reta_conf);
5297741e4cfSIntel void set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on);
5307741e4cfSIntel void set_vf_rx_vlan(portid_t port_id, uint16_t vlan_id,
5317741e4cfSIntel 		uint64_t vf_mask, uint8_t on);
532af75078fSIntel 
53316321de0SIvan Boule void port_rss_hash_conf_show(portid_t port_id, int show_rss_key);
534f79959eaSIvan Boule void port_rss_hash_key_update(portid_t port_id, uint8_t *hash_key);
53516321de0SIvan Boule 
536af75078fSIntel /*
537af75078fSIntel  * Work-around of a compilation error with ICC on invocations of the
538af75078fSIntel  * rte_be_to_cpu_16() function.
539af75078fSIntel  */
540af75078fSIntel #ifdef __GCC__
541af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  rte_be_to_cpu_16((be_16_v))
542af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v))
543af75078fSIntel #else
544af75078fSIntel #ifdef __big_endian__
545af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v)  (be_16_v)
546af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v)
547af75078fSIntel #else
548af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \
549af75078fSIntel 	(uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8))
550af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \
551af75078fSIntel 	(uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8))
552af75078fSIntel #endif
553af75078fSIntel #endif /* __GCC__ */
554af75078fSIntel 
555af75078fSIntel #endif /* _TESTPMD_H_ */
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