1af75078fSIntel /*- 2af75078fSIntel * BSD LICENSE 3af75078fSIntel * 4e9d48c00SBruce Richardson * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 5af75078fSIntel * All rights reserved. 6af75078fSIntel * 7af75078fSIntel * Redistribution and use in source and binary forms, with or without 8af75078fSIntel * modification, are permitted provided that the following conditions 9af75078fSIntel * are met: 10af75078fSIntel * 11af75078fSIntel * * Redistributions of source code must retain the above copyright 12af75078fSIntel * notice, this list of conditions and the following disclaimer. 13af75078fSIntel * * Redistributions in binary form must reproduce the above copyright 14af75078fSIntel * notice, this list of conditions and the following disclaimer in 15af75078fSIntel * the documentation and/or other materials provided with the 16af75078fSIntel * distribution. 17af75078fSIntel * * Neither the name of Intel Corporation nor the names of its 18af75078fSIntel * contributors may be used to endorse or promote products derived 19af75078fSIntel * from this software without specific prior written permission. 20af75078fSIntel * 21af75078fSIntel * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22af75078fSIntel * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23af75078fSIntel * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24af75078fSIntel * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25af75078fSIntel * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26af75078fSIntel * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27af75078fSIntel * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28af75078fSIntel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29af75078fSIntel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30af75078fSIntel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31af75078fSIntel * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32af75078fSIntel */ 33af75078fSIntel 34af75078fSIntel #ifndef _TESTPMD_H_ 35af75078fSIntel #define _TESTPMD_H_ 36af75078fSIntel 37af75078fSIntel /* icc on baremetal gives us troubles with function named 'main' */ 38af75078fSIntel #ifdef RTE_EXEC_ENV_BAREMETAL 39af75078fSIntel #define main _main 40af75078fSIntel int main(int argc, char **argv); 41af75078fSIntel #endif 42af75078fSIntel 43ce8d5614SIntel #define RTE_PORT_ALL (~(portid_t)0x0) 44ce8d5614SIntel 45ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX 2048 46ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX 2048 47ce8d5614SIntel 48ce8d5614SIntel #define RTE_PORT_STOPPED (uint16_t)0 49ce8d5614SIntel #define RTE_PORT_STARTED (uint16_t)1 50ce8d5614SIntel #define RTE_PORT_CLOSED (uint16_t)2 51ce8d5614SIntel #define RTE_PORT_HANDLING (uint16_t)3 52ce8d5614SIntel 53af75078fSIntel /* 54af75078fSIntel * Default size of the mbuf data buffer to receive standard 1518-byte 55af75078fSIntel * Ethernet frames in a mono-segment memory buffer. 56af75078fSIntel */ 57af75078fSIntel #define DEFAULT_MBUF_DATA_SIZE 2048 /**< Default size of mbuf data buffer. */ 58af75078fSIntel 59af75078fSIntel /* 60af75078fSIntel * The maximum number of segments per packet is used when creating 61af75078fSIntel * scattered transmit packets composed of a list of mbufs. 62af75078fSIntel */ 63ea672a8bSOlivier Matz #define RTE_MAX_SEGS_PER_PKT 255 /**< nb_segs is a 8-bit unsigned char. */ 64af75078fSIntel 65af75078fSIntel #define MAX_PKT_BURST 512 66836853d3SCunming Liang #define DEF_PKT_BURST 32 67af75078fSIntel 68e9378bbcSCunming Liang #define DEF_MBUF_CACHE 250 69e9378bbcSCunming Liang 70af75078fSIntel #define CACHE_LINE_SIZE_ROUNDUP(size) \ 71af75078fSIntel (CACHE_LINE_SIZE * ((size + CACHE_LINE_SIZE - 1) / CACHE_LINE_SIZE)) 72af75078fSIntel 73b6ea6408SIntel #define NUMA_NO_CONFIG 0xFF 74b6ea6408SIntel #define UMA_NO_CONFIG 0xFF 75b6ea6408SIntel 76af75078fSIntel typedef uint8_t lcoreid_t; 77af75078fSIntel typedef uint8_t portid_t; 78af75078fSIntel typedef uint16_t queueid_t; 79af75078fSIntel typedef uint16_t streamid_t; 80af75078fSIntel 81af75078fSIntel #define MAX_QUEUE_ID ((1 << (sizeof(queueid_t) * 8)) - 1) 82af75078fSIntel 83af75078fSIntel enum { 84af75078fSIntel PORT_TOPOLOGY_PAIRED, 853e2006d6SCyril Chemparathy PORT_TOPOLOGY_CHAINED, 863e2006d6SCyril Chemparathy PORT_TOPOLOGY_LOOP, 87af75078fSIntel }; 88af75078fSIntel 89af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 90af75078fSIntel /** 91af75078fSIntel * The data structure associated with RX and TX packet burst statistics 92af75078fSIntel * that are recorded for each forwarding stream. 93af75078fSIntel */ 94af75078fSIntel struct pkt_burst_stats { 95af75078fSIntel unsigned int pkt_burst_spread[MAX_PKT_BURST]; 96af75078fSIntel }; 97af75078fSIntel #endif 98af75078fSIntel 99af75078fSIntel /** 100af75078fSIntel * The data structure associated with a forwarding stream between a receive 101af75078fSIntel * port/queue and a transmit port/queue. 102af75078fSIntel */ 103af75078fSIntel struct fwd_stream { 104af75078fSIntel /* "read-only" data */ 105af75078fSIntel portid_t rx_port; /**< port to poll for received packets */ 106af75078fSIntel queueid_t rx_queue; /**< RX queue to poll on "rx_port" */ 107af75078fSIntel portid_t tx_port; /**< forwarding port of received packets */ 108af75078fSIntel queueid_t tx_queue; /**< TX queue to send forwarded packets */ 109af75078fSIntel streamid_t peer_addr; /**< index of peer ethernet address of packets */ 110af75078fSIntel 111af75078fSIntel /* "read-write" results */ 112af75078fSIntel unsigned int rx_packets; /**< received packets */ 113af75078fSIntel unsigned int tx_packets; /**< received packets transmitted */ 114af75078fSIntel unsigned int fwd_dropped; /**< received packets not forwarded */ 115af75078fSIntel unsigned int rx_bad_ip_csum ; /**< received packets has bad ip checksum */ 116af75078fSIntel unsigned int rx_bad_l4_csum ; /**< received packets has bad l4 checksum */ 117af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 118af75078fSIntel uint64_t core_cycles; /**< used for RX and TX processing */ 119af75078fSIntel #endif 120af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 121af75078fSIntel struct pkt_burst_stats rx_burst_stats; 122af75078fSIntel struct pkt_burst_stats tx_burst_stats; 123af75078fSIntel #endif 124af75078fSIntel }; 125af75078fSIntel 126*cf543fdbSOlivier Matz /** Offload IP checksum in csum forward engine */ 127*cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_IP_CKSUM 0x0001 128*cf543fdbSOlivier Matz /** Offload UDP checksum in csum forward engine */ 129*cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_UDP_CKSUM 0x0002 130*cf543fdbSOlivier Matz /** Offload TCP checksum in csum forward engine */ 131*cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_TCP_CKSUM 0x0004 132*cf543fdbSOlivier Matz /** Offload SCTP checksum in csum forward engine */ 133*cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_SCTP_CKSUM 0x0008 134*cf543fdbSOlivier Matz /** Offload inner IP checksum in csum forward engine */ 135*cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_INNER_IP_CKSUM 0x0010 136*cf543fdbSOlivier Matz /** Offload inner UDP checksum in csum forward engine */ 137*cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_INNER_UDP_CKSUM 0x0020 138*cf543fdbSOlivier Matz /** Offload inner TCP checksum in csum forward engine */ 139*cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_INNER_TCP_CKSUM 0x0040 140*cf543fdbSOlivier Matz /** Offload inner SCTP checksum in csum forward engine */ 141*cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_INNER_SCTP_CKSUM 0x0080 142*cf543fdbSOlivier Matz /** Offload inner IP checksum mask */ 143*cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_INNER_CKSUM_MASK 0x00F0 144*cf543fdbSOlivier Matz /** Insert VLAN header in forward engine */ 145*cf543fdbSOlivier Matz #define TESTPMD_TX_OFFLOAD_INSERT_VLAN 0x0100 146af75078fSIntel /** 147af75078fSIntel * The data structure associated with each port. 148af75078fSIntel */ 149af75078fSIntel struct rte_port { 150af75078fSIntel struct rte_eth_dev_info dev_info; /**< PCI info + driver name */ 151af75078fSIntel struct rte_eth_conf dev_conf; /**< Port configuration. */ 152af75078fSIntel struct ether_addr eth_addr; /**< Port ethernet address */ 153af75078fSIntel struct rte_eth_stats stats; /**< Last port statistics */ 154af75078fSIntel uint64_t tx_dropped; /**< If no descriptor in TX ring */ 155af75078fSIntel struct fwd_stream *rx_stream; /**< Port RX stream, if unique */ 156af75078fSIntel struct fwd_stream *tx_stream; /**< Port TX stream, if unique */ 157af75078fSIntel unsigned int socket_id; /**< For NUMA support */ 158*cf543fdbSOlivier Matz uint16_t tx_ol_flags;/**< TX Offload Flags (TESTPMD_TX_OFFLOAD...). */ 159af75078fSIntel uint16_t tx_vlan_id; /**< Tag Id. in TX VLAN packets. */ 160af75078fSIntel void *fwd_ctx; /**< Forwarding mode context */ 161af75078fSIntel uint64_t rx_bad_ip_csum; /**< rx pkts with bad ip checksum */ 162af75078fSIntel uint64_t rx_bad_l4_csum; /**< rx pkts with bad l4 checksum */ 163ed30d9b6SIntel uint8_t tx_queue_stats_mapping_enabled; 164ed30d9b6SIntel uint8_t rx_queue_stats_mapping_enabled; 165ce8d5614SIntel volatile uint16_t port_status; /**< port started or not */ 166ce8d5614SIntel uint8_t need_reconfig; /**< need reconfiguring port or not */ 167ce8d5614SIntel uint8_t need_reconfig_queues; /**< need reconfiguring queues or not */ 168ce8d5614SIntel uint8_t rss_flag; /**< enable rss or not */ 1697741e4cfSIntel uint8_t dcb_flag; /**< enable dcb */ 170ce8d5614SIntel struct rte_eth_rxconf rx_conf; /**< rx configuration */ 171ce8d5614SIntel struct rte_eth_txconf tx_conf; /**< tx configuration */ 172af75078fSIntel }; 173af75078fSIntel 174af75078fSIntel /** 175af75078fSIntel * The data structure associated with each forwarding logical core. 176af75078fSIntel * The logical cores are internally numbered by a core index from 0 to 177af75078fSIntel * the maximum number of logical cores - 1. 178af75078fSIntel * The system CPU identifier of all logical cores are setup in a global 179af75078fSIntel * CPU id. configuration table. 180af75078fSIntel */ 181af75078fSIntel struct fwd_lcore { 182af75078fSIntel struct rte_mempool *mbp; /**< The mbuf pool to use by this core */ 183af75078fSIntel streamid_t stream_idx; /**< index of 1st stream in "fwd_streams" */ 184af75078fSIntel streamid_t stream_nb; /**< number of streams in "fwd_streams" */ 185af75078fSIntel lcoreid_t cpuid_idx; /**< index of logical core in CPU id table */ 186af75078fSIntel queueid_t tx_queue; /**< TX queue to send forwarded packets */ 187af75078fSIntel volatile char stopped; /**< stop forwarding when set */ 188af75078fSIntel }; 189af75078fSIntel 190af75078fSIntel /* 191af75078fSIntel * Forwarding mode operations: 192af75078fSIntel * - IO forwarding mode (default mode) 193af75078fSIntel * Forwards packets unchanged. 194af75078fSIntel * 195af75078fSIntel * - MAC forwarding mode 196af75078fSIntel * Set the source and the destination Ethernet addresses of packets 197af75078fSIntel * before forwarding them. 198af75078fSIntel * 199af75078fSIntel * - IEEE1588 forwarding mode 200af75078fSIntel * Check that received IEEE1588 Precise Time Protocol (PTP) packets are 201af75078fSIntel * filtered and timestamped by the hardware. 202af75078fSIntel * Forwards packets unchanged on the same port. 203af75078fSIntel * Check that sent IEEE1588 PTP packets are timestamped by the hardware. 204af75078fSIntel */ 205af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi); 206af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi); 207af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs); 208af75078fSIntel 209af75078fSIntel struct fwd_engine { 210af75078fSIntel const char *fwd_mode_name; /**< Forwarding mode name. */ 211af75078fSIntel port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */ 212af75078fSIntel port_fwd_end_t port_fwd_end; /**< NULL if nothing special to do. */ 213af75078fSIntel packet_fwd_t packet_fwd; /**< Mandatory. */ 214af75078fSIntel }; 215af75078fSIntel 216af75078fSIntel extern struct fwd_engine io_fwd_engine; 217af75078fSIntel extern struct fwd_engine mac_fwd_engine; 21857e85242SBruce Richardson extern struct fwd_engine mac_retry_fwd_engine; 219d47388f1SCyril Chemparathy extern struct fwd_engine mac_swap_engine; 220e9e23a61SCyril Chemparathy extern struct fwd_engine flow_gen_engine; 221af75078fSIntel extern struct fwd_engine rx_only_engine; 222af75078fSIntel extern struct fwd_engine tx_only_engine; 223af75078fSIntel extern struct fwd_engine csum_fwd_engine; 224168dfa61SIvan Boule extern struct fwd_engine icmp_echo_engine; 225af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588 226af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine; 227af75078fSIntel #endif 228af75078fSIntel 229af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */ 230af75078fSIntel 231af75078fSIntel /** 232af75078fSIntel * Forwarding Configuration 233af75078fSIntel * 234af75078fSIntel */ 235af75078fSIntel struct fwd_config { 236af75078fSIntel struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */ 237af75078fSIntel streamid_t nb_fwd_streams; /**< Nb. of forward streams to process. */ 238af75078fSIntel lcoreid_t nb_fwd_lcores; /**< Nb. of logical cores to launch. */ 239af75078fSIntel portid_t nb_fwd_ports; /**< Nb. of ports involved. */ 240af75078fSIntel }; 241af75078fSIntel 242900550deSIntel /** 243900550deSIntel * DCB mode enable 244900550deSIntel */ 245900550deSIntel enum dcb_mode_enable 246900550deSIntel { 247900550deSIntel DCB_VT_ENABLED, 248900550deSIntel DCB_ENABLED 249900550deSIntel }; 250900550deSIntel 251900550deSIntel /* 252900550deSIntel * DCB general config info 253900550deSIntel */ 254900550deSIntel struct dcb_config { 255900550deSIntel enum dcb_mode_enable dcb_mode; 256900550deSIntel uint8_t vt_en; 257900550deSIntel enum rte_eth_nb_tcs num_tcs; 258900550deSIntel uint8_t pfc_en; 259900550deSIntel }; 260900550deSIntel 261900550deSIntel /* 262900550deSIntel * In DCB io FWD mode, 128 RX queue to 128 TX queue mapping 263900550deSIntel */ 264900550deSIntel enum dcb_queue_mapping_mode { 265900550deSIntel DCB_VT_Q_MAPPING = 0, 266900550deSIntel DCB_4_TCS_Q_MAPPING, 267900550deSIntel DCB_8_TCS_Q_MAPPING 268900550deSIntel }; 269900550deSIntel 270ed30d9b6SIntel #define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */ 271ed30d9b6SIntel #define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */ 272ed30d9b6SIntel 273ed30d9b6SIntel struct queue_stats_mappings { 274ed30d9b6SIntel uint8_t port_id; 275ed30d9b6SIntel uint16_t queue_id; 276ed30d9b6SIntel uint8_t stats_counter_id; 277ed30d9b6SIntel } __rte_cache_aligned; 278ed30d9b6SIntel 279ed30d9b6SIntel extern struct queue_stats_mappings tx_queue_stats_mappings_array[]; 280ed30d9b6SIntel extern struct queue_stats_mappings rx_queue_stats_mappings_array[]; 281ed30d9b6SIntel 282ed30d9b6SIntel /* Assign both tx and rx queue stats mappings to the same default values */ 283ed30d9b6SIntel extern struct queue_stats_mappings *tx_queue_stats_mappings; 284ed30d9b6SIntel extern struct queue_stats_mappings *rx_queue_stats_mappings; 285ed30d9b6SIntel 286ed30d9b6SIntel extern uint16_t nb_tx_queue_stats_mappings; 287ed30d9b6SIntel extern uint16_t nb_rx_queue_stats_mappings; 288ed30d9b6SIntel 289af75078fSIntel /* globals used for configuration */ 290af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */ 291af75078fSIntel extern uint8_t interactive; 292ca7feb22SCyril Chemparathy extern uint8_t auto_start; 293af75078fSIntel extern uint8_t numa_support; /**< set by "--numa" parameter */ 294af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */ 2957741e4cfSIntel extern uint8_t no_flush_rx; /**<set by "--no-flush-rx" parameter */ 296148f963fSBruce Richardson extern uint8_t mp_anon; /**< set by "--mp-anon" parameter */ 297bc202406SDavid Marchand extern uint8_t no_link_check; /**<set by "--disable-link-check" parameter */ 2982950a769SDeclan Doherty extern volatile int test_done; /* stop packet forwarding when set to 1. */ 299af75078fSIntel 3007b7e5ba7SIntel #ifdef RTE_NIC_BYPASS 3017b7e5ba7SIntel extern uint32_t bypass_timeout; /**< Store the NIC bypass watchdog timeout */ 3027b7e5ba7SIntel #endif 3037b7e5ba7SIntel 304b6ea6408SIntel #define MAX_SOCKET 2 /*MAX SOCKET:currently, it is 2 */ 305b6ea6408SIntel 306b6ea6408SIntel /* 307b6ea6408SIntel * Store specified sockets on which memory pool to be used by ports 308b6ea6408SIntel * is allocated. 309b6ea6408SIntel */ 310b6ea6408SIntel uint8_t port_numa[RTE_MAX_ETHPORTS]; 311b6ea6408SIntel 312b6ea6408SIntel /* 313b6ea6408SIntel * Store specified sockets on which RX ring to be used by ports 314b6ea6408SIntel * is allocated. 315b6ea6408SIntel */ 316b6ea6408SIntel uint8_t rxring_numa[RTE_MAX_ETHPORTS]; 317b6ea6408SIntel 318b6ea6408SIntel /* 319b6ea6408SIntel * Store specified sockets on which TX ring to be used by ports 320b6ea6408SIntel * is allocated. 321b6ea6408SIntel */ 322b6ea6408SIntel uint8_t txring_numa[RTE_MAX_ETHPORTS]; 323b6ea6408SIntel 324b6ea6408SIntel extern uint8_t socket_num; 325b6ea6408SIntel 326af75078fSIntel /* 327af75078fSIntel * Configuration of logical cores: 328af75078fSIntel * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores 329af75078fSIntel */ 330af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */ 331af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */ 332af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */ 333af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE]; 334af75078fSIntel 335af75078fSIntel /* 336af75078fSIntel * Configuration of Ethernet ports: 337af75078fSIntel * nb_fwd_ports <= nb_cfg_ports <= nb_ports 338af75078fSIntel */ 339af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */ 340af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */ 341af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */ 342af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS]; 343af75078fSIntel extern struct rte_port *ports; 344af75078fSIntel 345af75078fSIntel extern struct rte_eth_rxmode rx_mode; 3468a387fa8SHelin Zhang extern uint64_t rss_hf; 347af75078fSIntel 348af75078fSIntel extern queueid_t nb_rxq; 349af75078fSIntel extern queueid_t nb_txq; 350af75078fSIntel 351af75078fSIntel extern uint16_t nb_rxd; 352af75078fSIntel extern uint16_t nb_txd; 353af75078fSIntel 354af75078fSIntel extern uint16_t rx_free_thresh; 355ce8d5614SIntel extern uint8_t rx_drop_en; 356af75078fSIntel extern uint16_t tx_free_thresh; 357af75078fSIntel extern uint16_t tx_rs_thresh; 358ce8d5614SIntel extern uint32_t txq_flags; 359af75078fSIntel 360900550deSIntel extern uint8_t dcb_config; 361900550deSIntel extern uint8_t dcb_test; 362900550deSIntel extern enum dcb_queue_mapping_mode dcb_q_mapping; 363900550deSIntel 364af75078fSIntel extern uint16_t mbuf_data_size; /**< Mbuf data space size. */ 365c8798818SIntel extern uint32_t param_total_num_mbufs; 366af75078fSIntel 367af75078fSIntel extern struct rte_fdir_conf fdir_conf; 368af75078fSIntel 369af75078fSIntel /* 370af75078fSIntel * Configuration of packet segments used by the "txonly" processing engine. 371af75078fSIntel */ 372af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64 373af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */ 374af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */ 375af75078fSIntel extern uint8_t tx_pkt_nb_segs; /**< Number of segments in TX packets */ 376af75078fSIntel 377af75078fSIntel extern uint16_t nb_pkt_per_burst; 378af75078fSIntel extern uint16_t mb_mempool_cache; 379af75078fSIntel extern struct rte_eth_thresh rx_thresh; 380af75078fSIntel extern struct rte_eth_thresh tx_thresh; 381af75078fSIntel 382af75078fSIntel extern struct fwd_config cur_fwd_config; 383af75078fSIntel extern struct fwd_engine *cur_fwd_eng; 384af75078fSIntel extern struct fwd_lcore **fwd_lcores; 385af75078fSIntel extern struct fwd_stream **fwd_streams; 386af75078fSIntel 387af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */ 388af75078fSIntel extern struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS]; 389af75078fSIntel 39057e85242SBruce Richardson extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */ 39157e85242SBruce Richardson extern uint32_t burst_tx_retry_num; /**< Burst tx retry number for mac-retry. */ 39257e85242SBruce Richardson 393af75078fSIntel static inline unsigned int 394af75078fSIntel lcore_num(void) 395af75078fSIntel { 396af75078fSIntel unsigned int i; 397af75078fSIntel 398af75078fSIntel for (i = 0; i < RTE_MAX_LCORE; ++i) 399af75078fSIntel if (fwd_lcores_cpuids[i] == rte_lcore_id()) 400af75078fSIntel return i; 401af75078fSIntel 402af75078fSIntel rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n"); 403af75078fSIntel } 404af75078fSIntel 405af75078fSIntel static inline struct fwd_lcore * 406af75078fSIntel current_fwd_lcore(void) 407af75078fSIntel { 408af75078fSIntel return fwd_lcores[lcore_num()]; 409af75078fSIntel } 410af75078fSIntel 411af75078fSIntel /* Mbuf Pools */ 412af75078fSIntel static inline void 413af75078fSIntel mbuf_poolname_build(unsigned int sock_id, char* mp_name, int name_size) 414af75078fSIntel { 4156f41fe75SStephen Hemminger snprintf(mp_name, name_size, "mbuf_pool_socket_%u", sock_id); 416af75078fSIntel } 417af75078fSIntel 418af75078fSIntel static inline struct rte_mempool * 419af75078fSIntel mbuf_pool_find(unsigned int sock_id) 420af75078fSIntel { 421af75078fSIntel char pool_name[RTE_MEMPOOL_NAMESIZE]; 422af75078fSIntel 423af75078fSIntel mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name)); 424af75078fSIntel return (rte_mempool_lookup((const char *)pool_name)); 425af75078fSIntel } 426af75078fSIntel 427af75078fSIntel /** 428af75078fSIntel * Read/Write operations on a PCI register of a port. 429af75078fSIntel */ 430af75078fSIntel static inline uint32_t 431af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off) 432af75078fSIntel { 433af75078fSIntel void *reg_addr; 434af75078fSIntel uint32_t reg_v; 435af75078fSIntel 436eee16c96SStephen Hemminger reg_addr = (void *) 437eee16c96SStephen Hemminger ((char *)port->dev_info.pci_dev->mem_resource[0].addr + 438af75078fSIntel reg_off); 439af75078fSIntel reg_v = *((volatile uint32_t *)reg_addr); 440af75078fSIntel return rte_le_to_cpu_32(reg_v); 441af75078fSIntel } 442af75078fSIntel 443af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \ 444af75078fSIntel port_pci_reg_read(&ports[(pt_id)], (reg_off)) 445af75078fSIntel 446af75078fSIntel static inline void 447af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v) 448af75078fSIntel { 449af75078fSIntel void *reg_addr; 450af75078fSIntel 451eee16c96SStephen Hemminger reg_addr = (void *) 452eee16c96SStephen Hemminger ((char *)port->dev_info.pci_dev->mem_resource[0].addr + 453af75078fSIntel reg_off); 454af75078fSIntel *((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v); 455af75078fSIntel } 456af75078fSIntel 457af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \ 458af75078fSIntel port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value)) 459af75078fSIntel 460af75078fSIntel /* Prototypes */ 461af75078fSIntel void launch_args_parse(int argc, char** argv); 462af75078fSIntel void prompt(void); 463af75078fSIntel void nic_stats_display(portid_t port_id); 464af75078fSIntel void nic_stats_clear(portid_t port_id); 465bfd5051bSOlivier Matz void nic_xstats_display(portid_t port_id); 466bfd5051bSOlivier Matz void nic_xstats_clear(portid_t port_id); 467ed30d9b6SIntel void nic_stats_mapping_display(portid_t port_id); 468af75078fSIntel void port_infos_display(portid_t port_id); 469af75078fSIntel void fwd_lcores_config_display(void); 470af75078fSIntel void fwd_config_display(void); 471af75078fSIntel void rxtx_config_display(void); 472af75078fSIntel void fwd_config_setup(void); 473af75078fSIntel void set_def_fwd_config(void); 474a21d5a4bSDeclan Doherty void reconfig(portid_t new_port_id, unsigned socket_id); 475013af9b6SIntel int init_fwd_streams(void); 476013af9b6SIntel 477ae03d0d1SIvan Boule void port_mtu_set(portid_t port_id, uint16_t mtu); 478af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos); 479af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos, 480af75078fSIntel uint8_t bit_v); 481af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off, 482af75078fSIntel uint8_t bit1_pos, uint8_t bit2_pos); 483af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off, 484af75078fSIntel uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value); 485af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off); 486af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value); 487af75078fSIntel 488af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id); 489af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id); 490af75078fSIntel 491013af9b6SIntel int set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc); 492013af9b6SIntel int set_fwd_lcores_mask(uint64_t lcoremask); 493af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc); 494af75078fSIntel 495af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt); 496af75078fSIntel void set_fwd_ports_mask(uint64_t portmask); 497af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt); 498af75078fSIntel 499a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on); 500a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on); 501a47aa8b9SIntel 502a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on); 503af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on); 504a47aa8b9SIntel void rx_vft_set(portid_t port_id, uint16_t vlan_id, int on); 505a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on); 506a47aa8b9SIntel void vlan_tpid_set(portid_t port_id, uint16_t tp_id); 507af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id); 508af75078fSIntel void tx_vlan_reset(portid_t port_id); 509529ba951SHelin Zhang void tx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on); 510ed30d9b6SIntel 511ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value); 512ed30d9b6SIntel 5134332beeeSBruce Richardson void tx_cksum_set(portid_t port_id, uint64_t ol_flags); 514af75078fSIntel 515af75078fSIntel void set_verbose_level(uint16_t vb_level); 516af75078fSIntel void set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs); 517af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst); 518769ce6b1SThomas Monjalon char *list_pkt_forwarding_modes(void); 519af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode); 520af75078fSIntel void start_packet_forwarding(int with_tx_first); 521af75078fSIntel void stop_packet_forwarding(void); 522cfae07fdSOuyang Changchun void dev_set_link_up(portid_t pid); 523cfae07fdSOuyang Changchun void dev_set_link_down(portid_t pid); 524ce8d5614SIntel void init_port_config(void); 525900550deSIntel int init_port_dcb_config(portid_t pid,struct dcb_config *dcb_conf); 526148f963fSBruce Richardson int start_port(portid_t pid); 527ce8d5614SIntel void stop_port(portid_t pid); 528ce8d5614SIntel void close_port(portid_t pid); 529ce8d5614SIntel int all_ports_stopped(void); 5305f4ec54fSChen Jing D(Mark) int port_is_started(portid_t port_id); 531af75078fSIntel void pmd_test_exit(void); 532af75078fSIntel 533af75078fSIntel void fdir_add_signature_filter(portid_t port_id, uint8_t queue_id, 534af75078fSIntel struct rte_fdir_filter *fdir_filter); 535af75078fSIntel void fdir_update_signature_filter(portid_t port_id, uint8_t queue_id, 536af75078fSIntel struct rte_fdir_filter *fdir_filter); 537af75078fSIntel void fdir_remove_signature_filter(portid_t port_id, 538af75078fSIntel struct rte_fdir_filter *fdir_filter); 539af75078fSIntel void fdir_get_infos(portid_t port_id); 540af75078fSIntel void fdir_add_perfect_filter(portid_t port_id, uint16_t soft_id, 541af75078fSIntel uint8_t queue_id, uint8_t drop, 542af75078fSIntel struct rte_fdir_filter *fdir_filter); 543af75078fSIntel void fdir_update_perfect_filter(portid_t port_id, uint16_t soft_id, 544af75078fSIntel uint8_t queue_id, uint8_t drop, 545af75078fSIntel struct rte_fdir_filter *fdir_filter); 546af75078fSIntel void fdir_remove_perfect_filter(portid_t port_id, uint16_t soft_id, 547af75078fSIntel struct rte_fdir_filter *fdir_filter); 548af75078fSIntel void fdir_set_masks(portid_t port_id, struct rte_fdir_masks *fdir_masks); 549aeca06dfSJingjing Wu void fdir_set_flex_mask(portid_t port_id, 550aeca06dfSJingjing Wu struct rte_eth_fdir_flex_mask *cfg); 55197b74464SJingjing Wu void fdir_set_flex_payload(portid_t port_id, 55297b74464SJingjing Wu struct rte_eth_flex_payload_cfg *cfg); 55366c59490SHelin Zhang void port_rss_reta_info(portid_t port_id, 55466c59490SHelin Zhang struct rte_eth_rss_reta_entry64 *reta_conf, 55566c59490SHelin Zhang uint16_t nb_entries); 5566a18e1afSOuyang Changchun 5577741e4cfSIntel void set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on); 5587741e4cfSIntel void set_vf_rx_vlan(portid_t port_id, uint16_t vlan_id, 5597741e4cfSIntel uint64_t vf_mask, uint8_t on); 560af75078fSIntel 5616a18e1afSOuyang Changchun int set_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate); 5626a18e1afSOuyang Changchun int set_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate, 5636a18e1afSOuyang Changchun uint64_t q_msk); 5646a18e1afSOuyang Changchun 56516321de0SIvan Boule void port_rss_hash_conf_show(portid_t port_id, int show_rss_key); 566f79959eaSIvan Boule void port_rss_hash_key_update(portid_t port_id, uint8_t *hash_key); 5670db70a80SJingjing Wu void get_syn_filter(uint8_t port_id); 5680db70a80SJingjing Wu void get_ethertype_filter(uint8_t port_id, uint16_t index); 5690db70a80SJingjing Wu void get_2tuple_filter(uint8_t port_id, uint16_t index); 5700db70a80SJingjing Wu void get_5tuple_filter(uint8_t port_id, uint16_t index); 5710db70a80SJingjing Wu void get_flex_filter(uint8_t port_id, uint16_t index); 5725f4ec54fSChen Jing D(Mark) int port_id_is_invalid(portid_t port_id); 5735f4ec54fSChen Jing D(Mark) int rx_queue_id_is_invalid(queueid_t rxq_id); 5745f4ec54fSChen Jing D(Mark) int tx_queue_id_is_invalid(queueid_t txq_id); 57516321de0SIvan Boule 576af75078fSIntel /* 577af75078fSIntel * Work-around of a compilation error with ICC on invocations of the 578af75078fSIntel * rte_be_to_cpu_16() function. 579af75078fSIntel */ 580af75078fSIntel #ifdef __GCC__ 581af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) rte_be_to_cpu_16((be_16_v)) 582af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v)) 583af75078fSIntel #else 584af75078fSIntel #ifdef __big_endian__ 585af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) (be_16_v) 586af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v) 587af75078fSIntel #else 588af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \ 589af75078fSIntel (uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8)) 590af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \ 591af75078fSIntel (uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8)) 592af75078fSIntel #endif 593af75078fSIntel #endif /* __GCC__ */ 594af75078fSIntel 595af75078fSIntel #endif /* _TESTPMD_H_ */ 596