1af75078fSIntel /*- 2af75078fSIntel * BSD LICENSE 3af75078fSIntel * 4af75078fSIntel * Copyright(c) 2010-2012 Intel Corporation. All rights reserved. 5af75078fSIntel * All rights reserved. 6af75078fSIntel * 7af75078fSIntel * Redistribution and use in source and binary forms, with or without 8af75078fSIntel * modification, are permitted provided that the following conditions 9af75078fSIntel * are met: 10af75078fSIntel * 11af75078fSIntel * * Redistributions of source code must retain the above copyright 12af75078fSIntel * notice, this list of conditions and the following disclaimer. 13af75078fSIntel * * Redistributions in binary form must reproduce the above copyright 14af75078fSIntel * notice, this list of conditions and the following disclaimer in 15af75078fSIntel * the documentation and/or other materials provided with the 16af75078fSIntel * distribution. 17af75078fSIntel * * Neither the name of Intel Corporation nor the names of its 18af75078fSIntel * contributors may be used to endorse or promote products derived 19af75078fSIntel * from this software without specific prior written permission. 20af75078fSIntel * 21af75078fSIntel * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22af75078fSIntel * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23af75078fSIntel * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24af75078fSIntel * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25af75078fSIntel * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26af75078fSIntel * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27af75078fSIntel * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28af75078fSIntel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29af75078fSIntel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30af75078fSIntel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31af75078fSIntel * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32af75078fSIntel * 33af75078fSIntel */ 34af75078fSIntel 35af75078fSIntel #ifndef _TESTPMD_H_ 36af75078fSIntel #define _TESTPMD_H_ 37af75078fSIntel 38af75078fSIntel /* icc on baremetal gives us troubles with function named 'main' */ 39af75078fSIntel #ifdef RTE_EXEC_ENV_BAREMETAL 40af75078fSIntel #define main _main 41af75078fSIntel int main(int argc, char **argv); 42af75078fSIntel #endif 43af75078fSIntel 44*ce8d5614SIntel #define RTE_PORT_ALL (~(portid_t)0x0) 45*ce8d5614SIntel 46*ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX 2048 47*ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX 2048 48*ce8d5614SIntel 49*ce8d5614SIntel #define RTE_PORT_STOPPED (uint16_t)0 50*ce8d5614SIntel #define RTE_PORT_STARTED (uint16_t)1 51*ce8d5614SIntel #define RTE_PORT_CLOSED (uint16_t)2 52*ce8d5614SIntel #define RTE_PORT_HANDLING (uint16_t)3 53*ce8d5614SIntel 54af75078fSIntel /* 55af75078fSIntel * Default size of the mbuf data buffer to receive standard 1518-byte 56af75078fSIntel * Ethernet frames in a mono-segment memory buffer. 57af75078fSIntel */ 58af75078fSIntel #define DEFAULT_MBUF_DATA_SIZE 2048 /**< Default size of mbuf data buffer. */ 59af75078fSIntel 60af75078fSIntel /* 61af75078fSIntel * The maximum number of segments per packet is used when creating 62af75078fSIntel * scattered transmit packets composed of a list of mbufs. 63af75078fSIntel */ 64af75078fSIntel #define RTE_MAX_SEGS_PER_PKT 255 /**< pkt.nb_segs is a 8-bit unsigned char. */ 65af75078fSIntel 66af75078fSIntel #define MAX_PKT_BURST 512 67af75078fSIntel #define DEF_PKT_BURST 16 68af75078fSIntel 69af75078fSIntel #define CACHE_LINE_SIZE_ROUNDUP(size) \ 70af75078fSIntel (CACHE_LINE_SIZE * ((size + CACHE_LINE_SIZE - 1) / CACHE_LINE_SIZE)) 71af75078fSIntel 72af75078fSIntel typedef uint8_t lcoreid_t; 73af75078fSIntel typedef uint8_t portid_t; 74af75078fSIntel typedef uint16_t queueid_t; 75af75078fSIntel typedef uint16_t streamid_t; 76af75078fSIntel 77af75078fSIntel #define MAX_QUEUE_ID ((1 << (sizeof(queueid_t) * 8)) - 1) 78af75078fSIntel 79af75078fSIntel enum { 80af75078fSIntel PORT_TOPOLOGY_PAIRED, 81af75078fSIntel PORT_TOPOLOGY_CHAINED 82af75078fSIntel }; 83af75078fSIntel 84af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 85af75078fSIntel /** 86af75078fSIntel * The data structure associated with RX and TX packet burst statistics 87af75078fSIntel * that are recorded for each forwarding stream. 88af75078fSIntel */ 89af75078fSIntel struct pkt_burst_stats { 90af75078fSIntel unsigned int pkt_burst_spread[MAX_PKT_BURST]; 91af75078fSIntel }; 92af75078fSIntel #endif 93af75078fSIntel 94af75078fSIntel /** 95af75078fSIntel * The data structure associated with a forwarding stream between a receive 96af75078fSIntel * port/queue and a transmit port/queue. 97af75078fSIntel */ 98af75078fSIntel struct fwd_stream { 99af75078fSIntel /* "read-only" data */ 100af75078fSIntel portid_t rx_port; /**< port to poll for received packets */ 101af75078fSIntel queueid_t rx_queue; /**< RX queue to poll on "rx_port" */ 102af75078fSIntel portid_t tx_port; /**< forwarding port of received packets */ 103af75078fSIntel queueid_t tx_queue; /**< TX queue to send forwarded packets */ 104af75078fSIntel streamid_t peer_addr; /**< index of peer ethernet address of packets */ 105af75078fSIntel 106af75078fSIntel /* "read-write" results */ 107af75078fSIntel unsigned int rx_packets; /**< received packets */ 108af75078fSIntel unsigned int tx_packets; /**< received packets transmitted */ 109af75078fSIntel unsigned int fwd_dropped; /**< received packets not forwarded */ 110af75078fSIntel unsigned int rx_bad_ip_csum ; /**< received packets has bad ip checksum */ 111af75078fSIntel unsigned int rx_bad_l4_csum ; /**< received packets has bad l4 checksum */ 112af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 113af75078fSIntel uint64_t core_cycles; /**< used for RX and TX processing */ 114af75078fSIntel #endif 115af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 116af75078fSIntel struct pkt_burst_stats rx_burst_stats; 117af75078fSIntel struct pkt_burst_stats tx_burst_stats; 118af75078fSIntel #endif 119af75078fSIntel }; 120af75078fSIntel 121af75078fSIntel /** 122af75078fSIntel * The data structure associated with each port. 123af75078fSIntel * tx_ol_flags is slightly different from ol_flags of rte_mbuf. 124af75078fSIntel * Bit 0: Insert IP checksum 125af75078fSIntel * Bit 1: Insert UDP checksum 126af75078fSIntel * Bit 2: Insert TCP checksum 127af75078fSIntel * Bit 3: Insert SCTP checksum 128af75078fSIntel * Bit 11: Insert VLAN Label 129af75078fSIntel */ 130af75078fSIntel struct rte_port { 131af75078fSIntel struct rte_eth_dev_info dev_info; /**< PCI info + driver name */ 132af75078fSIntel struct rte_eth_conf dev_conf; /**< Port configuration. */ 133af75078fSIntel struct ether_addr eth_addr; /**< Port ethernet address */ 134af75078fSIntel struct rte_eth_stats stats; /**< Last port statistics */ 135af75078fSIntel uint64_t tx_dropped; /**< If no descriptor in TX ring */ 136af75078fSIntel struct fwd_stream *rx_stream; /**< Port RX stream, if unique */ 137af75078fSIntel struct fwd_stream *tx_stream; /**< Port TX stream, if unique */ 138af75078fSIntel unsigned int socket_id; /**< For NUMA support */ 139af75078fSIntel uint16_t tx_ol_flags;/**< Offload Flags of TX packets. */ 140af75078fSIntel uint16_t tx_vlan_id; /**< Tag Id. in TX VLAN packets. */ 141af75078fSIntel void *fwd_ctx; /**< Forwarding mode context */ 142af75078fSIntel uint64_t rx_bad_ip_csum; /**< rx pkts with bad ip checksum */ 143af75078fSIntel uint64_t rx_bad_l4_csum; /**< rx pkts with bad l4 checksum */ 144ed30d9b6SIntel uint8_t tx_queue_stats_mapping_enabled; 145ed30d9b6SIntel uint8_t rx_queue_stats_mapping_enabled; 146*ce8d5614SIntel volatile uint16_t port_status; /**< port started or not */ 147*ce8d5614SIntel uint8_t need_reconfig; /**< need reconfiguring port or not */ 148*ce8d5614SIntel uint8_t need_reconfig_queues; /**< need reconfiguring queues or not */ 149*ce8d5614SIntel uint8_t rss_flag; /**< enable rss or not */ 150*ce8d5614SIntel struct rte_eth_rxconf rx_conf; /**< rx configuration */ 151*ce8d5614SIntel struct rte_eth_txconf tx_conf; /**< tx configuration */ 152af75078fSIntel }; 153af75078fSIntel 154af75078fSIntel /** 155af75078fSIntel * The data structure associated with each forwarding logical core. 156af75078fSIntel * The logical cores are internally numbered by a core index from 0 to 157af75078fSIntel * the maximum number of logical cores - 1. 158af75078fSIntel * The system CPU identifier of all logical cores are setup in a global 159af75078fSIntel * CPU id. configuration table. 160af75078fSIntel */ 161af75078fSIntel struct fwd_lcore { 162af75078fSIntel struct rte_mempool *mbp; /**< The mbuf pool to use by this core */ 163af75078fSIntel streamid_t stream_idx; /**< index of 1st stream in "fwd_streams" */ 164af75078fSIntel streamid_t stream_nb; /**< number of streams in "fwd_streams" */ 165af75078fSIntel lcoreid_t cpuid_idx; /**< index of logical core in CPU id table */ 166af75078fSIntel queueid_t tx_queue; /**< TX queue to send forwarded packets */ 167af75078fSIntel volatile char stopped; /**< stop forwarding when set */ 168af75078fSIntel }; 169af75078fSIntel 170af75078fSIntel /* 171af75078fSIntel * Forwarding mode operations: 172af75078fSIntel * - IO forwarding mode (default mode) 173af75078fSIntel * Forwards packets unchanged. 174af75078fSIntel * 175af75078fSIntel * - MAC forwarding mode 176af75078fSIntel * Set the source and the destination Ethernet addresses of packets 177af75078fSIntel * before forwarding them. 178af75078fSIntel * 179af75078fSIntel * - IEEE1588 forwarding mode 180af75078fSIntel * Check that received IEEE1588 Precise Time Protocol (PTP) packets are 181af75078fSIntel * filtered and timestamped by the hardware. 182af75078fSIntel * Forwards packets unchanged on the same port. 183af75078fSIntel * Check that sent IEEE1588 PTP packets are timestamped by the hardware. 184af75078fSIntel */ 185af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi); 186af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi); 187af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs); 188af75078fSIntel 189af75078fSIntel struct fwd_engine { 190af75078fSIntel const char *fwd_mode_name; /**< Forwarding mode name. */ 191af75078fSIntel port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */ 192af75078fSIntel port_fwd_end_t port_fwd_end; /**< NULL if nothing special to do. */ 193af75078fSIntel packet_fwd_t packet_fwd; /**< Mandatory. */ 194af75078fSIntel }; 195af75078fSIntel 196af75078fSIntel extern struct fwd_engine io_fwd_engine; 197af75078fSIntel extern struct fwd_engine mac_fwd_engine; 198af75078fSIntel extern struct fwd_engine rx_only_engine; 199af75078fSIntel extern struct fwd_engine tx_only_engine; 200af75078fSIntel extern struct fwd_engine csum_fwd_engine; 201af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588 202af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine; 203af75078fSIntel #endif 204af75078fSIntel 205af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */ 206af75078fSIntel 207af75078fSIntel /** 208af75078fSIntel * Forwarding Configuration 209af75078fSIntel * 210af75078fSIntel */ 211af75078fSIntel struct fwd_config { 212af75078fSIntel struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */ 213af75078fSIntel streamid_t nb_fwd_streams; /**< Nb. of forward streams to process. */ 214af75078fSIntel lcoreid_t nb_fwd_lcores; /**< Nb. of logical cores to launch. */ 215af75078fSIntel portid_t nb_fwd_ports; /**< Nb. of ports involved. */ 216af75078fSIntel }; 217af75078fSIntel 218ed30d9b6SIntel #define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */ 219ed30d9b6SIntel #define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */ 220ed30d9b6SIntel 221ed30d9b6SIntel struct queue_stats_mappings { 222ed30d9b6SIntel uint8_t port_id; 223ed30d9b6SIntel uint16_t queue_id; 224ed30d9b6SIntel uint8_t stats_counter_id; 225ed30d9b6SIntel } __rte_cache_aligned; 226ed30d9b6SIntel 227ed30d9b6SIntel extern struct queue_stats_mappings tx_queue_stats_mappings_array[]; 228ed30d9b6SIntel extern struct queue_stats_mappings rx_queue_stats_mappings_array[]; 229ed30d9b6SIntel 230ed30d9b6SIntel /* Assign both tx and rx queue stats mappings to the same default values */ 231ed30d9b6SIntel extern struct queue_stats_mappings *tx_queue_stats_mappings; 232ed30d9b6SIntel extern struct queue_stats_mappings *rx_queue_stats_mappings; 233ed30d9b6SIntel 234ed30d9b6SIntel extern uint16_t nb_tx_queue_stats_mappings; 235ed30d9b6SIntel extern uint16_t nb_rx_queue_stats_mappings; 236ed30d9b6SIntel 237af75078fSIntel /* globals used for configuration */ 238af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */ 239af75078fSIntel extern uint8_t interactive; 240af75078fSIntel extern uint8_t numa_support; /**< set by "--numa" parameter */ 241af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */ 242af75078fSIntel 243af75078fSIntel /* 244af75078fSIntel * Configuration of logical cores: 245af75078fSIntel * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores 246af75078fSIntel */ 247af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */ 248af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */ 249af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */ 250af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE]; 251af75078fSIntel 252af75078fSIntel /* 253af75078fSIntel * Configuration of Ethernet ports: 254af75078fSIntel * nb_fwd_ports <= nb_cfg_ports <= nb_ports 255af75078fSIntel */ 256af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */ 257af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */ 258af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */ 259af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS]; 260af75078fSIntel extern struct rte_port *ports; 261af75078fSIntel 262af75078fSIntel extern struct rte_eth_rxmode rx_mode; 263af75078fSIntel extern uint16_t rss_hf; 264af75078fSIntel 265af75078fSIntel extern queueid_t nb_rxq; 266af75078fSIntel extern queueid_t nb_txq; 267af75078fSIntel 268af75078fSIntel extern uint16_t nb_rxd; 269af75078fSIntel extern uint16_t nb_txd; 270af75078fSIntel 271af75078fSIntel extern uint16_t rx_free_thresh; 272*ce8d5614SIntel extern uint8_t rx_drop_en; 273af75078fSIntel extern uint16_t tx_free_thresh; 274af75078fSIntel extern uint16_t tx_rs_thresh; 275*ce8d5614SIntel extern uint32_t txq_flags; 276af75078fSIntel 277af75078fSIntel extern uint16_t mbuf_data_size; /**< Mbuf data space size. */ 278c8798818SIntel extern uint32_t param_total_num_mbufs; 279af75078fSIntel 280af75078fSIntel extern struct rte_fdir_conf fdir_conf; 281af75078fSIntel 282af75078fSIntel /* 283af75078fSIntel * Configuration of packet segments used by the "txonly" processing engine. 284af75078fSIntel */ 285af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64 286af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */ 287af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */ 288af75078fSIntel extern uint8_t tx_pkt_nb_segs; /**< Number of segments in TX packets */ 289af75078fSIntel 290af75078fSIntel extern uint16_t nb_pkt_per_burst; 291af75078fSIntel extern uint16_t mb_mempool_cache; 292af75078fSIntel extern struct rte_eth_thresh rx_thresh; 293af75078fSIntel extern struct rte_eth_thresh tx_thresh; 294af75078fSIntel 295af75078fSIntel extern struct fwd_config cur_fwd_config; 296af75078fSIntel extern struct fwd_engine *cur_fwd_eng; 297af75078fSIntel extern struct fwd_lcore **fwd_lcores; 298af75078fSIntel extern struct fwd_stream **fwd_streams; 299af75078fSIntel 300af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */ 301af75078fSIntel extern struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS]; 302af75078fSIntel 303af75078fSIntel static inline unsigned int 304af75078fSIntel lcore_num(void) 305af75078fSIntel { 306af75078fSIntel unsigned int i; 307af75078fSIntel 308af75078fSIntel for (i = 0; i < RTE_MAX_LCORE; ++i) 309af75078fSIntel if (fwd_lcores_cpuids[i] == rte_lcore_id()) 310af75078fSIntel return i; 311af75078fSIntel 312af75078fSIntel rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n"); 313af75078fSIntel } 314af75078fSIntel 315af75078fSIntel static inline struct fwd_lcore * 316af75078fSIntel current_fwd_lcore(void) 317af75078fSIntel { 318af75078fSIntel return fwd_lcores[lcore_num()]; 319af75078fSIntel } 320af75078fSIntel 321af75078fSIntel /* Mbuf Pools */ 322af75078fSIntel static inline void 323af75078fSIntel mbuf_poolname_build(unsigned int sock_id, char* mp_name, int name_size) 324af75078fSIntel { 325af75078fSIntel rte_snprintf(mp_name, name_size, "mbuf_pool_socket_%u", sock_id); 326af75078fSIntel } 327af75078fSIntel 328af75078fSIntel static inline struct rte_mempool * 329af75078fSIntel mbuf_pool_find(unsigned int sock_id) 330af75078fSIntel { 331af75078fSIntel char pool_name[RTE_MEMPOOL_NAMESIZE]; 332af75078fSIntel 333af75078fSIntel mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name)); 334af75078fSIntel return (rte_mempool_lookup((const char *)pool_name)); 335af75078fSIntel } 336af75078fSIntel 337af75078fSIntel /** 338af75078fSIntel * Read/Write operations on a PCI register of a port. 339af75078fSIntel */ 340af75078fSIntel static inline uint32_t 341af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off) 342af75078fSIntel { 343af75078fSIntel void *reg_addr; 344af75078fSIntel uint32_t reg_v; 345af75078fSIntel 346af75078fSIntel reg_addr = (void *)((char *)port->dev_info.pci_dev->mem_resource.addr + 347af75078fSIntel reg_off); 348af75078fSIntel reg_v = *((volatile uint32_t *)reg_addr); 349af75078fSIntel return rte_le_to_cpu_32(reg_v); 350af75078fSIntel } 351af75078fSIntel 352af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \ 353af75078fSIntel port_pci_reg_read(&ports[(pt_id)], (reg_off)) 354af75078fSIntel 355af75078fSIntel static inline void 356af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v) 357af75078fSIntel { 358af75078fSIntel void *reg_addr; 359af75078fSIntel 360af75078fSIntel reg_addr = (void *)((char *)port->dev_info.pci_dev->mem_resource.addr + 361af75078fSIntel reg_off); 362af75078fSIntel *((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v); 363af75078fSIntel } 364af75078fSIntel 365af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \ 366af75078fSIntel port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value)) 367af75078fSIntel 368af75078fSIntel /* Prototypes */ 369af75078fSIntel void launch_args_parse(int argc, char** argv); 370af75078fSIntel void prompt(void); 371af75078fSIntel void nic_stats_display(portid_t port_id); 372af75078fSIntel void nic_stats_clear(portid_t port_id); 373ed30d9b6SIntel void nic_stats_mapping_display(portid_t port_id); 374af75078fSIntel void port_infos_display(portid_t port_id); 375af75078fSIntel void fwd_lcores_config_display(void); 376af75078fSIntel void fwd_config_display(void); 377af75078fSIntel void rxtx_config_display(void); 378af75078fSIntel void fwd_config_setup(void); 379af75078fSIntel void set_def_fwd_config(void); 380af75078fSIntel 381af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos); 382af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos, 383af75078fSIntel uint8_t bit_v); 384af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off, 385af75078fSIntel uint8_t bit1_pos, uint8_t bit2_pos); 386af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off, 387af75078fSIntel uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value); 388af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off); 389af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value); 390af75078fSIntel 391af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id); 392af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id); 393af75078fSIntel 394af75078fSIntel void set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc); 395af75078fSIntel void set_fwd_lcores_mask(uint64_t lcoremask); 396af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc); 397af75078fSIntel 398af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt); 399af75078fSIntel void set_fwd_ports_mask(uint64_t portmask); 400af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt); 401af75078fSIntel 402a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on); 403a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on); 404a47aa8b9SIntel 405a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on); 406af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on); 407a47aa8b9SIntel void rx_vft_set(portid_t port_id, uint16_t vlan_id, int on); 408a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on); 409a47aa8b9SIntel void vlan_tpid_set(portid_t port_id, uint16_t tp_id); 410af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id); 411af75078fSIntel void tx_vlan_reset(portid_t port_id); 412af75078fSIntel 413ed30d9b6SIntel 414ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value); 415ed30d9b6SIntel 416af75078fSIntel void tx_cksum_set(portid_t port_id, uint8_t cksum_mask); 417af75078fSIntel 418af75078fSIntel void set_verbose_level(uint16_t vb_level); 419af75078fSIntel void set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs); 420af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst); 421af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode); 422af75078fSIntel void start_packet_forwarding(int with_tx_first); 423af75078fSIntel void stop_packet_forwarding(void); 424*ce8d5614SIntel void init_port_config(void); 425*ce8d5614SIntel void start_port(portid_t pid); 426*ce8d5614SIntel void stop_port(portid_t pid); 427*ce8d5614SIntel void close_port(portid_t pid); 428*ce8d5614SIntel int all_ports_stopped(void); 429af75078fSIntel void pmd_test_exit(void); 430af75078fSIntel 431af75078fSIntel void fdir_add_signature_filter(portid_t port_id, uint8_t queue_id, 432af75078fSIntel struct rte_fdir_filter *fdir_filter); 433af75078fSIntel void fdir_update_signature_filter(portid_t port_id, uint8_t queue_id, 434af75078fSIntel struct rte_fdir_filter *fdir_filter); 435af75078fSIntel void fdir_remove_signature_filter(portid_t port_id, 436af75078fSIntel struct rte_fdir_filter *fdir_filter); 437af75078fSIntel void fdir_get_infos(portid_t port_id); 438af75078fSIntel void fdir_add_perfect_filter(portid_t port_id, uint16_t soft_id, 439af75078fSIntel uint8_t queue_id, uint8_t drop, 440af75078fSIntel struct rte_fdir_filter *fdir_filter); 441af75078fSIntel void fdir_update_perfect_filter(portid_t port_id, uint16_t soft_id, 442af75078fSIntel uint8_t queue_id, uint8_t drop, 443af75078fSIntel struct rte_fdir_filter *fdir_filter); 444af75078fSIntel void fdir_remove_perfect_filter(portid_t port_id, uint16_t soft_id, 445af75078fSIntel struct rte_fdir_filter *fdir_filter); 446af75078fSIntel void fdir_set_masks(portid_t port_id, struct rte_fdir_masks *fdir_masks); 447af75078fSIntel 448af75078fSIntel /* 449af75078fSIntel * Work-around of a compilation error with ICC on invocations of the 450af75078fSIntel * rte_be_to_cpu_16() function. 451af75078fSIntel */ 452af75078fSIntel #ifdef __GCC__ 453af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) rte_be_to_cpu_16((be_16_v)) 454af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v)) 455af75078fSIntel #else 456af75078fSIntel #ifdef __big_endian__ 457af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) (be_16_v) 458af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v) 459af75078fSIntel #else 460af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \ 461af75078fSIntel (uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8)) 462af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \ 463af75078fSIntel (uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8)) 464af75078fSIntel #endif 465af75078fSIntel #endif /* __GCC__ */ 466af75078fSIntel 467af75078fSIntel #endif /* _TESTPMD_H_ */ 468