1174a1631SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 2174a1631SBruce Richardson * Copyright(c) 2010-2017 Intel Corporation 3af75078fSIntel */ 4af75078fSIntel 5af75078fSIntel #ifndef _TESTPMD_H_ 6af75078fSIntel #define _TESTPMD_H_ 7af75078fSIntel 885c18dcbSGaetan Rivet #include <rte_pci.h> 9c752998bSGaetan Rivet #include <rte_bus_pci.h> 10b40f8d78SJiayu Hu #include <rte_gro.h> 1152f38a20SJiayu Hu #include <rte_gso.h> 1285c18dcbSGaetan Rivet 13ce8d5614SIntel #define RTE_PORT_ALL (~(portid_t)0x0) 14ce8d5614SIntel 15ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX 2048 16ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX 2048 17ce8d5614SIntel 18ce8d5614SIntel #define RTE_PORT_STOPPED (uint16_t)0 19ce8d5614SIntel #define RTE_PORT_STARTED (uint16_t)1 20ce8d5614SIntel #define RTE_PORT_CLOSED (uint16_t)2 21ce8d5614SIntel #define RTE_PORT_HANDLING (uint16_t)3 22ce8d5614SIntel 23af75078fSIntel /* 240f6f219eSMohammad Abdul Awal * It is used to allocate the memory for hash key. 250f6f219eSMohammad Abdul Awal * The hash key size is NIC dependent. 260f6f219eSMohammad Abdul Awal */ 270f6f219eSMohammad Abdul Awal #define RSS_HASH_KEY_LENGTH 64 280f6f219eSMohammad Abdul Awal 290f6f219eSMohammad Abdul Awal /* 30af75078fSIntel * Default size of the mbuf data buffer to receive standard 1518-byte 31af75078fSIntel * Ethernet frames in a mono-segment memory buffer. 32af75078fSIntel */ 33824cb29cSKonstantin Ananyev #define DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE 34824cb29cSKonstantin Ananyev /**< Default size of mbuf data buffer. */ 35af75078fSIntel 36af75078fSIntel /* 37af75078fSIntel * The maximum number of segments per packet is used when creating 38af75078fSIntel * scattered transmit packets composed of a list of mbufs. 39af75078fSIntel */ 40ea672a8bSOlivier Matz #define RTE_MAX_SEGS_PER_PKT 255 /**< nb_segs is a 8-bit unsigned char. */ 41af75078fSIntel 42af75078fSIntel #define MAX_PKT_BURST 512 43836853d3SCunming Liang #define DEF_PKT_BURST 32 44af75078fSIntel 45e9378bbcSCunming Liang #define DEF_MBUF_CACHE 250 46e9378bbcSCunming Liang 47fdf20fa7SSergio Gonzalez Monroy #define RTE_CACHE_LINE_SIZE_ROUNDUP(size) \ 48fdf20fa7SSergio Gonzalez Monroy (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) 49af75078fSIntel 50b6ea6408SIntel #define NUMA_NO_CONFIG 0xFF 51b6ea6408SIntel #define UMA_NO_CONFIG 0xFF 52b6ea6408SIntel 53af75078fSIntel typedef uint8_t lcoreid_t; 54f8244c63SZhiyong Yang typedef uint16_t portid_t; 55af75078fSIntel typedef uint16_t queueid_t; 56af75078fSIntel typedef uint16_t streamid_t; 57af75078fSIntel 58af75078fSIntel #define MAX_QUEUE_ID ((1 << (sizeof(queueid_t) * 8)) - 1) 59af75078fSIntel 600ad778b3SJasvinder Singh #if defined RTE_LIBRTE_PMD_SOFTNIC 610ad778b3SJasvinder Singh #define SOFTNIC 1 625b590fbeSJasvinder Singh #else 630ad778b3SJasvinder Singh #define SOFTNIC 0 645b590fbeSJasvinder Singh #endif 655b590fbeSJasvinder Singh 66af75078fSIntel enum { 67af75078fSIntel PORT_TOPOLOGY_PAIRED, 683e2006d6SCyril Chemparathy PORT_TOPOLOGY_CHAINED, 693e2006d6SCyril Chemparathy PORT_TOPOLOGY_LOOP, 70af75078fSIntel }; 71af75078fSIntel 72*c7f5dba7SAnatoly Burakov enum { 73*c7f5dba7SAnatoly Burakov MP_ALLOC_NATIVE, /**< allocate and populate mempool natively */ 74*c7f5dba7SAnatoly Burakov MP_ALLOC_ANON, 75*c7f5dba7SAnatoly Burakov /**< allocate mempool natively, but populate using anonymous memory */ 76*c7f5dba7SAnatoly Burakov MP_ALLOC_XMEM, 77*c7f5dba7SAnatoly Burakov /**< allocate and populate mempool using anonymous memory */ 78*c7f5dba7SAnatoly Burakov MP_ALLOC_XMEM_HUGE 79*c7f5dba7SAnatoly Burakov /**< allocate and populate mempool using anonymous hugepage memory */ 80*c7f5dba7SAnatoly Burakov }; 81*c7f5dba7SAnatoly Burakov 82af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 83af75078fSIntel /** 84af75078fSIntel * The data structure associated with RX and TX packet burst statistics 85af75078fSIntel * that are recorded for each forwarding stream. 86af75078fSIntel */ 87af75078fSIntel struct pkt_burst_stats { 88af75078fSIntel unsigned int pkt_burst_spread[MAX_PKT_BURST]; 89af75078fSIntel }; 90af75078fSIntel #endif 91af75078fSIntel 92f4d623f9SAdrien Mazarguil /** Information for a given RSS type. */ 93f4d623f9SAdrien Mazarguil struct rss_type_info { 94f4d623f9SAdrien Mazarguil const char *str; /**< Type name. */ 95f4d623f9SAdrien Mazarguil uint64_t rss_type; /**< Type value. */ 96f4d623f9SAdrien Mazarguil }; 97f4d623f9SAdrien Mazarguil 98f4d623f9SAdrien Mazarguil /** 99f4d623f9SAdrien Mazarguil * RSS type information table. 100f4d623f9SAdrien Mazarguil * 101f4d623f9SAdrien Mazarguil * An entry with a NULL type name terminates the list. 102f4d623f9SAdrien Mazarguil */ 103f4d623f9SAdrien Mazarguil extern const struct rss_type_info rss_type_table[]; 104f4d623f9SAdrien Mazarguil 105af75078fSIntel /** 106af75078fSIntel * The data structure associated with a forwarding stream between a receive 107af75078fSIntel * port/queue and a transmit port/queue. 108af75078fSIntel */ 109af75078fSIntel struct fwd_stream { 110af75078fSIntel /* "read-only" data */ 111af75078fSIntel portid_t rx_port; /**< port to poll for received packets */ 112af75078fSIntel queueid_t rx_queue; /**< RX queue to poll on "rx_port" */ 113af75078fSIntel portid_t tx_port; /**< forwarding port of received packets */ 114af75078fSIntel queueid_t tx_queue; /**< TX queue to send forwarded packets */ 115af75078fSIntel streamid_t peer_addr; /**< index of peer ethernet address of packets */ 116af75078fSIntel 117bf56fce1SZhihong Wang unsigned int retry_enabled; 118bf56fce1SZhihong Wang 119af75078fSIntel /* "read-write" results */ 120af75078fSIntel unsigned int rx_packets; /**< received packets */ 121af75078fSIntel unsigned int tx_packets; /**< received packets transmitted */ 122af75078fSIntel unsigned int fwd_dropped; /**< received packets not forwarded */ 123af75078fSIntel unsigned int rx_bad_ip_csum ; /**< received packets has bad ip checksum */ 124af75078fSIntel unsigned int rx_bad_l4_csum ; /**< received packets has bad l4 checksum */ 125b7091f1dSJiayu Hu unsigned int gro_times; /**< GRO operation times */ 126af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES 127af75078fSIntel uint64_t core_cycles; /**< used for RX and TX processing */ 128af75078fSIntel #endif 129af75078fSIntel #ifdef RTE_TEST_PMD_RECORD_BURST_STATS 130af75078fSIntel struct pkt_burst_stats rx_burst_stats; 131af75078fSIntel struct pkt_burst_stats tx_burst_stats; 132af75078fSIntel #endif 133af75078fSIntel }; 134af75078fSIntel 135938a184aSAdrien Mazarguil /** Descriptor for a single flow. */ 136938a184aSAdrien Mazarguil struct port_flow { 137938a184aSAdrien Mazarguil size_t size; /**< Allocated space including data[]. */ 138938a184aSAdrien Mazarguil struct port_flow *next; /**< Next flow in list. */ 139938a184aSAdrien Mazarguil struct port_flow *tmp; /**< Temporary linking. */ 140938a184aSAdrien Mazarguil uint32_t id; /**< Flow rule ID. */ 141938a184aSAdrien Mazarguil struct rte_flow *flow; /**< Opaque flow object returned by PMD. */ 142938a184aSAdrien Mazarguil struct rte_flow_attr attr; /**< Attributes. */ 143938a184aSAdrien Mazarguil struct rte_flow_item *pattern; /**< Pattern. */ 144938a184aSAdrien Mazarguil struct rte_flow_action *actions; /**< Actions. */ 145938a184aSAdrien Mazarguil uint8_t data[]; /**< Storage for pattern/actions. */ 146938a184aSAdrien Mazarguil }; 147938a184aSAdrien Mazarguil 1480ad778b3SJasvinder Singh #ifdef SOFTNIC 1495b590fbeSJasvinder Singh /** 1505b590fbeSJasvinder Singh * The data structure associate with softnic port 1515b590fbeSJasvinder Singh */ 1525b590fbeSJasvinder Singh struct softnic_port { 1530ad778b3SJasvinder Singh uint32_t default_tm_hierarchy_enable; /**< default tm hierarchy */ 1540ad778b3SJasvinder Singh struct fwd_lcore **fwd_lcore_arg; /**< softnic fwd core parameters */ 1555b590fbeSJasvinder Singh }; 1565b590fbeSJasvinder Singh #endif 1575b590fbeSJasvinder Singh 158af75078fSIntel /** 159af75078fSIntel * The data structure associated with each port. 160af75078fSIntel */ 161af75078fSIntel struct rte_port { 162af75078fSIntel struct rte_eth_dev_info dev_info; /**< PCI info + driver name */ 163af75078fSIntel struct rte_eth_conf dev_conf; /**< Port configuration. */ 164af75078fSIntel struct ether_addr eth_addr; /**< Port ethernet address */ 165af75078fSIntel struct rte_eth_stats stats; /**< Last port statistics */ 166af75078fSIntel uint64_t tx_dropped; /**< If no descriptor in TX ring */ 167af75078fSIntel struct fwd_stream *rx_stream; /**< Port RX stream, if unique */ 168af75078fSIntel struct fwd_stream *tx_stream; /**< Port TX stream, if unique */ 169af75078fSIntel unsigned int socket_id; /**< For NUMA support */ 1703eecba26SShahaf Shuler uint16_t parse_tunnel:1; /**< Parse internal headers */ 1710f62d635SJianfeng Tan uint16_t tso_segsz; /**< Segmentation offload MSS for non-tunneled packets. */ 1720f62d635SJianfeng Tan uint16_t tunnel_tso_segsz; /**< Segmentation offload MSS for tunneled pkts. */ 17392ebda07SHelin Zhang uint16_t tx_vlan_id;/**< The tag ID */ 17492ebda07SHelin Zhang uint16_t tx_vlan_id_outer;/**< The outer tag ID */ 175af75078fSIntel void *fwd_ctx; /**< Forwarding mode context */ 176af75078fSIntel uint64_t rx_bad_ip_csum; /**< rx pkts with bad ip checksum */ 177af75078fSIntel uint64_t rx_bad_l4_csum; /**< rx pkts with bad l4 checksum */ 178ed30d9b6SIntel uint8_t tx_queue_stats_mapping_enabled; 179ed30d9b6SIntel uint8_t rx_queue_stats_mapping_enabled; 180ce8d5614SIntel volatile uint16_t port_status; /**< port started or not */ 181ce8d5614SIntel uint8_t need_reconfig; /**< need reconfiguring port or not */ 182ce8d5614SIntel uint8_t need_reconfig_queues; /**< need reconfiguring queues or not */ 183ce8d5614SIntel uint8_t rss_flag; /**< enable rss or not */ 1847741e4cfSIntel uint8_t dcb_flag; /**< enable dcb */ 185d44f8a48SQi Zhang uint16_t nb_rx_desc[MAX_QUEUE_ID+1]; /**< per queue rx desc number */ 186d44f8a48SQi Zhang uint16_t nb_tx_desc[MAX_QUEUE_ID+1]; /**< per queue tx desc number */ 187d44f8a48SQi Zhang struct rte_eth_rxconf rx_conf[MAX_QUEUE_ID+1]; /**< per queue rx configuration */ 188d44f8a48SQi Zhang struct rte_eth_txconf tx_conf[MAX_QUEUE_ID+1]; /**< per queue tx configuration */ 1898fff6675SIvan Boule struct ether_addr *mc_addr_pool; /**< pool of multicast addrs */ 1908fff6675SIvan Boule uint32_t mc_addr_nb; /**< nb. of addr. in mc_addr_pool */ 19141b05095SBernard Iremonger uint8_t slave_flag; /**< bonding slave port */ 192938a184aSAdrien Mazarguil struct port_flow *flow_list; /**< Associated flows. */ 1930ad778b3SJasvinder Singh #ifdef SOFTNIC 1940ad778b3SJasvinder Singh struct softnic_port softport; /**< softnic params */ 1955b590fbeSJasvinder Singh #endif 196af75078fSIntel }; 197af75078fSIntel 198af75078fSIntel /** 199af75078fSIntel * The data structure associated with each forwarding logical core. 200af75078fSIntel * The logical cores are internally numbered by a core index from 0 to 201af75078fSIntel * the maximum number of logical cores - 1. 202af75078fSIntel * The system CPU identifier of all logical cores are setup in a global 203af75078fSIntel * CPU id. configuration table. 204af75078fSIntel */ 205af75078fSIntel struct fwd_lcore { 20652f38a20SJiayu Hu struct rte_gso_ctx gso_ctx; /**< GSO context */ 207af75078fSIntel struct rte_mempool *mbp; /**< The mbuf pool to use by this core */ 208b7091f1dSJiayu Hu void *gro_ctx; /**< GRO context */ 209af75078fSIntel streamid_t stream_idx; /**< index of 1st stream in "fwd_streams" */ 210af75078fSIntel streamid_t stream_nb; /**< number of streams in "fwd_streams" */ 211af75078fSIntel lcoreid_t cpuid_idx; /**< index of logical core in CPU id table */ 212af75078fSIntel queueid_t tx_queue; /**< TX queue to send forwarded packets */ 213af75078fSIntel volatile char stopped; /**< stop forwarding when set */ 214af75078fSIntel }; 215af75078fSIntel 216af75078fSIntel /* 217af75078fSIntel * Forwarding mode operations: 218af75078fSIntel * - IO forwarding mode (default mode) 219af75078fSIntel * Forwards packets unchanged. 220af75078fSIntel * 221af75078fSIntel * - MAC forwarding mode 222af75078fSIntel * Set the source and the destination Ethernet addresses of packets 223af75078fSIntel * before forwarding them. 224af75078fSIntel * 225af75078fSIntel * - IEEE1588 forwarding mode 226af75078fSIntel * Check that received IEEE1588 Precise Time Protocol (PTP) packets are 227af75078fSIntel * filtered and timestamped by the hardware. 228af75078fSIntel * Forwards packets unchanged on the same port. 229af75078fSIntel * Check that sent IEEE1588 PTP packets are timestamped by the hardware. 230af75078fSIntel */ 231af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi); 232af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi); 233af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs); 234af75078fSIntel 235af75078fSIntel struct fwd_engine { 236af75078fSIntel const char *fwd_mode_name; /**< Forwarding mode name. */ 237af75078fSIntel port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */ 238af75078fSIntel port_fwd_end_t port_fwd_end; /**< NULL if nothing special to do. */ 239af75078fSIntel packet_fwd_t packet_fwd; /**< Mandatory. */ 240af75078fSIntel }; 241af75078fSIntel 242bf56fce1SZhihong Wang #define BURST_TX_WAIT_US 1 243bf56fce1SZhihong Wang #define BURST_TX_RETRIES 64 244bf56fce1SZhihong Wang 245bf56fce1SZhihong Wang extern uint32_t burst_tx_delay_time; 246bf56fce1SZhihong Wang extern uint32_t burst_tx_retry_num; 247bf56fce1SZhihong Wang 248af75078fSIntel extern struct fwd_engine io_fwd_engine; 249af75078fSIntel extern struct fwd_engine mac_fwd_engine; 250d47388f1SCyril Chemparathy extern struct fwd_engine mac_swap_engine; 251e9e23a61SCyril Chemparathy extern struct fwd_engine flow_gen_engine; 252af75078fSIntel extern struct fwd_engine rx_only_engine; 253af75078fSIntel extern struct fwd_engine tx_only_engine; 254af75078fSIntel extern struct fwd_engine csum_fwd_engine; 255168dfa61SIvan Boule extern struct fwd_engine icmp_echo_engine; 2560ad778b3SJasvinder Singh #ifdef SOFTNIC 2570ad778b3SJasvinder Singh extern struct fwd_engine softnic_fwd_engine; 2585b590fbeSJasvinder Singh #endif 259af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588 260af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine; 261af75078fSIntel #endif 262af75078fSIntel 263af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */ 264af75078fSIntel 265af75078fSIntel /** 266af75078fSIntel * Forwarding Configuration 267af75078fSIntel * 268af75078fSIntel */ 269af75078fSIntel struct fwd_config { 270af75078fSIntel struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */ 271af75078fSIntel streamid_t nb_fwd_streams; /**< Nb. of forward streams to process. */ 272af75078fSIntel lcoreid_t nb_fwd_lcores; /**< Nb. of logical cores to launch. */ 273af75078fSIntel portid_t nb_fwd_ports; /**< Nb. of ports involved. */ 274af75078fSIntel }; 275af75078fSIntel 276900550deSIntel /** 277900550deSIntel * DCB mode enable 278900550deSIntel */ 279900550deSIntel enum dcb_mode_enable 280900550deSIntel { 281900550deSIntel DCB_VT_ENABLED, 282900550deSIntel DCB_ENABLED 283900550deSIntel }; 284900550deSIntel 285ed30d9b6SIntel #define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */ 286ed30d9b6SIntel #define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */ 287ed30d9b6SIntel 288ed30d9b6SIntel struct queue_stats_mappings { 289f8244c63SZhiyong Yang portid_t port_id; 290ed30d9b6SIntel uint16_t queue_id; 291ed30d9b6SIntel uint8_t stats_counter_id; 292ed30d9b6SIntel } __rte_cache_aligned; 293ed30d9b6SIntel 294ed30d9b6SIntel extern struct queue_stats_mappings tx_queue_stats_mappings_array[]; 295ed30d9b6SIntel extern struct queue_stats_mappings rx_queue_stats_mappings_array[]; 296ed30d9b6SIntel 297ed30d9b6SIntel /* Assign both tx and rx queue stats mappings to the same default values */ 298ed30d9b6SIntel extern struct queue_stats_mappings *tx_queue_stats_mappings; 299ed30d9b6SIntel extern struct queue_stats_mappings *rx_queue_stats_mappings; 300ed30d9b6SIntel 301ed30d9b6SIntel extern uint16_t nb_tx_queue_stats_mappings; 302ed30d9b6SIntel extern uint16_t nb_rx_queue_stats_mappings; 303ed30d9b6SIntel 304a4fd5eeeSElza Mathew extern uint8_t xstats_hide_zero; /**< Hide zero values for xstats display */ 305a4fd5eeeSElza Mathew 306af75078fSIntel /* globals used for configuration */ 307af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */ 308285fd101SOlivier Matz extern int testpmd_logtype; /**< Log type for testpmd logs */ 309af75078fSIntel extern uint8_t interactive; 310ca7feb22SCyril Chemparathy extern uint8_t auto_start; 31199cabef0SPablo de Lara extern uint8_t tx_first; 31281ef862bSAllain Legacy extern char cmdline_filename[PATH_MAX]; /**< offline commands file */ 313af75078fSIntel extern uint8_t numa_support; /**< set by "--numa" parameter */ 314af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */ 3157741e4cfSIntel extern uint8_t no_flush_rx; /**<set by "--no-flush-rx" parameter */ 3167ee3e944SVasily Philipov extern uint8_t flow_isolate_all; /**< set by "--flow-isolate-all */ 317*c7f5dba7SAnatoly Burakov extern uint8_t mp_alloc_type; 318*c7f5dba7SAnatoly Burakov /**< set by "--mp-anon" or "--mp-alloc" parameter */ 319bc202406SDavid Marchand extern uint8_t no_link_check; /**<set by "--disable-link-check" parameter */ 3202950a769SDeclan Doherty extern volatile int test_done; /* stop packet forwarding when set to 1. */ 3218ea656f8SGaetan Rivet extern uint8_t lsc_interrupt; /**< disabled by "--no-lsc-interrupt" parameter */ 322284c908cSGaetan Rivet extern uint8_t rmv_interrupt; /**< disabled by "--no-rmv-interrupt" parameter */ 3233af72783SGaetan Rivet extern uint32_t event_print_mask; 3243af72783SGaetan Rivet /**< set by "--print-event xxxx" and "--mask-event xxxx parameters */ 325e505d84cSAnatoly Burakov extern uint8_t hot_plug; /**< enable by "--hot-plug" parameter */ 326e505d84cSAnatoly Burakov extern int do_mlockall; /**< set by "--mlockall" or "--no-mlockall" parameter */ 327af75078fSIntel 328e261265eSRadu Nicolau #ifdef RTE_LIBRTE_IXGBE_BYPASS 3297b7e5ba7SIntel extern uint32_t bypass_timeout; /**< Store the NIC bypass watchdog timeout */ 3307b7e5ba7SIntel #endif 3317b7e5ba7SIntel 332b6ea6408SIntel /* 333b6ea6408SIntel * Store specified sockets on which memory pool to be used by ports 334b6ea6408SIntel * is allocated. 335b6ea6408SIntel */ 33663531389SGeorgios Katsikas extern uint8_t port_numa[RTE_MAX_ETHPORTS]; 337b6ea6408SIntel 338b6ea6408SIntel /* 339b6ea6408SIntel * Store specified sockets on which RX ring to be used by ports 340b6ea6408SIntel * is allocated. 341b6ea6408SIntel */ 34263531389SGeorgios Katsikas extern uint8_t rxring_numa[RTE_MAX_ETHPORTS]; 343b6ea6408SIntel 344b6ea6408SIntel /* 345b6ea6408SIntel * Store specified sockets on which TX ring to be used by ports 346b6ea6408SIntel * is allocated. 347b6ea6408SIntel */ 34863531389SGeorgios Katsikas extern uint8_t txring_numa[RTE_MAX_ETHPORTS]; 349b6ea6408SIntel 350b6ea6408SIntel extern uint8_t socket_num; 351b6ea6408SIntel 352af75078fSIntel /* 353af75078fSIntel * Configuration of logical cores: 354af75078fSIntel * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores 355af75078fSIntel */ 356af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */ 357af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */ 358af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */ 359af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE]; 360c9cafcc8SShahaf Shuler extern unsigned int num_sockets; 361c9cafcc8SShahaf Shuler extern unsigned int socket_ids[RTE_MAX_NUMA_NODES]; 362af75078fSIntel 363af75078fSIntel /* 364af75078fSIntel * Configuration of Ethernet ports: 365af75078fSIntel * nb_fwd_ports <= nb_cfg_ports <= nb_ports 366af75078fSIntel */ 367af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */ 368af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */ 369af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */ 370af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS]; 371af75078fSIntel extern struct rte_port *ports; 372af75078fSIntel 373af75078fSIntel extern struct rte_eth_rxmode rx_mode; 374fd8c20aaSShahaf Shuler extern struct rte_eth_txmode tx_mode; 375fd8c20aaSShahaf Shuler 3768a387fa8SHelin Zhang extern uint64_t rss_hf; 377af75078fSIntel 378af75078fSIntel extern queueid_t nb_rxq; 379af75078fSIntel extern queueid_t nb_txq; 380af75078fSIntel 381af75078fSIntel extern uint16_t nb_rxd; 382af75078fSIntel extern uint16_t nb_txd; 383af75078fSIntel 384f2c5125aSPablo de Lara extern int16_t rx_free_thresh; 385f2c5125aSPablo de Lara extern int8_t rx_drop_en; 386f2c5125aSPablo de Lara extern int16_t tx_free_thresh; 387f2c5125aSPablo de Lara extern int16_t tx_rs_thresh; 388af75078fSIntel 389900550deSIntel extern uint8_t dcb_config; 390900550deSIntel extern uint8_t dcb_test; 391900550deSIntel 392af75078fSIntel extern uint16_t mbuf_data_size; /**< Mbuf data space size. */ 393c8798818SIntel extern uint32_t param_total_num_mbufs; 394af75078fSIntel 395cfea1f30SPablo de Lara extern uint16_t stats_period; 39662d3216dSReshma Pattan 39762d3216dSReshma Pattan #ifdef RTE_LIBRTE_LATENCY_STATS 39862d3216dSReshma Pattan extern uint8_t latencystats_enabled; 39962d3216dSReshma Pattan extern lcoreid_t latencystats_lcore_id; 40062d3216dSReshma Pattan #endif 40162d3216dSReshma Pattan 402e25e6c70SRemy Horton #ifdef RTE_LIBRTE_BITRATE 403e25e6c70SRemy Horton extern lcoreid_t bitrate_lcore_id; 404e25e6c70SRemy Horton extern uint8_t bitrate_enabled; 405e25e6c70SRemy Horton #endif 406e25e6c70SRemy Horton 407af75078fSIntel extern struct rte_fdir_conf fdir_conf; 408af75078fSIntel 409af75078fSIntel /* 410af75078fSIntel * Configuration of packet segments used by the "txonly" processing engine. 411af75078fSIntel */ 412af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64 413af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */ 414af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */ 415af75078fSIntel extern uint8_t tx_pkt_nb_segs; /**< Number of segments in TX packets */ 416af75078fSIntel 41779bec05bSKonstantin Ananyev enum tx_pkt_split { 41879bec05bSKonstantin Ananyev TX_PKT_SPLIT_OFF, 41979bec05bSKonstantin Ananyev TX_PKT_SPLIT_ON, 42079bec05bSKonstantin Ananyev TX_PKT_SPLIT_RND, 42179bec05bSKonstantin Ananyev }; 42279bec05bSKonstantin Ananyev 42379bec05bSKonstantin Ananyev extern enum tx_pkt_split tx_pkt_split; 42479bec05bSKonstantin Ananyev 425af75078fSIntel extern uint16_t nb_pkt_per_burst; 426af75078fSIntel extern uint16_t mb_mempool_cache; 427f2c5125aSPablo de Lara extern int8_t rx_pthresh; 428f2c5125aSPablo de Lara extern int8_t rx_hthresh; 429f2c5125aSPablo de Lara extern int8_t rx_wthresh; 430f2c5125aSPablo de Lara extern int8_t tx_pthresh; 431f2c5125aSPablo de Lara extern int8_t tx_hthresh; 432f2c5125aSPablo de Lara extern int8_t tx_wthresh; 433af75078fSIntel 434af75078fSIntel extern struct fwd_config cur_fwd_config; 435af75078fSIntel extern struct fwd_engine *cur_fwd_eng; 436bf56fce1SZhihong Wang extern uint32_t retry_enabled; 437af75078fSIntel extern struct fwd_lcore **fwd_lcores; 438af75078fSIntel extern struct fwd_stream **fwd_streams; 439af75078fSIntel 44039e5e20fSXueming Li extern uint16_t vxlan_gpe_udp_port; /**< UDP port of tunnel VXLAN-GPE. */ 44139e5e20fSXueming Li 442af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */ 443af75078fSIntel extern struct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS]; 444af75078fSIntel 44557e85242SBruce Richardson extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */ 44657e85242SBruce Richardson extern uint32_t burst_tx_retry_num; /**< Burst tx retry number for mac-retry. */ 44757e85242SBruce Richardson 448b7091f1dSJiayu Hu #define GRO_DEFAULT_ITEM_NUM_PER_FLOW 32 449b7091f1dSJiayu Hu #define GRO_DEFAULT_FLOW_NUM (RTE_GRO_MAX_BURST_ITEM_NUM / \ 450b7091f1dSJiayu Hu GRO_DEFAULT_ITEM_NUM_PER_FLOW) 451b7091f1dSJiayu Hu 452b7091f1dSJiayu Hu #define GRO_DEFAULT_FLUSH_CYCLES 1 453b7091f1dSJiayu Hu #define GRO_MAX_FLUSH_CYCLES 4 454b7091f1dSJiayu Hu 455b40f8d78SJiayu Hu struct gro_status { 456b40f8d78SJiayu Hu struct rte_gro_param param; 457b40f8d78SJiayu Hu uint8_t enable; 458b40f8d78SJiayu Hu }; 459b40f8d78SJiayu Hu extern struct gro_status gro_ports[RTE_MAX_ETHPORTS]; 460b7091f1dSJiayu Hu extern uint8_t gro_flush_cycles; 461b40f8d78SJiayu Hu 46252f38a20SJiayu Hu #define GSO_MAX_PKT_BURST 2048 46352f38a20SJiayu Hu struct gso_status { 46452f38a20SJiayu Hu uint8_t enable; 46552f38a20SJiayu Hu }; 46652f38a20SJiayu Hu extern struct gso_status gso_ports[RTE_MAX_ETHPORTS]; 46752f38a20SJiayu Hu extern uint16_t gso_max_segment_size; 46852f38a20SJiayu Hu 4691960be7dSNelio Laranjeiro /* VXLAN encap/decap parameters. */ 4701960be7dSNelio Laranjeiro struct vxlan_encap_conf { 4711960be7dSNelio Laranjeiro uint32_t select_ipv4:1; 4721960be7dSNelio Laranjeiro uint32_t select_vlan:1; 4731960be7dSNelio Laranjeiro uint8_t vni[3]; 4741960be7dSNelio Laranjeiro rte_be16_t udp_src; 4751960be7dSNelio Laranjeiro rte_be16_t udp_dst; 4761960be7dSNelio Laranjeiro rte_be32_t ipv4_src; 4771960be7dSNelio Laranjeiro rte_be32_t ipv4_dst; 4781960be7dSNelio Laranjeiro uint8_t ipv6_src[16]; 4791960be7dSNelio Laranjeiro uint8_t ipv6_dst[16]; 4801960be7dSNelio Laranjeiro rte_be16_t vlan_tci; 4811960be7dSNelio Laranjeiro uint8_t eth_src[ETHER_ADDR_LEN]; 4821960be7dSNelio Laranjeiro uint8_t eth_dst[ETHER_ADDR_LEN]; 4831960be7dSNelio Laranjeiro }; 4841960be7dSNelio Laranjeiro struct vxlan_encap_conf vxlan_encap_conf; 4851960be7dSNelio Laranjeiro 486dcd962fcSNelio Laranjeiro /* NVGRE encap/decap parameters. */ 487dcd962fcSNelio Laranjeiro struct nvgre_encap_conf { 488dcd962fcSNelio Laranjeiro uint32_t select_ipv4:1; 489dcd962fcSNelio Laranjeiro uint32_t select_vlan:1; 490dcd962fcSNelio Laranjeiro uint8_t tni[3]; 491dcd962fcSNelio Laranjeiro rte_be32_t ipv4_src; 492dcd962fcSNelio Laranjeiro rte_be32_t ipv4_dst; 493dcd962fcSNelio Laranjeiro uint8_t ipv6_src[16]; 494dcd962fcSNelio Laranjeiro uint8_t ipv6_dst[16]; 495dcd962fcSNelio Laranjeiro rte_be16_t vlan_tci; 496dcd962fcSNelio Laranjeiro uint8_t eth_src[ETHER_ADDR_LEN]; 497dcd962fcSNelio Laranjeiro uint8_t eth_dst[ETHER_ADDR_LEN]; 498dcd962fcSNelio Laranjeiro }; 499dcd962fcSNelio Laranjeiro struct nvgre_encap_conf nvgre_encap_conf; 500dcd962fcSNelio Laranjeiro 501af75078fSIntel static inline unsigned int 502af75078fSIntel lcore_num(void) 503af75078fSIntel { 504af75078fSIntel unsigned int i; 505af75078fSIntel 506af75078fSIntel for (i = 0; i < RTE_MAX_LCORE; ++i) 507af75078fSIntel if (fwd_lcores_cpuids[i] == rte_lcore_id()) 508af75078fSIntel return i; 509af75078fSIntel 510af75078fSIntel rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n"); 511af75078fSIntel } 512af75078fSIntel 513af75078fSIntel static inline struct fwd_lcore * 514af75078fSIntel current_fwd_lcore(void) 515af75078fSIntel { 516af75078fSIntel return fwd_lcores[lcore_num()]; 517af75078fSIntel } 518af75078fSIntel 519af75078fSIntel /* Mbuf Pools */ 520af75078fSIntel static inline void 521af75078fSIntel mbuf_poolname_build(unsigned int sock_id, char* mp_name, int name_size) 522af75078fSIntel { 5236f41fe75SStephen Hemminger snprintf(mp_name, name_size, "mbuf_pool_socket_%u", sock_id); 524af75078fSIntel } 525af75078fSIntel 526af75078fSIntel static inline struct rte_mempool * 527af75078fSIntel mbuf_pool_find(unsigned int sock_id) 528af75078fSIntel { 529af75078fSIntel char pool_name[RTE_MEMPOOL_NAMESIZE]; 530af75078fSIntel 531af75078fSIntel mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name)); 532693f715dSHuawei Xie return rte_mempool_lookup((const char *)pool_name); 533af75078fSIntel } 534af75078fSIntel 535af75078fSIntel /** 536af75078fSIntel * Read/Write operations on a PCI register of a port. 537af75078fSIntel */ 538af75078fSIntel static inline uint32_t 539af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off) 540af75078fSIntel { 541cd8c7c7cSFerruh Yigit const struct rte_pci_device *pci_dev; 542cd8c7c7cSFerruh Yigit const struct rte_bus *bus; 543af75078fSIntel void *reg_addr; 544af75078fSIntel uint32_t reg_v; 545af75078fSIntel 546cd8c7c7cSFerruh Yigit if (!port->dev_info.device) { 547cd8c7c7cSFerruh Yigit printf("Invalid device\n"); 548cd8c7c7cSFerruh Yigit return 0; 549cd8c7c7cSFerruh Yigit } 550cd8c7c7cSFerruh Yigit 551cd8c7c7cSFerruh Yigit bus = rte_bus_find_by_device(port->dev_info.device); 552cd8c7c7cSFerruh Yigit if (bus && !strcmp(bus->name, "pci")) { 553cd8c7c7cSFerruh Yigit pci_dev = RTE_DEV_TO_PCI(port->dev_info.device); 554cd8c7c7cSFerruh Yigit } else { 555cd8c7c7cSFerruh Yigit printf("Not a PCI device\n"); 556cd8c7c7cSFerruh Yigit return 0; 557cd8c7c7cSFerruh Yigit } 558cd8c7c7cSFerruh Yigit 559cd8c7c7cSFerruh Yigit reg_addr = ((char *)pci_dev->mem_resource[0].addr + reg_off); 560af75078fSIntel reg_v = *((volatile uint32_t *)reg_addr); 561af75078fSIntel return rte_le_to_cpu_32(reg_v); 562af75078fSIntel } 563af75078fSIntel 564af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \ 565af75078fSIntel port_pci_reg_read(&ports[(pt_id)], (reg_off)) 566af75078fSIntel 567af75078fSIntel static inline void 568af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v) 569af75078fSIntel { 570cd8c7c7cSFerruh Yigit const struct rte_pci_device *pci_dev; 571cd8c7c7cSFerruh Yigit const struct rte_bus *bus; 572af75078fSIntel void *reg_addr; 573af75078fSIntel 574cd8c7c7cSFerruh Yigit if (!port->dev_info.device) { 575cd8c7c7cSFerruh Yigit printf("Invalid device\n"); 576cd8c7c7cSFerruh Yigit return; 577cd8c7c7cSFerruh Yigit } 578cd8c7c7cSFerruh Yigit 579cd8c7c7cSFerruh Yigit bus = rte_bus_find_by_device(port->dev_info.device); 580cd8c7c7cSFerruh Yigit if (bus && !strcmp(bus->name, "pci")) { 581cd8c7c7cSFerruh Yigit pci_dev = RTE_DEV_TO_PCI(port->dev_info.device); 582cd8c7c7cSFerruh Yigit } else { 583cd8c7c7cSFerruh Yigit printf("Not a PCI device\n"); 584cd8c7c7cSFerruh Yigit return; 585cd8c7c7cSFerruh Yigit } 586cd8c7c7cSFerruh Yigit 587cd8c7c7cSFerruh Yigit reg_addr = ((char *)pci_dev->mem_resource[0].addr + reg_off); 588af75078fSIntel *((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v); 589af75078fSIntel } 590af75078fSIntel 591af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \ 592af75078fSIntel port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value)) 593af75078fSIntel 594af75078fSIntel /* Prototypes */ 595950d1516SBruce Richardson unsigned int parse_item_list(char* str, const char* item_name, 596950d1516SBruce Richardson unsigned int max_items, 597950d1516SBruce Richardson unsigned int *parsed_items, int check_unique_values); 598af75078fSIntel void launch_args_parse(int argc, char** argv); 59981ef862bSAllain Legacy void cmdline_read_from_file(const char *filename); 600af75078fSIntel void prompt(void); 601d3a274ceSZhihong Wang void prompt_exit(void); 602af75078fSIntel void nic_stats_display(portid_t port_id); 603af75078fSIntel void nic_stats_clear(portid_t port_id); 604bfd5051bSOlivier Matz void nic_xstats_display(portid_t port_id); 605bfd5051bSOlivier Matz void nic_xstats_clear(portid_t port_id); 606ed30d9b6SIntel void nic_stats_mapping_display(portid_t port_id); 607af75078fSIntel void port_infos_display(portid_t port_id); 608d28645c7SQiming Yang void port_offload_cap_display(portid_t port_id); 609ab3257e1SKonstantin Ananyev void rx_queue_infos_display(portid_t port_idi, uint16_t queue_id); 610ab3257e1SKonstantin Ananyev void tx_queue_infos_display(portid_t port_idi, uint16_t queue_id); 611af75078fSIntel void fwd_lcores_config_display(void); 6120c0db76fSBernard Iremonger void pkt_fwd_config_display(struct fwd_config *cfg); 613af75078fSIntel void rxtx_config_display(void); 614af75078fSIntel void fwd_config_setup(void); 615af75078fSIntel void set_def_fwd_config(void); 616a21d5a4bSDeclan Doherty void reconfig(portid_t new_port_id, unsigned socket_id); 617013af9b6SIntel int init_fwd_streams(void); 61803ce2c53SMatan Azrad void update_fwd_ports(portid_t new_pid); 619013af9b6SIntel 620aac6f11fSWisam Jaddo void set_fwd_eth_peer(portid_t port_id, char *peer_addr); 621aac6f11fSWisam Jaddo 622ae03d0d1SIvan Boule void port_mtu_set(portid_t port_id, uint16_t mtu); 623af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos); 624af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos, 625af75078fSIntel uint8_t bit_v); 626af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off, 627af75078fSIntel uint8_t bit1_pos, uint8_t bit2_pos); 628af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off, 629af75078fSIntel uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value); 630af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off); 631af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value); 632938a184aSAdrien Mazarguil int port_flow_validate(portid_t port_id, 633938a184aSAdrien Mazarguil const struct rte_flow_attr *attr, 634938a184aSAdrien Mazarguil const struct rte_flow_item *pattern, 635938a184aSAdrien Mazarguil const struct rte_flow_action *actions); 636938a184aSAdrien Mazarguil int port_flow_create(portid_t port_id, 637938a184aSAdrien Mazarguil const struct rte_flow_attr *attr, 638938a184aSAdrien Mazarguil const struct rte_flow_item *pattern, 639938a184aSAdrien Mazarguil const struct rte_flow_action *actions); 640938a184aSAdrien Mazarguil int port_flow_destroy(portid_t port_id, uint32_t n, const uint32_t *rule); 641938a184aSAdrien Mazarguil int port_flow_flush(portid_t port_id); 642938a184aSAdrien Mazarguil int port_flow_query(portid_t port_id, uint32_t rule, 643fb8fd96dSDeclan Doherty const struct rte_flow_action *action); 644938a184aSAdrien Mazarguil void port_flow_list(portid_t port_id, uint32_t n, const uint32_t *group); 645323f811aSAdrien Mazarguil int port_flow_isolate(portid_t port_id, int set); 646af75078fSIntel 647af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id); 648af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id); 649af75078fSIntel 650013af9b6SIntel int set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc); 651013af9b6SIntel int set_fwd_lcores_mask(uint64_t lcoremask); 652af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc); 653af75078fSIntel 654af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt); 655af75078fSIntel void set_fwd_ports_mask(uint64_t portmask); 656af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt); 657a8ef3e3aSBernard Iremonger int port_is_forwarding(portid_t port_id); 658af75078fSIntel 659a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on); 660a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on); 661a47aa8b9SIntel 662a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on); 663af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on); 66464b01ee0SMichal Jastrzebski int rx_vft_set(portid_t port_id, uint16_t vlan_id, int on); 665a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on); 66619b16e2fSHelin Zhang void vlan_tpid_set(portid_t port_id, enum rte_vlan_type vlan_type, 66719b16e2fSHelin Zhang uint16_t tp_id); 668af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id); 66992ebda07SHelin Zhang void tx_qinq_set(portid_t port_id, uint16_t vlan_id, uint16_t vlan_id_outer); 670af75078fSIntel void tx_vlan_reset(portid_t port_id); 671529ba951SHelin Zhang void tx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on); 672ed30d9b6SIntel 673ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value); 674ed30d9b6SIntel 675a4fd5eeeSElza Mathew void set_xstats_hide_zero(uint8_t on_off); 676a4fd5eeeSElza Mathew 677af75078fSIntel void set_verbose_level(uint16_t vb_level); 678af75078fSIntel void set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs); 67979bec05bSKonstantin Ananyev void show_tx_pkt_segments(void); 68079bec05bSKonstantin Ananyev void set_tx_pkt_split(const char *name); 681af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst); 682769ce6b1SThomas Monjalon char *list_pkt_forwarding_modes(void); 683bf56fce1SZhihong Wang char *list_pkt_forwarding_retry_modes(void); 684af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode); 685af75078fSIntel void start_packet_forwarding(int with_tx_first); 686af75078fSIntel void stop_packet_forwarding(void); 687cfae07fdSOuyang Changchun void dev_set_link_up(portid_t pid); 688cfae07fdSOuyang Changchun void dev_set_link_down(portid_t pid); 689ce8d5614SIntel void init_port_config(void); 69041b05095SBernard Iremonger void set_port_slave_flag(portid_t slave_pid); 69141b05095SBernard Iremonger void clear_port_slave_flag(portid_t slave_pid); 6920e545d30SBernard Iremonger uint8_t port_is_bonding_slave(portid_t slave_pid); 6930e545d30SBernard Iremonger 6941a572499SJingjing Wu int init_port_dcb_config(portid_t pid, enum dcb_mode_enable dcb_mode, 6951a572499SJingjing Wu enum rte_eth_nb_tcs num_tcs, 6961a572499SJingjing Wu uint8_t pfc_en); 697148f963fSBruce Richardson int start_port(portid_t pid); 698ce8d5614SIntel void stop_port(portid_t pid); 699ce8d5614SIntel void close_port(portid_t pid); 70097f1e196SWei Dai void reset_port(portid_t pid); 701edab33b1STetsuya Mukawa void attach_port(char *identifier); 70228caa76aSZhiyong Yang void detach_port(portid_t port_id); 703ce8d5614SIntel int all_ports_stopped(void); 7046018eb8cSShahaf Shuler int port_is_stopped(portid_t port_id); 7055f4ec54fSChen Jing D(Mark) int port_is_started(portid_t port_id); 706af75078fSIntel void pmd_test_exit(void); 707af75078fSIntel void fdir_get_infos(portid_t port_id); 708aeca06dfSJingjing Wu void fdir_set_flex_mask(portid_t port_id, 709aeca06dfSJingjing Wu struct rte_eth_fdir_flex_mask *cfg); 71097b74464SJingjing Wu void fdir_set_flex_payload(portid_t port_id, 71197b74464SJingjing Wu struct rte_eth_flex_payload_cfg *cfg); 71266c59490SHelin Zhang void port_rss_reta_info(portid_t port_id, 71366c59490SHelin Zhang struct rte_eth_rss_reta_entry64 *reta_conf, 71466c59490SHelin Zhang uint16_t nb_entries); 7156a18e1afSOuyang Changchun 7167741e4cfSIntel void set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on); 717af75078fSIntel 7186a18e1afSOuyang Changchun int set_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate); 7196a18e1afSOuyang Changchun int set_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate, 7206a18e1afSOuyang Changchun uint64_t q_msk); 7216a18e1afSOuyang Changchun 7228205e241SNelio Laranjeiro void port_rss_hash_conf_show(portid_t port_id, char rss_info[], 7238205e241SNelio Laranjeiro int show_rss_key); 7248205e241SNelio Laranjeiro void port_rss_hash_key_update(portid_t port_id, char rss_type[], 7258205e241SNelio Laranjeiro uint8_t *hash_key, uint hash_key_len); 7265f4ec54fSChen Jing D(Mark) int rx_queue_id_is_invalid(queueid_t rxq_id); 7275f4ec54fSChen Jing D(Mark) int tx_queue_id_is_invalid(queueid_t txq_id); 728b7091f1dSJiayu Hu void setup_gro(const char *onoff, portid_t port_id); 729b7091f1dSJiayu Hu void setup_gro_flush_cycles(uint8_t cycles); 730b7091f1dSJiayu Hu void show_gro(portid_t port_id); 73152f38a20SJiayu Hu void setup_gso(const char *mode, portid_t port_id); 73216321de0SIvan Boule 7338fff6675SIvan Boule /* Functions to manage the set of filtered Multicast MAC addresses */ 73428caa76aSZhiyong Yang void mcast_addr_add(portid_t port_id, struct ether_addr *mc_addr); 73528caa76aSZhiyong Yang void mcast_addr_remove(portid_t port_id, struct ether_addr *mc_addr); 73628caa76aSZhiyong Yang void port_dcb_info_display(portid_t port_id); 7378fff6675SIvan Boule 7389999dc6fSKirill Rybalchenko uint8_t *open_file(const char *file_path, uint32_t *size); 7399999dc6fSKirill Rybalchenko int save_file(const char *file_path, uint8_t *buf, uint32_t size); 7409999dc6fSKirill Rybalchenko int close_file(uint8_t *buf); 741a92a5a2cSBeilei Xing 7423c272b28SWei Zhao void port_queue_region_info_display(portid_t port_id, void *buf); 7433c272b28SWei Zhao 744edab33b1STetsuya Mukawa enum print_warning { 745edab33b1STetsuya Mukawa ENABLED_WARN = 0, 746edab33b1STetsuya Mukawa DISABLED_WARN 747edab33b1STetsuya Mukawa }; 748edab33b1STetsuya Mukawa int port_id_is_invalid(portid_t port_id, enum print_warning warning); 7498f3c4176SMatan Azrad void print_valid_ports(void); 750c9cafcc8SShahaf Shuler int new_socket_id(unsigned int socket_id); 751edab33b1STetsuya Mukawa 7523f7311baSWei Dai queueid_t get_allowed_max_nb_rxq(portid_t *pid); 7533f7311baSWei Dai int check_nb_rxq(queueid_t rxq); 75436db4f6cSWei Dai queueid_t get_allowed_max_nb_txq(portid_t *pid); 75536db4f6cSWei Dai int check_nb_txq(queueid_t txq); 7563f7311baSWei Dai 757af75078fSIntel /* 758af75078fSIntel * Work-around of a compilation error with ICC on invocations of the 759af75078fSIntel * rte_be_to_cpu_16() function. 760af75078fSIntel */ 761af75078fSIntel #ifdef __GCC__ 762af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) rte_be_to_cpu_16((be_16_v)) 763af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v)) 764af75078fSIntel #else 76544eb9456SThomas Monjalon #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 766af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) (be_16_v) 767af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v) 768af75078fSIntel #else 769af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \ 770af75078fSIntel (uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8)) 771af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \ 772af75078fSIntel (uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8)) 773af75078fSIntel #endif 774af75078fSIntel #endif /* __GCC__ */ 775af75078fSIntel 776285fd101SOlivier Matz #define TESTPMD_LOG(level, fmt, args...) \ 777285fd101SOlivier Matz rte_log(RTE_LOG_ ## level, testpmd_logtype, "testpmd: " fmt, ## args) 778285fd101SOlivier Matz 779af75078fSIntel #endif /* _TESTPMD_H_ */ 780