1174a1631SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 2174a1631SBruce Richardson * Copyright(c) 2010-2017 Intel Corporation 3af75078fSIntel */ 4af75078fSIntel 5af75078fSIntel #ifndef _TESTPMD_H_ 6af75078fSIntel #define _TESTPMD_H_ 7af75078fSIntel 84f1ed78eSThomas Monjalon #include <stdbool.h> 94f1ed78eSThomas Monjalon 1085c18dcbSGaetan Rivet #include <rte_pci.h> 11c752998bSGaetan Rivet #include <rte_bus_pci.h> 12b40f8d78SJiayu Hu #include <rte_gro.h> 1352f38a20SJiayu Hu #include <rte_gso.h> 1430626defSXiaoyu Min #include <cmdline.h> 151b9f2746SGregory Etelson #include <sys/queue.h> 1685c18dcbSGaetan Rivet 17ce8d5614SIntel #define RTE_PORT_ALL (~(portid_t)0x0) 18ce8d5614SIntel 19ce8d5614SIntel #define RTE_TEST_RX_DESC_MAX 2048 20ce8d5614SIntel #define RTE_TEST_TX_DESC_MAX 2048 21ce8d5614SIntel 22ce8d5614SIntel #define RTE_PORT_STOPPED (uint16_t)0 23ce8d5614SIntel #define RTE_PORT_STARTED (uint16_t)1 24ce8d5614SIntel #define RTE_PORT_CLOSED (uint16_t)2 25ce8d5614SIntel #define RTE_PORT_HANDLING (uint16_t)3 26ce8d5614SIntel 27af75078fSIntel /* 280f6f219eSMohammad Abdul Awal * It is used to allocate the memory for hash key. 290f6f219eSMohammad Abdul Awal * The hash key size is NIC dependent. 300f6f219eSMohammad Abdul Awal */ 310f6f219eSMohammad Abdul Awal #define RSS_HASH_KEY_LENGTH 64 320f6f219eSMohammad Abdul Awal 330f6f219eSMohammad Abdul Awal /* 34af75078fSIntel * Default size of the mbuf data buffer to receive standard 1518-byte 35af75078fSIntel * Ethernet frames in a mono-segment memory buffer. 36af75078fSIntel */ 37824cb29cSKonstantin Ananyev #define DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE 38824cb29cSKonstantin Ananyev /**< Default size of mbuf data buffer. */ 39af75078fSIntel 40af75078fSIntel /* 41af75078fSIntel * The maximum number of segments per packet is used when creating 42af75078fSIntel * scattered transmit packets composed of a list of mbufs. 43af75078fSIntel */ 44ea672a8bSOlivier Matz #define RTE_MAX_SEGS_PER_PKT 255 /**< nb_segs is a 8-bit unsigned char. */ 45af75078fSIntel 4626cbb419SViacheslav Ovsiienko /* 4726cbb419SViacheslav Ovsiienko * The maximum number of segments per packet is used to configure 4826cbb419SViacheslav Ovsiienko * buffer split feature, also specifies the maximum amount of 4926cbb419SViacheslav Ovsiienko * optional Rx pools to allocate mbufs to split. 5026cbb419SViacheslav Ovsiienko */ 5126cbb419SViacheslav Ovsiienko #define MAX_SEGS_BUFFER_SPLIT 8 /**< nb_segs is a 8-bit unsigned char. */ 5226cbb419SViacheslav Ovsiienko 5326cbb419SViacheslav Ovsiienko /* The prefix of the mbuf pool names created by the application. */ 5426cbb419SViacheslav Ovsiienko #define MBUF_POOL_NAME_PFX "mb_pool" 5526cbb419SViacheslav Ovsiienko 56af75078fSIntel #define MAX_PKT_BURST 512 57836853d3SCunming Liang #define DEF_PKT_BURST 32 58af75078fSIntel 59e9378bbcSCunming Liang #define DEF_MBUF_CACHE 250 60e9378bbcSCunming Liang 61fdf20fa7SSergio Gonzalez Monroy #define RTE_CACHE_LINE_SIZE_ROUNDUP(size) \ 62fdf20fa7SSergio Gonzalez Monroy (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) 63af75078fSIntel 64b6ea6408SIntel #define NUMA_NO_CONFIG 0xFF 65b6ea6408SIntel #define UMA_NO_CONFIG 0xFF 66b6ea6408SIntel 67af75078fSIntel typedef uint8_t lcoreid_t; 68f8244c63SZhiyong Yang typedef uint16_t portid_t; 69af75078fSIntel typedef uint16_t queueid_t; 70af75078fSIntel typedef uint16_t streamid_t; 71af75078fSIntel 72af75078fSIntel enum { 73af75078fSIntel PORT_TOPOLOGY_PAIRED, 743e2006d6SCyril Chemparathy PORT_TOPOLOGY_CHAINED, 753e2006d6SCyril Chemparathy PORT_TOPOLOGY_LOOP, 76af75078fSIntel }; 77af75078fSIntel 78c7f5dba7SAnatoly Burakov enum { 79c7f5dba7SAnatoly Burakov MP_ALLOC_NATIVE, /**< allocate and populate mempool natively */ 80c7f5dba7SAnatoly Burakov MP_ALLOC_ANON, 81c7f5dba7SAnatoly Burakov /**< allocate mempool natively, but populate using anonymous memory */ 82c7f5dba7SAnatoly Burakov MP_ALLOC_XMEM, 83c7f5dba7SAnatoly Burakov /**< allocate and populate mempool using anonymous memory */ 8472512e18SViacheslav Ovsiienko MP_ALLOC_XMEM_HUGE, 85c7f5dba7SAnatoly Burakov /**< allocate and populate mempool using anonymous hugepage memory */ 8672512e18SViacheslav Ovsiienko MP_ALLOC_XBUF 8772512e18SViacheslav Ovsiienko /**< allocate mempool natively, use rte_pktmbuf_pool_create_extbuf */ 88c7f5dba7SAnatoly Burakov }; 89c7f5dba7SAnatoly Burakov 90af75078fSIntel /** 91af75078fSIntel * The data structure associated with RX and TX packet burst statistics 92af75078fSIntel * that are recorded for each forwarding stream. 93af75078fSIntel */ 94af75078fSIntel struct pkt_burst_stats { 95af75078fSIntel unsigned int pkt_burst_spread[MAX_PKT_BURST]; 96af75078fSIntel }; 97af75078fSIntel 98f4d623f9SAdrien Mazarguil /** Information for a given RSS type. */ 99f4d623f9SAdrien Mazarguil struct rss_type_info { 100f4d623f9SAdrien Mazarguil const char *str; /**< Type name. */ 101f4d623f9SAdrien Mazarguil uint64_t rss_type; /**< Type value. */ 102f4d623f9SAdrien Mazarguil }; 103f4d623f9SAdrien Mazarguil 104f4d623f9SAdrien Mazarguil /** 105f4d623f9SAdrien Mazarguil * RSS type information table. 106f4d623f9SAdrien Mazarguil * 107f4d623f9SAdrien Mazarguil * An entry with a NULL type name terminates the list. 108f4d623f9SAdrien Mazarguil */ 109f4d623f9SAdrien Mazarguil extern const struct rss_type_info rss_type_table[]; 110f4d623f9SAdrien Mazarguil 111af75078fSIntel /** 112b57b66a9SOri Kam * Dynf name array. 113b57b66a9SOri Kam * 114b57b66a9SOri Kam * Array that holds the name for each dynf. 115b57b66a9SOri Kam */ 116b57b66a9SOri Kam extern char dynf_names[64][RTE_MBUF_DYN_NAMESIZE]; 117b57b66a9SOri Kam 118b57b66a9SOri Kam /** 119af75078fSIntel * The data structure associated with a forwarding stream between a receive 120af75078fSIntel * port/queue and a transmit port/queue. 121af75078fSIntel */ 122af75078fSIntel struct fwd_stream { 123af75078fSIntel /* "read-only" data */ 124af75078fSIntel portid_t rx_port; /**< port to poll for received packets */ 125af75078fSIntel queueid_t rx_queue; /**< RX queue to poll on "rx_port" */ 126af75078fSIntel portid_t tx_port; /**< forwarding port of received packets */ 127af75078fSIntel queueid_t tx_queue; /**< TX queue to send forwarded packets */ 128af75078fSIntel streamid_t peer_addr; /**< index of peer ethernet address of packets */ 129af75078fSIntel 130bf56fce1SZhihong Wang unsigned int retry_enabled; 131bf56fce1SZhihong Wang 132af75078fSIntel /* "read-write" results */ 133c185d42cSDavid Marchand uint64_t rx_packets; /**< received packets */ 134c185d42cSDavid Marchand uint64_t tx_packets; /**< received packets transmitted */ 135c185d42cSDavid Marchand uint64_t fwd_dropped; /**< received packets not forwarded */ 136c185d42cSDavid Marchand uint64_t rx_bad_ip_csum ; /**< received packets has bad ip checksum */ 137c185d42cSDavid Marchand uint64_t rx_bad_l4_csum ; /**< received packets has bad l4 checksum */ 138c185d42cSDavid Marchand uint64_t rx_bad_outer_l4_csum; 13958d475b7SJerin Jacob /**< received packets has bad outer l4 checksum */ 140d139cf23SLance Richardson uint64_t rx_bad_outer_ip_csum; 141d139cf23SLance Richardson /**< received packets having bad outer ip checksum */ 142b7091f1dSJiayu Hu unsigned int gro_times; /**< GRO operation times */ 143af75078fSIntel uint64_t core_cycles; /**< used for RX and TX processing */ 144af75078fSIntel struct pkt_burst_stats rx_burst_stats; 145af75078fSIntel struct pkt_burst_stats tx_burst_stats; 146af75078fSIntel }; 147af75078fSIntel 148de956d5eSMatan Azrad /** 149de956d5eSMatan Azrad * Age action context types, must be included inside the age action 150de956d5eSMatan Azrad * context structure. 151de956d5eSMatan Azrad */ 152de956d5eSMatan Azrad enum age_action_context_type { 153de956d5eSMatan Azrad ACTION_AGE_CONTEXT_TYPE_FLOW, 154de956d5eSMatan Azrad ACTION_AGE_CONTEXT_TYPE_SHARED_ACTION, 155de956d5eSMatan Azrad }; 156de956d5eSMatan Azrad 157938a184aSAdrien Mazarguil /** Descriptor for a single flow. */ 158938a184aSAdrien Mazarguil struct port_flow { 159938a184aSAdrien Mazarguil struct port_flow *next; /**< Next flow in list. */ 160938a184aSAdrien Mazarguil struct port_flow *tmp; /**< Temporary linking. */ 161938a184aSAdrien Mazarguil uint32_t id; /**< Flow rule ID. */ 162938a184aSAdrien Mazarguil struct rte_flow *flow; /**< Opaque flow object returned by PMD. */ 163de956d5eSMatan Azrad struct rte_flow_conv_rule rule; /**< Saved flow rule description. */ 164de956d5eSMatan Azrad enum age_action_context_type age_type; /**< Age action context type. */ 16544b257ffSAdrien Mazarguil uint8_t data[]; /**< Storage for flow rule description */ 166938a184aSAdrien Mazarguil }; 167938a184aSAdrien Mazarguil 16855509e3aSAndrey Vesnovaty /* Descriptor for shared action */ 16955509e3aSAndrey Vesnovaty struct port_shared_action { 17055509e3aSAndrey Vesnovaty struct port_shared_action *next; /**< Next flow in list. */ 17155509e3aSAndrey Vesnovaty uint32_t id; /**< Shared action ID. */ 17255509e3aSAndrey Vesnovaty enum rte_flow_action_type type; /**< Action type. */ 17355509e3aSAndrey Vesnovaty struct rte_flow_shared_action *action; /**< Shared action handle. */ 174de956d5eSMatan Azrad enum age_action_context_type age_type; /**< Age action context type. */ 17555509e3aSAndrey Vesnovaty }; 17655509e3aSAndrey Vesnovaty 1771b9f2746SGregory Etelson struct port_flow_tunnel { 1781b9f2746SGregory Etelson LIST_ENTRY(port_flow_tunnel) chain; 1791b9f2746SGregory Etelson struct rte_flow_action *pmd_actions; 1801b9f2746SGregory Etelson struct rte_flow_item *pmd_items; 1811b9f2746SGregory Etelson uint32_t id; 1821b9f2746SGregory Etelson uint32_t num_pmd_actions; 1831b9f2746SGregory Etelson uint32_t num_pmd_items; 1841b9f2746SGregory Etelson struct rte_flow_tunnel tunnel; 1851b9f2746SGregory Etelson struct rte_flow_action *actions; 1861b9f2746SGregory Etelson struct rte_flow_item *items; 1871b9f2746SGregory Etelson }; 1881b9f2746SGregory Etelson 1891b9f2746SGregory Etelson struct tunnel_ops { 1901b9f2746SGregory Etelson uint32_t id; 1911b9f2746SGregory Etelson char type[16]; 1921b9f2746SGregory Etelson uint32_t enabled:1; 1931b9f2746SGregory Etelson uint32_t actions:1; 1941b9f2746SGregory Etelson uint32_t items:1; 1951b9f2746SGregory Etelson }; 1961b9f2746SGregory Etelson 197af75078fSIntel /** 198af75078fSIntel * The data structure associated with each port. 199af75078fSIntel */ 200af75078fSIntel struct rte_port { 201af75078fSIntel struct rte_eth_dev_info dev_info; /**< PCI info + driver name */ 202af75078fSIntel struct rte_eth_conf dev_conf; /**< Port configuration. */ 2036d13ea8eSOlivier Matz struct rte_ether_addr eth_addr; /**< Port ethernet address */ 204af75078fSIntel struct rte_eth_stats stats; /**< Last port statistics */ 205af75078fSIntel unsigned int socket_id; /**< For NUMA support */ 2063eecba26SShahaf Shuler uint16_t parse_tunnel:1; /**< Parse internal headers */ 2070f62d635SJianfeng Tan uint16_t tso_segsz; /**< Segmentation offload MSS for non-tunneled packets. */ 2080f62d635SJianfeng Tan uint16_t tunnel_tso_segsz; /**< Segmentation offload MSS for tunneled pkts. */ 20992ebda07SHelin Zhang uint16_t tx_vlan_id;/**< The tag ID */ 21092ebda07SHelin Zhang uint16_t tx_vlan_id_outer;/**< The outer tag ID */ 211ce8d5614SIntel volatile uint16_t port_status; /**< port started or not */ 2124f1ed78eSThomas Monjalon uint8_t need_setup; /**< port just attached */ 213ce8d5614SIntel uint8_t need_reconfig; /**< need reconfiguring port or not */ 214ce8d5614SIntel uint8_t need_reconfig_queues; /**< need reconfiguring queues or not */ 215ce8d5614SIntel uint8_t rss_flag; /**< enable rss or not */ 2167741e4cfSIntel uint8_t dcb_flag; /**< enable dcb */ 2179e6b36c3SDavid Marchand uint16_t nb_rx_desc[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue rx desc number */ 2189e6b36c3SDavid Marchand uint16_t nb_tx_desc[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue tx desc number */ 2199e6b36c3SDavid Marchand struct rte_eth_rxconf rx_conf[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue rx configuration */ 2209e6b36c3SDavid Marchand struct rte_eth_txconf tx_conf[RTE_MAX_QUEUES_PER_PORT+1]; /**< per queue tx configuration */ 2216d13ea8eSOlivier Matz struct rte_ether_addr *mc_addr_pool; /**< pool of multicast addrs */ 2228fff6675SIvan Boule uint32_t mc_addr_nb; /**< nb. of addr. in mc_addr_pool */ 22341b05095SBernard Iremonger uint8_t slave_flag; /**< bonding slave port */ 224938a184aSAdrien Mazarguil struct port_flow *flow_list; /**< Associated flows. */ 22555509e3aSAndrey Vesnovaty struct port_shared_action *actions_list; 22655509e3aSAndrey Vesnovaty /**< Associated shared actions. */ 2271b9f2746SGregory Etelson LIST_HEAD(, port_flow_tunnel) flow_tunnel_list; 2289e6b36c3SDavid Marchand const struct rte_eth_rxtx_callback *rx_dump_cb[RTE_MAX_QUEUES_PER_PORT+1]; 2299e6b36c3SDavid Marchand const struct rte_eth_rxtx_callback *tx_dump_cb[RTE_MAX_QUEUES_PER_PORT+1]; 230c18feafaSDekel Peled /**< metadata value to insert in Tx packets. */ 2319bf26e13SViacheslav Ovsiienko uint32_t tx_metadata; 2329e6b36c3SDavid Marchand const struct rte_eth_rxtx_callback *tx_set_md_cb[RTE_MAX_QUEUES_PER_PORT+1]; 233b57b66a9SOri Kam /**< dynamic flags. */ 234b57b66a9SOri Kam uint64_t mbuf_dynf; 235b57b66a9SOri Kam const struct rte_eth_rxtx_callback *tx_set_dynf_cb[RTE_MAX_QUEUES_PER_PORT+1]; 236af75078fSIntel }; 237af75078fSIntel 238af75078fSIntel /** 239af75078fSIntel * The data structure associated with each forwarding logical core. 240af75078fSIntel * The logical cores are internally numbered by a core index from 0 to 241af75078fSIntel * the maximum number of logical cores - 1. 242af75078fSIntel * The system CPU identifier of all logical cores are setup in a global 243af75078fSIntel * CPU id. configuration table. 244af75078fSIntel */ 245af75078fSIntel struct fwd_lcore { 24652f38a20SJiayu Hu struct rte_gso_ctx gso_ctx; /**< GSO context */ 247af75078fSIntel struct rte_mempool *mbp; /**< The mbuf pool to use by this core */ 248b7091f1dSJiayu Hu void *gro_ctx; /**< GRO context */ 249af75078fSIntel streamid_t stream_idx; /**< index of 1st stream in "fwd_streams" */ 250af75078fSIntel streamid_t stream_nb; /**< number of streams in "fwd_streams" */ 251af75078fSIntel lcoreid_t cpuid_idx; /**< index of logical core in CPU id table */ 252af75078fSIntel volatile char stopped; /**< stop forwarding when set */ 253af75078fSIntel }; 254af75078fSIntel 255af75078fSIntel /* 256af75078fSIntel * Forwarding mode operations: 257af75078fSIntel * - IO forwarding mode (default mode) 258af75078fSIntel * Forwards packets unchanged. 259af75078fSIntel * 260af75078fSIntel * - MAC forwarding mode 261af75078fSIntel * Set the source and the destination Ethernet addresses of packets 262af75078fSIntel * before forwarding them. 263af75078fSIntel * 264af75078fSIntel * - IEEE1588 forwarding mode 265af75078fSIntel * Check that received IEEE1588 Precise Time Protocol (PTP) packets are 266af75078fSIntel * filtered and timestamped by the hardware. 267af75078fSIntel * Forwards packets unchanged on the same port. 268af75078fSIntel * Check that sent IEEE1588 PTP packets are timestamped by the hardware. 269af75078fSIntel */ 270af75078fSIntel typedef void (*port_fwd_begin_t)(portid_t pi); 271af75078fSIntel typedef void (*port_fwd_end_t)(portid_t pi); 272af75078fSIntel typedef void (*packet_fwd_t)(struct fwd_stream *fs); 273af75078fSIntel 274af75078fSIntel struct fwd_engine { 275af75078fSIntel const char *fwd_mode_name; /**< Forwarding mode name. */ 276af75078fSIntel port_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */ 277af75078fSIntel port_fwd_end_t port_fwd_end; /**< NULL if nothing special to do. */ 278af75078fSIntel packet_fwd_t packet_fwd; /**< Mandatory. */ 279af75078fSIntel }; 280af75078fSIntel 281bf56fce1SZhihong Wang #define BURST_TX_WAIT_US 1 282bf56fce1SZhihong Wang #define BURST_TX_RETRIES 64 283bf56fce1SZhihong Wang 284bf56fce1SZhihong Wang extern uint32_t burst_tx_delay_time; 285bf56fce1SZhihong Wang extern uint32_t burst_tx_retry_num; 286bf56fce1SZhihong Wang 287af75078fSIntel extern struct fwd_engine io_fwd_engine; 288af75078fSIntel extern struct fwd_engine mac_fwd_engine; 289d47388f1SCyril Chemparathy extern struct fwd_engine mac_swap_engine; 290e9e23a61SCyril Chemparathy extern struct fwd_engine flow_gen_engine; 291af75078fSIntel extern struct fwd_engine rx_only_engine; 292af75078fSIntel extern struct fwd_engine tx_only_engine; 293af75078fSIntel extern struct fwd_engine csum_fwd_engine; 294168dfa61SIvan Boule extern struct fwd_engine icmp_echo_engine; 2953c156061SJens Freimann extern struct fwd_engine noisy_vnf_engine; 2962564abdaSShiri Kuzin extern struct fwd_engine five_tuple_swap_fwd_engine; 297af75078fSIntel #ifdef RTE_LIBRTE_IEEE1588 298af75078fSIntel extern struct fwd_engine ieee1588_fwd_engine; 299af75078fSIntel #endif 300af75078fSIntel 301af75078fSIntel extern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */ 30230626defSXiaoyu Min extern cmdline_parse_inst_t cmd_set_raw; 303739e045bSXiaoyu Min extern cmdline_parse_inst_t cmd_show_set_raw; 304739e045bSXiaoyu Min extern cmdline_parse_inst_t cmd_show_set_raw_all; 305af75078fSIntel 30659fcf854SShahaf Shuler extern uint16_t mempool_flags; 30759fcf854SShahaf Shuler 308af75078fSIntel /** 309af75078fSIntel * Forwarding Configuration 310af75078fSIntel * 311af75078fSIntel */ 312af75078fSIntel struct fwd_config { 313af75078fSIntel struct fwd_engine *fwd_eng; /**< Packet forwarding mode. */ 314af75078fSIntel streamid_t nb_fwd_streams; /**< Nb. of forward streams to process. */ 315af75078fSIntel lcoreid_t nb_fwd_lcores; /**< Nb. of logical cores to launch. */ 316af75078fSIntel portid_t nb_fwd_ports; /**< Nb. of ports involved. */ 317af75078fSIntel }; 318af75078fSIntel 319900550deSIntel /** 320900550deSIntel * DCB mode enable 321900550deSIntel */ 322900550deSIntel enum dcb_mode_enable 323900550deSIntel { 324900550deSIntel DCB_VT_ENABLED, 325900550deSIntel DCB_ENABLED 326900550deSIntel }; 327900550deSIntel 328a4fd5eeeSElza Mathew extern uint8_t xstats_hide_zero; /**< Hide zero values for xstats display */ 329a4fd5eeeSElza Mathew 330af75078fSIntel /* globals used for configuration */ 331bc700b67SDharmik Thakkar extern uint8_t record_core_cycles; /**< Enables measurement of CPU cycles */ 3320e4b1963SDharmik Thakkar extern uint8_t record_burst_stats; /**< Enables display of RX and TX bursts */ 333af75078fSIntel extern uint16_t verbose_level; /**< Drives messages being displayed, if any. */ 334285fd101SOlivier Matz extern int testpmd_logtype; /**< Log type for testpmd logs */ 335af75078fSIntel extern uint8_t interactive; 336ca7feb22SCyril Chemparathy extern uint8_t auto_start; 33799cabef0SPablo de Lara extern uint8_t tx_first; 33881ef862bSAllain Legacy extern char cmdline_filename[PATH_MAX]; /**< offline commands file */ 339af75078fSIntel extern uint8_t numa_support; /**< set by "--numa" parameter */ 340af75078fSIntel extern uint16_t port_topology; /**< set by "--port-topology" parameter */ 3417741e4cfSIntel extern uint8_t no_flush_rx; /**<set by "--no-flush-rx" parameter */ 3427ee3e944SVasily Philipov extern uint8_t flow_isolate_all; /**< set by "--flow-isolate-all */ 343c7f5dba7SAnatoly Burakov extern uint8_t mp_alloc_type; 344c7f5dba7SAnatoly Burakov /**< set by "--mp-anon" or "--mp-alloc" parameter */ 345*b7b78a08SAjit Khaparde extern uint32_t eth_link_speed; 346bc202406SDavid Marchand extern uint8_t no_link_check; /**<set by "--disable-link-check" parameter */ 3476937d210SStephen Hemminger extern uint8_t no_device_start; /**<set by "--disable-device-start" parameter */ 3482950a769SDeclan Doherty extern volatile int test_done; /* stop packet forwarding when set to 1. */ 3498ea656f8SGaetan Rivet extern uint8_t lsc_interrupt; /**< disabled by "--no-lsc-interrupt" parameter */ 350284c908cSGaetan Rivet extern uint8_t rmv_interrupt; /**< disabled by "--no-rmv-interrupt" parameter */ 3513af72783SGaetan Rivet extern uint32_t event_print_mask; 3523af72783SGaetan Rivet /**< set by "--print-event xxxx" and "--mask-event xxxx parameters */ 3534f1ed78eSThomas Monjalon extern bool setup_on_probe_event; /**< disabled by port setup-on iterator */ 354e505d84cSAnatoly Burakov extern uint8_t hot_plug; /**< enable by "--hot-plug" parameter */ 355e505d84cSAnatoly Burakov extern int do_mlockall; /**< set by "--mlockall" or "--no-mlockall" parameter */ 356b0a9354aSPavan Nikhilesh extern uint8_t clear_ptypes; /**< disabled by set ptype cmd */ 357af75078fSIntel 358e261265eSRadu Nicolau #ifdef RTE_LIBRTE_IXGBE_BYPASS 3597b7e5ba7SIntel extern uint32_t bypass_timeout; /**< Store the NIC bypass watchdog timeout */ 3607b7e5ba7SIntel #endif 3617b7e5ba7SIntel 362b6ea6408SIntel /* 363b6ea6408SIntel * Store specified sockets on which memory pool to be used by ports 364b6ea6408SIntel * is allocated. 365b6ea6408SIntel */ 36663531389SGeorgios Katsikas extern uint8_t port_numa[RTE_MAX_ETHPORTS]; 367b6ea6408SIntel 368b6ea6408SIntel /* 369b6ea6408SIntel * Store specified sockets on which RX ring to be used by ports 370b6ea6408SIntel * is allocated. 371b6ea6408SIntel */ 37263531389SGeorgios Katsikas extern uint8_t rxring_numa[RTE_MAX_ETHPORTS]; 373b6ea6408SIntel 374b6ea6408SIntel /* 375b6ea6408SIntel * Store specified sockets on which TX ring to be used by ports 376b6ea6408SIntel * is allocated. 377b6ea6408SIntel */ 37863531389SGeorgios Katsikas extern uint8_t txring_numa[RTE_MAX_ETHPORTS]; 379b6ea6408SIntel 380b6ea6408SIntel extern uint8_t socket_num; 381b6ea6408SIntel 382af75078fSIntel /* 383af75078fSIntel * Configuration of logical cores: 384af75078fSIntel * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores 385af75078fSIntel */ 386af75078fSIntel extern lcoreid_t nb_lcores; /**< Number of logical cores probed at init time. */ 387af75078fSIntel extern lcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */ 388af75078fSIntel extern lcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */ 389af75078fSIntel extern unsigned int fwd_lcores_cpuids[RTE_MAX_LCORE]; 390c9cafcc8SShahaf Shuler extern unsigned int num_sockets; 391c9cafcc8SShahaf Shuler extern unsigned int socket_ids[RTE_MAX_NUMA_NODES]; 392af75078fSIntel 393af75078fSIntel /* 394af75078fSIntel * Configuration of Ethernet ports: 395af75078fSIntel * nb_fwd_ports <= nb_cfg_ports <= nb_ports 396af75078fSIntel */ 397af75078fSIntel extern portid_t nb_ports; /**< Number of ethernet ports probed at init time. */ 398af75078fSIntel extern portid_t nb_cfg_ports; /**< Number of configured ports. */ 399af75078fSIntel extern portid_t nb_fwd_ports; /**< Number of forwarding ports. */ 400af75078fSIntel extern portid_t fwd_ports_ids[RTE_MAX_ETHPORTS]; 401af75078fSIntel extern struct rte_port *ports; 402af75078fSIntel 403af75078fSIntel extern struct rte_eth_rxmode rx_mode; 404fd8c20aaSShahaf Shuler extern struct rte_eth_txmode tx_mode; 405fd8c20aaSShahaf Shuler 4068a387fa8SHelin Zhang extern uint64_t rss_hf; 407af75078fSIntel 4081c69df45SOri Kam extern queueid_t nb_hairpinq; 409af75078fSIntel extern queueid_t nb_rxq; 410af75078fSIntel extern queueid_t nb_txq; 411af75078fSIntel 412af75078fSIntel extern uint16_t nb_rxd; 413af75078fSIntel extern uint16_t nb_txd; 414af75078fSIntel 415f2c5125aSPablo de Lara extern int16_t rx_free_thresh; 416f2c5125aSPablo de Lara extern int8_t rx_drop_en; 417f2c5125aSPablo de Lara extern int16_t tx_free_thresh; 418f2c5125aSPablo de Lara extern int16_t tx_rs_thresh; 419af75078fSIntel 4203c156061SJens Freimann extern uint16_t noisy_tx_sw_bufsz; 4213c156061SJens Freimann extern uint16_t noisy_tx_sw_buf_flush_time; 4223c156061SJens Freimann extern uint64_t noisy_lkup_mem_sz; 4233c156061SJens Freimann extern uint64_t noisy_lkup_num_writes; 4243c156061SJens Freimann extern uint64_t noisy_lkup_num_reads; 4253c156061SJens Freimann extern uint64_t noisy_lkup_num_reads_writes; 4263c156061SJens Freimann 427900550deSIntel extern uint8_t dcb_config; 428900550deSIntel extern uint8_t dcb_test; 429900550deSIntel 43026cbb419SViacheslav Ovsiienko extern uint32_t mbuf_data_size_n; 43126cbb419SViacheslav Ovsiienko extern uint16_t mbuf_data_size[MAX_SEGS_BUFFER_SPLIT]; 43226cbb419SViacheslav Ovsiienko /**< Mbuf data space size. */ 433c8798818SIntel extern uint32_t param_total_num_mbufs; 434af75078fSIntel 435cfea1f30SPablo de Lara extern uint16_t stats_period; 43662d3216dSReshma Pattan 43701817b10SBing Zhao extern uint16_t hairpin_mode; 43801817b10SBing Zhao 439a8d0d473SBruce Richardson #ifdef RTE_LIB_LATENCYSTATS 44062d3216dSReshma Pattan extern uint8_t latencystats_enabled; 44162d3216dSReshma Pattan extern lcoreid_t latencystats_lcore_id; 44262d3216dSReshma Pattan #endif 44362d3216dSReshma Pattan 444a8d0d473SBruce Richardson #ifdef RTE_LIB_BITRATESTATS 445e25e6c70SRemy Horton extern lcoreid_t bitrate_lcore_id; 446e25e6c70SRemy Horton extern uint8_t bitrate_enabled; 447e25e6c70SRemy Horton #endif 448e25e6c70SRemy Horton 449af75078fSIntel extern struct rte_fdir_conf fdir_conf; 450af75078fSIntel 451af75078fSIntel /* 4520f2096d7SViacheslav Ovsiienko * Configuration of packet segments used to scatter received packets 4530f2096d7SViacheslav Ovsiienko * if some of split features is configured. 4540f2096d7SViacheslav Ovsiienko */ 4550f2096d7SViacheslav Ovsiienko extern uint16_t rx_pkt_seg_lengths[MAX_SEGS_BUFFER_SPLIT]; 4560f2096d7SViacheslav Ovsiienko extern uint8_t rx_pkt_nb_segs; /**< Number of segments to split */ 45791c78e09SViacheslav Ovsiienko extern uint16_t rx_pkt_seg_offsets[MAX_SEGS_BUFFER_SPLIT]; 45891c78e09SViacheslav Ovsiienko extern uint8_t rx_pkt_nb_offs; /**< Number of specified offsets */ 4590f2096d7SViacheslav Ovsiienko 4600f2096d7SViacheslav Ovsiienko /* 461af75078fSIntel * Configuration of packet segments used by the "txonly" processing engine. 462af75078fSIntel */ 463af75078fSIntel #define TXONLY_DEF_PACKET_LEN 64 464af75078fSIntel extern uint16_t tx_pkt_length; /**< Length of TXONLY packet */ 465af75078fSIntel extern uint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT]; /**< Seg. lengths */ 466af75078fSIntel extern uint8_t tx_pkt_nb_segs; /**< Number of segments in TX packets */ 4674940344dSViacheslav Ovsiienko extern uint32_t tx_pkt_times_intra; 4684940344dSViacheslav Ovsiienko extern uint32_t tx_pkt_times_inter; 469af75078fSIntel 47079bec05bSKonstantin Ananyev enum tx_pkt_split { 47179bec05bSKonstantin Ananyev TX_PKT_SPLIT_OFF, 47279bec05bSKonstantin Ananyev TX_PKT_SPLIT_ON, 47379bec05bSKonstantin Ananyev TX_PKT_SPLIT_RND, 47479bec05bSKonstantin Ananyev }; 47579bec05bSKonstantin Ananyev 47679bec05bSKonstantin Ananyev extern enum tx_pkt_split tx_pkt_split; 47779bec05bSKonstantin Ananyev 47882010ef5SYongseok Koh extern uint8_t txonly_multi_flow; 47982010ef5SYongseok Koh 480af75078fSIntel extern uint16_t nb_pkt_per_burst; 4816c02043eSIgor Russkikh extern uint16_t nb_pkt_flowgen_clones; 482af75078fSIntel extern uint16_t mb_mempool_cache; 483f2c5125aSPablo de Lara extern int8_t rx_pthresh; 484f2c5125aSPablo de Lara extern int8_t rx_hthresh; 485f2c5125aSPablo de Lara extern int8_t rx_wthresh; 486f2c5125aSPablo de Lara extern int8_t tx_pthresh; 487f2c5125aSPablo de Lara extern int8_t tx_hthresh; 488f2c5125aSPablo de Lara extern int8_t tx_wthresh; 489af75078fSIntel 490bf5b2126SStephen Hemminger extern uint16_t tx_udp_src_port; 491bf5b2126SStephen Hemminger extern uint16_t tx_udp_dst_port; 492bf5b2126SStephen Hemminger 493bf5b2126SStephen Hemminger extern uint32_t tx_ip_src_addr; 494bf5b2126SStephen Hemminger extern uint32_t tx_ip_dst_addr; 495bf5b2126SStephen Hemminger 496af75078fSIntel extern struct fwd_config cur_fwd_config; 497af75078fSIntel extern struct fwd_engine *cur_fwd_eng; 498bf56fce1SZhihong Wang extern uint32_t retry_enabled; 499af75078fSIntel extern struct fwd_lcore **fwd_lcores; 500af75078fSIntel extern struct fwd_stream **fwd_streams; 501af75078fSIntel 50239e5e20fSXueming Li extern uint16_t vxlan_gpe_udp_port; /**< UDP port of tunnel VXLAN-GPE. */ 503ea0e711bSOphir Munk extern uint16_t geneve_udp_port; /**< UDP port of tunnel GENEVE. */ 50439e5e20fSXueming Li 505af75078fSIntel extern portid_t nb_peer_eth_addrs; /**< Number of peer ethernet addresses. */ 5066d13ea8eSOlivier Matz extern struct rte_ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS]; 507af75078fSIntel 50857e85242SBruce Richardson extern uint32_t burst_tx_delay_time; /**< Burst tx delay time(us) for mac-retry. */ 50957e85242SBruce Richardson extern uint32_t burst_tx_retry_num; /**< Burst tx retry number for mac-retry. */ 51057e85242SBruce Richardson 511b7091f1dSJiayu Hu #define GRO_DEFAULT_ITEM_NUM_PER_FLOW 32 512b7091f1dSJiayu Hu #define GRO_DEFAULT_FLOW_NUM (RTE_GRO_MAX_BURST_ITEM_NUM / \ 513b7091f1dSJiayu Hu GRO_DEFAULT_ITEM_NUM_PER_FLOW) 514b7091f1dSJiayu Hu 515b7091f1dSJiayu Hu #define GRO_DEFAULT_FLUSH_CYCLES 1 516b7091f1dSJiayu Hu #define GRO_MAX_FLUSH_CYCLES 4 517b7091f1dSJiayu Hu 518b40f8d78SJiayu Hu struct gro_status { 519b40f8d78SJiayu Hu struct rte_gro_param param; 520b40f8d78SJiayu Hu uint8_t enable; 521b40f8d78SJiayu Hu }; 522b40f8d78SJiayu Hu extern struct gro_status gro_ports[RTE_MAX_ETHPORTS]; 523b7091f1dSJiayu Hu extern uint8_t gro_flush_cycles; 524b40f8d78SJiayu Hu 52552f38a20SJiayu Hu #define GSO_MAX_PKT_BURST 2048 52652f38a20SJiayu Hu struct gso_status { 52752f38a20SJiayu Hu uint8_t enable; 52852f38a20SJiayu Hu }; 52952f38a20SJiayu Hu extern struct gso_status gso_ports[RTE_MAX_ETHPORTS]; 53052f38a20SJiayu Hu extern uint16_t gso_max_segment_size; 53152f38a20SJiayu Hu 5321960be7dSNelio Laranjeiro /* VXLAN encap/decap parameters. */ 5331960be7dSNelio Laranjeiro struct vxlan_encap_conf { 5341960be7dSNelio Laranjeiro uint32_t select_ipv4:1; 5351960be7dSNelio Laranjeiro uint32_t select_vlan:1; 53662e8a5a8SViacheslav Ovsiienko uint32_t select_tos_ttl:1; 5371960be7dSNelio Laranjeiro uint8_t vni[3]; 5381960be7dSNelio Laranjeiro rte_be16_t udp_src; 5391960be7dSNelio Laranjeiro rte_be16_t udp_dst; 5401960be7dSNelio Laranjeiro rte_be32_t ipv4_src; 5411960be7dSNelio Laranjeiro rte_be32_t ipv4_dst; 5421960be7dSNelio Laranjeiro uint8_t ipv6_src[16]; 5431960be7dSNelio Laranjeiro uint8_t ipv6_dst[16]; 5441960be7dSNelio Laranjeiro rte_be16_t vlan_tci; 54562e8a5a8SViacheslav Ovsiienko uint8_t ip_tos; 54662e8a5a8SViacheslav Ovsiienko uint8_t ip_ttl; 54735b2d13fSOlivier Matz uint8_t eth_src[RTE_ETHER_ADDR_LEN]; 54835b2d13fSOlivier Matz uint8_t eth_dst[RTE_ETHER_ADDR_LEN]; 5491960be7dSNelio Laranjeiro }; 550f6e63e59SFerruh Yigit 551f6e63e59SFerruh Yigit extern struct vxlan_encap_conf vxlan_encap_conf; 5521960be7dSNelio Laranjeiro 553dcd962fcSNelio Laranjeiro /* NVGRE encap/decap parameters. */ 554dcd962fcSNelio Laranjeiro struct nvgre_encap_conf { 555dcd962fcSNelio Laranjeiro uint32_t select_ipv4:1; 556dcd962fcSNelio Laranjeiro uint32_t select_vlan:1; 557dcd962fcSNelio Laranjeiro uint8_t tni[3]; 558dcd962fcSNelio Laranjeiro rte_be32_t ipv4_src; 559dcd962fcSNelio Laranjeiro rte_be32_t ipv4_dst; 560dcd962fcSNelio Laranjeiro uint8_t ipv6_src[16]; 561dcd962fcSNelio Laranjeiro uint8_t ipv6_dst[16]; 562dcd962fcSNelio Laranjeiro rte_be16_t vlan_tci; 56335b2d13fSOlivier Matz uint8_t eth_src[RTE_ETHER_ADDR_LEN]; 56435b2d13fSOlivier Matz uint8_t eth_dst[RTE_ETHER_ADDR_LEN]; 565dcd962fcSNelio Laranjeiro }; 566f6e63e59SFerruh Yigit 567f6e63e59SFerruh Yigit extern struct nvgre_encap_conf nvgre_encap_conf; 568dcd962fcSNelio Laranjeiro 569a1191d39SOri Kam /* L2 encap parameters. */ 570a1191d39SOri Kam struct l2_encap_conf { 571a1191d39SOri Kam uint32_t select_ipv4:1; 572a1191d39SOri Kam uint32_t select_vlan:1; 573a1191d39SOri Kam rte_be16_t vlan_tci; 57435b2d13fSOlivier Matz uint8_t eth_src[RTE_ETHER_ADDR_LEN]; 57535b2d13fSOlivier Matz uint8_t eth_dst[RTE_ETHER_ADDR_LEN]; 576a1191d39SOri Kam }; 577f6e63e59SFerruh Yigit extern struct l2_encap_conf l2_encap_conf; 578a1191d39SOri Kam 579a1191d39SOri Kam /* L2 decap parameters. */ 580a1191d39SOri Kam struct l2_decap_conf { 581a1191d39SOri Kam uint32_t select_vlan:1; 582a1191d39SOri Kam }; 583f6e63e59SFerruh Yigit extern struct l2_decap_conf l2_decap_conf; 584a1191d39SOri Kam 5853e77031bSOri Kam /* MPLSoGRE encap parameters. */ 5863e77031bSOri Kam struct mplsogre_encap_conf { 5873e77031bSOri Kam uint32_t select_ipv4:1; 5883e77031bSOri Kam uint32_t select_vlan:1; 5893e77031bSOri Kam uint8_t label[3]; 5903e77031bSOri Kam rte_be32_t ipv4_src; 5913e77031bSOri Kam rte_be32_t ipv4_dst; 5923e77031bSOri Kam uint8_t ipv6_src[16]; 5933e77031bSOri Kam uint8_t ipv6_dst[16]; 5943e77031bSOri Kam rte_be16_t vlan_tci; 59535b2d13fSOlivier Matz uint8_t eth_src[RTE_ETHER_ADDR_LEN]; 59635b2d13fSOlivier Matz uint8_t eth_dst[RTE_ETHER_ADDR_LEN]; 5973e77031bSOri Kam }; 598f6e63e59SFerruh Yigit extern struct mplsogre_encap_conf mplsogre_encap_conf; 5993e77031bSOri Kam 6003e77031bSOri Kam /* MPLSoGRE decap parameters. */ 6013e77031bSOri Kam struct mplsogre_decap_conf { 6023e77031bSOri Kam uint32_t select_ipv4:1; 6033e77031bSOri Kam uint32_t select_vlan:1; 6043e77031bSOri Kam }; 605f6e63e59SFerruh Yigit extern struct mplsogre_decap_conf mplsogre_decap_conf; 6063e77031bSOri Kam 607a1191d39SOri Kam /* MPLSoUDP encap parameters. */ 608a1191d39SOri Kam struct mplsoudp_encap_conf { 609a1191d39SOri Kam uint32_t select_ipv4:1; 610a1191d39SOri Kam uint32_t select_vlan:1; 611a1191d39SOri Kam uint8_t label[3]; 612a1191d39SOri Kam rte_be16_t udp_src; 613a1191d39SOri Kam rte_be16_t udp_dst; 614a1191d39SOri Kam rte_be32_t ipv4_src; 615a1191d39SOri Kam rte_be32_t ipv4_dst; 616a1191d39SOri Kam uint8_t ipv6_src[16]; 617a1191d39SOri Kam uint8_t ipv6_dst[16]; 618a1191d39SOri Kam rte_be16_t vlan_tci; 61935b2d13fSOlivier Matz uint8_t eth_src[RTE_ETHER_ADDR_LEN]; 62035b2d13fSOlivier Matz uint8_t eth_dst[RTE_ETHER_ADDR_LEN]; 621a1191d39SOri Kam }; 622f6e63e59SFerruh Yigit extern struct mplsoudp_encap_conf mplsoudp_encap_conf; 623a1191d39SOri Kam 624a1191d39SOri Kam /* MPLSoUDP decap parameters. */ 625a1191d39SOri Kam struct mplsoudp_decap_conf { 626a1191d39SOri Kam uint32_t select_ipv4:1; 627a1191d39SOri Kam uint32_t select_vlan:1; 628a1191d39SOri Kam }; 629f6e63e59SFerruh Yigit extern struct mplsoudp_decap_conf mplsoudp_decap_conf; 630a1191d39SOri Kam 631f9295aa2SXiaoyu Min extern enum rte_eth_rx_mq_mode rx_mq_mode; 632f9295aa2SXiaoyu Min 633af75078fSIntel static inline unsigned int 634af75078fSIntel lcore_num(void) 635af75078fSIntel { 636af75078fSIntel unsigned int i; 637af75078fSIntel 638af75078fSIntel for (i = 0; i < RTE_MAX_LCORE; ++i) 639af75078fSIntel if (fwd_lcores_cpuids[i] == rte_lcore_id()) 640af75078fSIntel return i; 641af75078fSIntel 642af75078fSIntel rte_panic("lcore_id of current thread not found in fwd_lcores_cpuids\n"); 643af75078fSIntel } 644af75078fSIntel 6452df00d56SHariprasad Govindharajan void 6462df00d56SHariprasad Govindharajan parse_fwd_portlist(const char *port); 6472df00d56SHariprasad Govindharajan 648af75078fSIntel static inline struct fwd_lcore * 649af75078fSIntel current_fwd_lcore(void) 650af75078fSIntel { 651af75078fSIntel return fwd_lcores[lcore_num()]; 652af75078fSIntel } 653af75078fSIntel 654af75078fSIntel /* Mbuf Pools */ 655af75078fSIntel static inline void 65626cbb419SViacheslav Ovsiienko mbuf_poolname_build(unsigned int sock_id, char *mp_name, 65726cbb419SViacheslav Ovsiienko int name_size, uint16_t idx) 658af75078fSIntel { 65926cbb419SViacheslav Ovsiienko if (!idx) 66026cbb419SViacheslav Ovsiienko snprintf(mp_name, name_size, 66126cbb419SViacheslav Ovsiienko MBUF_POOL_NAME_PFX "_%u", sock_id); 66226cbb419SViacheslav Ovsiienko else 66326cbb419SViacheslav Ovsiienko snprintf(mp_name, name_size, 66426cbb419SViacheslav Ovsiienko MBUF_POOL_NAME_PFX "_%hu_%hu", (uint16_t)sock_id, idx); 665af75078fSIntel } 666af75078fSIntel 667af75078fSIntel static inline struct rte_mempool * 66826cbb419SViacheslav Ovsiienko mbuf_pool_find(unsigned int sock_id, uint16_t idx) 669af75078fSIntel { 670af75078fSIntel char pool_name[RTE_MEMPOOL_NAMESIZE]; 671af75078fSIntel 67226cbb419SViacheslav Ovsiienko mbuf_poolname_build(sock_id, pool_name, sizeof(pool_name), idx); 673693f715dSHuawei Xie return rte_mempool_lookup((const char *)pool_name); 674af75078fSIntel } 675af75078fSIntel 676af75078fSIntel /** 677af75078fSIntel * Read/Write operations on a PCI register of a port. 678af75078fSIntel */ 679af75078fSIntel static inline uint32_t 680af75078fSIntel port_pci_reg_read(struct rte_port *port, uint32_t reg_off) 681af75078fSIntel { 682cd8c7c7cSFerruh Yigit const struct rte_pci_device *pci_dev; 683cd8c7c7cSFerruh Yigit const struct rte_bus *bus; 684af75078fSIntel void *reg_addr; 685af75078fSIntel uint32_t reg_v; 686af75078fSIntel 687cd8c7c7cSFerruh Yigit if (!port->dev_info.device) { 688cd8c7c7cSFerruh Yigit printf("Invalid device\n"); 689cd8c7c7cSFerruh Yigit return 0; 690cd8c7c7cSFerruh Yigit } 691cd8c7c7cSFerruh Yigit 692cd8c7c7cSFerruh Yigit bus = rte_bus_find_by_device(port->dev_info.device); 693cd8c7c7cSFerruh Yigit if (bus && !strcmp(bus->name, "pci")) { 694cd8c7c7cSFerruh Yigit pci_dev = RTE_DEV_TO_PCI(port->dev_info.device); 695cd8c7c7cSFerruh Yigit } else { 696cd8c7c7cSFerruh Yigit printf("Not a PCI device\n"); 697cd8c7c7cSFerruh Yigit return 0; 698cd8c7c7cSFerruh Yigit } 699cd8c7c7cSFerruh Yigit 700cd8c7c7cSFerruh Yigit reg_addr = ((char *)pci_dev->mem_resource[0].addr + reg_off); 701af75078fSIntel reg_v = *((volatile uint32_t *)reg_addr); 702af75078fSIntel return rte_le_to_cpu_32(reg_v); 703af75078fSIntel } 704af75078fSIntel 705af75078fSIntel #define port_id_pci_reg_read(pt_id, reg_off) \ 706af75078fSIntel port_pci_reg_read(&ports[(pt_id)], (reg_off)) 707af75078fSIntel 708af75078fSIntel static inline void 709af75078fSIntel port_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v) 710af75078fSIntel { 711cd8c7c7cSFerruh Yigit const struct rte_pci_device *pci_dev; 712cd8c7c7cSFerruh Yigit const struct rte_bus *bus; 713af75078fSIntel void *reg_addr; 714af75078fSIntel 715cd8c7c7cSFerruh Yigit if (!port->dev_info.device) { 716cd8c7c7cSFerruh Yigit printf("Invalid device\n"); 717cd8c7c7cSFerruh Yigit return; 718cd8c7c7cSFerruh Yigit } 719cd8c7c7cSFerruh Yigit 720cd8c7c7cSFerruh Yigit bus = rte_bus_find_by_device(port->dev_info.device); 721cd8c7c7cSFerruh Yigit if (bus && !strcmp(bus->name, "pci")) { 722cd8c7c7cSFerruh Yigit pci_dev = RTE_DEV_TO_PCI(port->dev_info.device); 723cd8c7c7cSFerruh Yigit } else { 724cd8c7c7cSFerruh Yigit printf("Not a PCI device\n"); 725cd8c7c7cSFerruh Yigit return; 726cd8c7c7cSFerruh Yigit } 727cd8c7c7cSFerruh Yigit 728cd8c7c7cSFerruh Yigit reg_addr = ((char *)pci_dev->mem_resource[0].addr + reg_off); 729af75078fSIntel *((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v); 730af75078fSIntel } 731af75078fSIntel 732af75078fSIntel #define port_id_pci_reg_write(pt_id, reg_off, reg_value) \ 733af75078fSIntel port_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value)) 734af75078fSIntel 735bc700b67SDharmik Thakkar static inline void 736bc700b67SDharmik Thakkar get_start_cycles(uint64_t *start_tsc) 737bc700b67SDharmik Thakkar { 738bc700b67SDharmik Thakkar if (record_core_cycles) 739bc700b67SDharmik Thakkar *start_tsc = rte_rdtsc(); 740bc700b67SDharmik Thakkar } 741bc700b67SDharmik Thakkar 742bc700b67SDharmik Thakkar static inline void 743bc700b67SDharmik Thakkar get_end_cycles(struct fwd_stream *fs, uint64_t start_tsc) 744bc700b67SDharmik Thakkar { 745bc700b67SDharmik Thakkar if (record_core_cycles) 746bc700b67SDharmik Thakkar fs->core_cycles += rte_rdtsc() - start_tsc; 747bc700b67SDharmik Thakkar } 748bc700b67SDharmik Thakkar 7490e4b1963SDharmik Thakkar static inline void 7500e4b1963SDharmik Thakkar inc_rx_burst_stats(struct fwd_stream *fs, uint16_t nb_rx) 7510e4b1963SDharmik Thakkar { 7520e4b1963SDharmik Thakkar if (record_burst_stats) 7530e4b1963SDharmik Thakkar fs->rx_burst_stats.pkt_burst_spread[nb_rx]++; 7540e4b1963SDharmik Thakkar } 7550e4b1963SDharmik Thakkar 7560e4b1963SDharmik Thakkar static inline void 7570e4b1963SDharmik Thakkar inc_tx_burst_stats(struct fwd_stream *fs, uint16_t nb_tx) 7580e4b1963SDharmik Thakkar { 7590e4b1963SDharmik Thakkar if (record_burst_stats) 7600e4b1963SDharmik Thakkar fs->tx_burst_stats.pkt_burst_spread[nb_tx]++; 7610e4b1963SDharmik Thakkar } 7620e4b1963SDharmik Thakkar 763af75078fSIntel /* Prototypes */ 764950d1516SBruce Richardson unsigned int parse_item_list(char* str, const char* item_name, 765950d1516SBruce Richardson unsigned int max_items, 766950d1516SBruce Richardson unsigned int *parsed_items, int check_unique_values); 767af75078fSIntel void launch_args_parse(int argc, char** argv); 76881ef862bSAllain Legacy void cmdline_read_from_file(const char *filename); 769af75078fSIntel void prompt(void); 770d3a274ceSZhihong Wang void prompt_exit(void); 771af75078fSIntel void nic_stats_display(portid_t port_id); 772af75078fSIntel void nic_stats_clear(portid_t port_id); 773bfd5051bSOlivier Matz void nic_xstats_display(portid_t port_id); 774bfd5051bSOlivier Matz void nic_xstats_clear(portid_t port_id); 77555e51c96SNithin Dabilpuram void device_infos_display(const char *identifier); 776af75078fSIntel void port_infos_display(portid_t port_id); 7774bfcbcf5SEmma Finn void port_summary_display(portid_t port_id); 7786b67721dSDavid Liu void port_eeprom_display(portid_t port_id); 7796b67721dSDavid Liu void port_module_eeprom_display(portid_t port_id); 7804bfcbcf5SEmma Finn void port_summary_header_display(void); 781ab3257e1SKonstantin Ananyev void rx_queue_infos_display(portid_t port_idi, uint16_t queue_id); 782ab3257e1SKonstantin Ananyev void tx_queue_infos_display(portid_t port_idi, uint16_t queue_id); 783af75078fSIntel void fwd_lcores_config_display(void); 7840c0db76fSBernard Iremonger void pkt_fwd_config_display(struct fwd_config *cfg); 785af75078fSIntel void rxtx_config_display(void); 786af75078fSIntel void fwd_config_setup(void); 787af75078fSIntel void set_def_fwd_config(void); 788a21d5a4bSDeclan Doherty void reconfig(portid_t new_port_id, unsigned socket_id); 789013af9b6SIntel int init_fwd_streams(void); 79003ce2c53SMatan Azrad void update_fwd_ports(portid_t new_pid); 791013af9b6SIntel 792aac6f11fSWisam Jaddo void set_fwd_eth_peer(portid_t port_id, char *peer_addr); 793aac6f11fSWisam Jaddo 794ae03d0d1SIvan Boule void port_mtu_set(portid_t port_id, uint16_t mtu); 795af75078fSIntel void port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos); 796af75078fSIntel void port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos, 797af75078fSIntel uint8_t bit_v); 798af75078fSIntel void port_reg_bit_field_display(portid_t port_id, uint32_t reg_off, 799af75078fSIntel uint8_t bit1_pos, uint8_t bit2_pos); 800af75078fSIntel void port_reg_bit_field_set(portid_t port_id, uint32_t reg_off, 801af75078fSIntel uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value); 802af75078fSIntel void port_reg_display(portid_t port_id, uint32_t reg_off); 803af75078fSIntel void port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value); 80455509e3aSAndrey Vesnovaty int port_shared_action_create(portid_t port_id, uint32_t id, 80555509e3aSAndrey Vesnovaty const struct rte_flow_shared_action_conf *conf, 80655509e3aSAndrey Vesnovaty const struct rte_flow_action *action); 80755509e3aSAndrey Vesnovaty int port_shared_action_destroy(portid_t port_id, 80855509e3aSAndrey Vesnovaty uint32_t n, const uint32_t *action); 80955509e3aSAndrey Vesnovaty struct rte_flow_shared_action *port_shared_action_get_by_id(portid_t port_id, 81055509e3aSAndrey Vesnovaty uint32_t id); 81155509e3aSAndrey Vesnovaty int port_shared_action_update(portid_t port_id, uint32_t id, 81255509e3aSAndrey Vesnovaty const struct rte_flow_action *action); 813938a184aSAdrien Mazarguil int port_flow_validate(portid_t port_id, 814938a184aSAdrien Mazarguil const struct rte_flow_attr *attr, 815938a184aSAdrien Mazarguil const struct rte_flow_item *pattern, 8161b9f2746SGregory Etelson const struct rte_flow_action *actions, 8171b9f2746SGregory Etelson const struct tunnel_ops *tunnel_ops); 818938a184aSAdrien Mazarguil int port_flow_create(portid_t port_id, 819938a184aSAdrien Mazarguil const struct rte_flow_attr *attr, 820938a184aSAdrien Mazarguil const struct rte_flow_item *pattern, 8211b9f2746SGregory Etelson const struct rte_flow_action *actions, 8221b9f2746SGregory Etelson const struct tunnel_ops *tunnel_ops); 82355509e3aSAndrey Vesnovaty int port_shared_action_query(portid_t port_id, uint32_t id); 8240e459ffaSDong Zhou void update_age_action_context(const struct rte_flow_action *actions, 8250e459ffaSDong Zhou struct port_flow *pf); 826938a184aSAdrien Mazarguil int port_flow_destroy(portid_t port_id, uint32_t n, const uint32_t *rule); 827938a184aSAdrien Mazarguil int port_flow_flush(portid_t port_id); 8281e8a4e97SXueming Li int port_flow_dump(portid_t port_id, const char *file_name); 829938a184aSAdrien Mazarguil int port_flow_query(portid_t port_id, uint32_t rule, 830fb8fd96dSDeclan Doherty const struct rte_flow_action *action); 831938a184aSAdrien Mazarguil void port_flow_list(portid_t port_id, uint32_t n, const uint32_t *group); 8320e459ffaSDong Zhou void port_flow_aged(portid_t port_id, uint8_t destroy); 8331b9f2746SGregory Etelson const char *port_flow_tunnel_type(struct rte_flow_tunnel *tunnel); 8341b9f2746SGregory Etelson struct port_flow_tunnel * 8351b9f2746SGregory Etelson port_flow_locate_tunnel(uint16_t port_id, struct rte_flow_tunnel *tun); 8361b9f2746SGregory Etelson void port_flow_tunnel_list(portid_t port_id); 8371b9f2746SGregory Etelson void port_flow_tunnel_destroy(portid_t port_id, uint32_t tunnel_id); 8381b9f2746SGregory Etelson void port_flow_tunnel_create(portid_t port_id, const struct tunnel_ops *ops); 839323f811aSAdrien Mazarguil int port_flow_isolate(portid_t port_id, int set); 840af75078fSIntel 841af75078fSIntel void rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id); 842af75078fSIntel void tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id); 843af75078fSIntel 844013af9b6SIntel int set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc); 845013af9b6SIntel int set_fwd_lcores_mask(uint64_t lcoremask); 846af75078fSIntel void set_fwd_lcores_number(uint16_t nb_lc); 847af75078fSIntel 848af75078fSIntel void set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt); 849af75078fSIntel void set_fwd_ports_mask(uint64_t portmask); 850af75078fSIntel void set_fwd_ports_number(uint16_t nb_pt); 851a8ef3e3aSBernard Iremonger int port_is_forwarding(portid_t port_id); 852af75078fSIntel 853a47aa8b9SIntel void rx_vlan_strip_set(portid_t port_id, int on); 854a47aa8b9SIntel void rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on); 855a47aa8b9SIntel 856a47aa8b9SIntel void rx_vlan_filter_set(portid_t port_id, int on); 857af75078fSIntel void rx_vlan_all_filter_set(portid_t port_id, int on); 8582a0b4198SVivek Sharma void rx_vlan_qinq_strip_set(portid_t port_id, int on); 85964b01ee0SMichal Jastrzebski int rx_vft_set(portid_t port_id, uint16_t vlan_id, int on); 860a47aa8b9SIntel void vlan_extend_set(portid_t port_id, int on); 86119b16e2fSHelin Zhang void vlan_tpid_set(portid_t port_id, enum rte_vlan_type vlan_type, 86219b16e2fSHelin Zhang uint16_t tp_id); 863af75078fSIntel void tx_vlan_set(portid_t port_id, uint16_t vlan_id); 86492ebda07SHelin Zhang void tx_qinq_set(portid_t port_id, uint16_t vlan_id, uint16_t vlan_id_outer); 865af75078fSIntel void tx_vlan_reset(portid_t port_id); 866529ba951SHelin Zhang void tx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on); 867ed30d9b6SIntel 868ed30d9b6SIntel void set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value); 869ed30d9b6SIntel 870a4fd5eeeSElza Mathew void set_xstats_hide_zero(uint8_t on_off); 871a4fd5eeeSElza Mathew 872bc700b67SDharmik Thakkar void set_record_core_cycles(uint8_t on_off); 8730e4b1963SDharmik Thakkar void set_record_burst_stats(uint8_t on_off); 874af75078fSIntel void set_verbose_level(uint16_t vb_level); 8750f2096d7SViacheslav Ovsiienko void set_rx_pkt_segments(unsigned int *seg_lengths, unsigned int nb_segs); 8760f2096d7SViacheslav Ovsiienko void show_rx_pkt_segments(void); 87791c78e09SViacheslav Ovsiienko void set_rx_pkt_offsets(unsigned int *seg_offsets, unsigned int nb_offs); 87891c78e09SViacheslav Ovsiienko void show_rx_pkt_offsets(void); 8790f2096d7SViacheslav Ovsiienko void set_tx_pkt_segments(unsigned int *seg_lengths, unsigned int nb_segs); 88079bec05bSKonstantin Ananyev void show_tx_pkt_segments(void); 8814940344dSViacheslav Ovsiienko void set_tx_pkt_times(unsigned int *tx_times); 8824940344dSViacheslav Ovsiienko void show_tx_pkt_times(void); 88379bec05bSKonstantin Ananyev void set_tx_pkt_split(const char *name); 884b19da32eSMin Hu (Connor) int parse_fec_mode(const char *name, enum rte_eth_fec_mode *mode); 885b19da32eSMin Hu (Connor) void show_fec_capability(uint32_t num, struct rte_eth_fec_capa *speed_fec_capa); 886af75078fSIntel void set_nb_pkt_per_burst(uint16_t pkt_burst); 887769ce6b1SThomas Monjalon char *list_pkt_forwarding_modes(void); 888bf56fce1SZhihong Wang char *list_pkt_forwarding_retry_modes(void); 889af75078fSIntel void set_pkt_forwarding_mode(const char *fwd_mode); 890af75078fSIntel void start_packet_forwarding(int with_tx_first); 89153324971SDavid Marchand void fwd_stats_display(void); 89253324971SDavid Marchand void fwd_stats_reset(void); 893af75078fSIntel void stop_packet_forwarding(void); 894cfae07fdSOuyang Changchun void dev_set_link_up(portid_t pid); 895cfae07fdSOuyang Changchun void dev_set_link_down(portid_t pid); 896ce8d5614SIntel void init_port_config(void); 89741b05095SBernard Iremonger void set_port_slave_flag(portid_t slave_pid); 89841b05095SBernard Iremonger void clear_port_slave_flag(portid_t slave_pid); 8990e545d30SBernard Iremonger uint8_t port_is_bonding_slave(portid_t slave_pid); 9000e545d30SBernard Iremonger 9011a572499SJingjing Wu int init_port_dcb_config(portid_t pid, enum dcb_mode_enable dcb_mode, 9021a572499SJingjing Wu enum rte_eth_nb_tcs num_tcs, 9031a572499SJingjing Wu uint8_t pfc_en); 904148f963fSBruce Richardson int start_port(portid_t pid); 905ce8d5614SIntel void stop_port(portid_t pid); 906ce8d5614SIntel void close_port(portid_t pid); 90797f1e196SWei Dai void reset_port(portid_t pid); 908edab33b1STetsuya Mukawa void attach_port(char *identifier); 9095edee5f6SThomas Monjalon void detach_devargs(char *identifier); 910f8e5baa2SThomas Monjalon void detach_port_device(portid_t port_id); 911ce8d5614SIntel int all_ports_stopped(void); 9126018eb8cSShahaf Shuler int port_is_stopped(portid_t port_id); 9135f4ec54fSChen Jing D(Mark) int port_is_started(portid_t port_id); 914af75078fSIntel void pmd_test_exit(void); 9151be514fbSAndrew Rybchenko #if defined(RTE_NET_I40E) || defined(RTE_NET_IXGBE) 916af75078fSIntel void fdir_get_infos(portid_t port_id); 9171be514fbSAndrew Rybchenko #endif 918aeca06dfSJingjing Wu void fdir_set_flex_mask(portid_t port_id, 919aeca06dfSJingjing Wu struct rte_eth_fdir_flex_mask *cfg); 92097b74464SJingjing Wu void fdir_set_flex_payload(portid_t port_id, 92197b74464SJingjing Wu struct rte_eth_flex_payload_cfg *cfg); 92266c59490SHelin Zhang void port_rss_reta_info(portid_t port_id, 92366c59490SHelin Zhang struct rte_eth_rss_reta_entry64 *reta_conf, 92466c59490SHelin Zhang uint16_t nb_entries); 9256a18e1afSOuyang Changchun 9267741e4cfSIntel void set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on); 927af75078fSIntel 9282befc67fSViacheslav Ovsiienko int 9292befc67fSViacheslav Ovsiienko rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, 9302befc67fSViacheslav Ovsiienko uint16_t nb_rx_desc, unsigned int socket_id, 9312befc67fSViacheslav Ovsiienko struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp); 9322befc67fSViacheslav Ovsiienko 9336a18e1afSOuyang Changchun int set_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate); 9346a18e1afSOuyang Changchun int set_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate, 9356a18e1afSOuyang Changchun uint64_t q_msk); 9366a18e1afSOuyang Changchun 9375b4557ecSFerruh Yigit void port_rss_hash_conf_show(portid_t port_id, int show_rss_key); 9388205e241SNelio Laranjeiro void port_rss_hash_key_update(portid_t port_id, char rss_type[], 9398205e241SNelio Laranjeiro uint8_t *hash_key, uint hash_key_len); 9405f4ec54fSChen Jing D(Mark) int rx_queue_id_is_invalid(queueid_t rxq_id); 9415f4ec54fSChen Jing D(Mark) int tx_queue_id_is_invalid(queueid_t txq_id); 942b7091f1dSJiayu Hu void setup_gro(const char *onoff, portid_t port_id); 943b7091f1dSJiayu Hu void setup_gro_flush_cycles(uint8_t cycles); 944b7091f1dSJiayu Hu void show_gro(portid_t port_id); 94552f38a20SJiayu Hu void setup_gso(const char *mode, portid_t port_id); 9466f51deb9SIvan Ilchenko int eth_dev_info_get_print_err(uint16_t port_id, 9476f51deb9SIvan Ilchenko struct rte_eth_dev_info *dev_info); 94834fc1051SIvan Ilchenko void eth_set_promisc_mode(uint16_t port_id, int enable); 9498835806dSIvan Ilchenko void eth_set_allmulticast_mode(uint16_t port, int enable); 950e661a08bSIgor Romanov int eth_link_get_nowait_print_err(uint16_t port_id, struct rte_eth_link *link); 951a5279d25SIgor Romanov int eth_macaddr_get_print_err(uint16_t port_id, 952a5279d25SIgor Romanov struct rte_ether_addr *mac_addr); 9536f51deb9SIvan Ilchenko 954e1d44d0aSKalesh AP /* Functions to display the set of MAC addresses added to a port*/ 955e1d44d0aSKalesh AP void show_macs(portid_t port_id); 956e1d44d0aSKalesh AP void show_mcast_macs(portid_t port_id); 95716321de0SIvan Boule 9588fff6675SIvan Boule /* Functions to manage the set of filtered Multicast MAC addresses */ 9596d13ea8eSOlivier Matz void mcast_addr_add(portid_t port_id, struct rte_ether_addr *mc_addr); 9606d13ea8eSOlivier Matz void mcast_addr_remove(portid_t port_id, struct rte_ether_addr *mc_addr); 96128caa76aSZhiyong Yang void port_dcb_info_display(portid_t port_id); 9628fff6675SIvan Boule 9639999dc6fSKirill Rybalchenko uint8_t *open_file(const char *file_path, uint32_t *size); 9649999dc6fSKirill Rybalchenko int save_file(const char *file_path, uint8_t *buf, uint32_t size); 9659999dc6fSKirill Rybalchenko int close_file(uint8_t *buf); 966a92a5a2cSBeilei Xing 9673c272b28SWei Zhao void port_queue_region_info_display(portid_t port_id, void *buf); 9683c272b28SWei Zhao 969edab33b1STetsuya Mukawa enum print_warning { 970edab33b1STetsuya Mukawa ENABLED_WARN = 0, 971edab33b1STetsuya Mukawa DISABLED_WARN 972edab33b1STetsuya Mukawa }; 973edab33b1STetsuya Mukawa int port_id_is_invalid(portid_t port_id, enum print_warning warning); 9748f3c4176SMatan Azrad void print_valid_ports(void); 975c9cafcc8SShahaf Shuler int new_socket_id(unsigned int socket_id); 976edab33b1STetsuya Mukawa 9773f7311baSWei Dai queueid_t get_allowed_max_nb_rxq(portid_t *pid); 9783f7311baSWei Dai int check_nb_rxq(queueid_t rxq); 97936db4f6cSWei Dai queueid_t get_allowed_max_nb_txq(portid_t *pid); 98036db4f6cSWei Dai int check_nb_txq(queueid_t txq); 98199e040d3SLijun Ou int check_nb_rxd(queueid_t rxd); 98299e040d3SLijun Ou int check_nb_txd(queueid_t txd); 9831c69df45SOri Kam queueid_t get_allowed_max_nb_hairpinq(portid_t *pid); 9841c69df45SOri Kam int check_nb_hairpinq(queueid_t hairpinq); 9853f7311baSWei Dai 986c77ad9deSRaslan Darawsheh uint16_t dump_rx_pkts(uint16_t port_id, uint16_t queue, struct rte_mbuf *pkts[], 987c77ad9deSRaslan Darawsheh uint16_t nb_pkts, __rte_unused uint16_t max_pkts, 988c77ad9deSRaslan Darawsheh __rte_unused void *user_param); 989c77ad9deSRaslan Darawsheh 990c77ad9deSRaslan Darawsheh uint16_t dump_tx_pkts(uint16_t port_id, uint16_t queue, struct rte_mbuf *pkts[], 991c77ad9deSRaslan Darawsheh uint16_t nb_pkts, __rte_unused void *user_param); 992c77ad9deSRaslan Darawsheh 993c77ad9deSRaslan Darawsheh void add_rx_dump_callbacks(portid_t portid); 994c77ad9deSRaslan Darawsheh void remove_rx_dump_callbacks(portid_t portid); 995c77ad9deSRaslan Darawsheh void add_tx_dump_callbacks(portid_t portid); 996c77ad9deSRaslan Darawsheh void remove_tx_dump_callbacks(portid_t portid); 997b5b38ed8SRaslan Darawsheh void configure_rxtx_dump_callbacks(uint16_t verbose); 998d862c45bSRaslan Darawsheh 9991e45c908SDekel Peled uint16_t tx_pkt_set_md(uint16_t port_id, __rte_unused uint16_t queue, 10001e45c908SDekel Peled struct rte_mbuf *pkts[], uint16_t nb_pkts, 10011e45c908SDekel Peled __rte_unused void *user_param); 10021e45c908SDekel Peled void add_tx_md_callback(portid_t portid); 10031e45c908SDekel Peled void remove_tx_md_callback(portid_t portid); 10041e45c908SDekel Peled 1005b57b66a9SOri Kam uint16_t tx_pkt_set_dynf(uint16_t port_id, __rte_unused uint16_t queue, 1006b57b66a9SOri Kam struct rte_mbuf *pkts[], uint16_t nb_pkts, 1007b57b66a9SOri Kam __rte_unused void *user_param); 1008b57b66a9SOri Kam void add_tx_dynf_callback(portid_t portid); 1009b57b66a9SOri Kam void remove_tx_dynf_callback(portid_t portid); 10100c4abd36SSteve Yang int update_jumbo_frame_offload(portid_t portid); 1011b57b66a9SOri Kam 1012af75078fSIntel /* 1013af75078fSIntel * Work-around of a compilation error with ICC on invocations of the 1014af75078fSIntel * rte_be_to_cpu_16() function. 1015af75078fSIntel */ 1016af75078fSIntel #ifdef __GCC__ 1017af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) rte_be_to_cpu_16((be_16_v)) 1018af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v)) 1019af75078fSIntel #else 102044eb9456SThomas Monjalon #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN 1021af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) (be_16_v) 1022af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v) 1023af75078fSIntel #else 1024af75078fSIntel #define RTE_BE_TO_CPU_16(be_16_v) \ 1025af75078fSIntel (uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8)) 1026af75078fSIntel #define RTE_CPU_TO_BE_16(cpu_16_v) \ 1027af75078fSIntel (uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8)) 1028af75078fSIntel #endif 1029af75078fSIntel #endif /* __GCC__ */ 1030af75078fSIntel 1031285fd101SOlivier Matz #define TESTPMD_LOG(level, fmt, args...) \ 1032285fd101SOlivier Matz rte_log(RTE_LOG_ ## level, testpmd_logtype, "testpmd: " fmt, ## args) 1033285fd101SOlivier Matz 1034af75078fSIntel #endif /* _TESTPMD_H_ */ 1035